JPH1032252A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JPH1032252A
JPH1032252A JP8655997A JP8655997A JPH1032252A JP H1032252 A JPH1032252 A JP H1032252A JP 8655997 A JP8655997 A JP 8655997A JP 8655997 A JP8655997 A JP 8655997A JP H1032252 A JPH1032252 A JP H1032252A
Authority
JP
Japan
Prior art keywords
gate electrode
insulating film
film
conductive film
contact hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8655997A
Other languages
Japanese (ja)
Other versions
JP2828089B2 (en
Inventor
Masahiro Takeuchi
正浩 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP9086559A priority Critical patent/JP2828089B2/en
Publication of JPH1032252A publication Critical patent/JPH1032252A/en
Application granted granted Critical
Publication of JP2828089B2 publication Critical patent/JP2828089B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

(57)【要約】 【解決手段】導電型の半導体基板5の表面上に絶縁膜3
を形成し、つづいて多結晶シリコン膜とシリコン酸化膜
を形成する。次に、不要なシリコン酸化膜および多結晶
シリコン膜を除去して、シリコン酸化膜6とゲート電極
1,2を形成する。次に不純物をイオン注入して、不純
物層4を形成し、シリコン酸化膜7を形成後、シリコン
酸化膜7および絶縁膜3を除去しコンタクトホール8を
形成する。ゲート電極1またはゲート電極2の側面には
サイドウオール10が形成され、次に金属電極9を形成
する。 【効果】ゲート電極1とコンタクトホール8およびコン
タクトホール8とゲート電極2との間の余裕を減らすこ
とができ微細化できる。
(57) Abstract: An insulating film (3) is formed on a surface of a conductive type semiconductor substrate (5).
Is formed, and then a polycrystalline silicon film and a silicon oxide film are formed. Next, unnecessary silicon oxide films and polycrystalline silicon films are removed to form silicon oxide films 6 and gate electrodes 1 and 2. Next, an impurity is ion-implanted to form an impurity layer 4, and a silicon oxide film 7 is formed. Then, the silicon oxide film 7 and the insulating film 3 are removed to form a contact hole 8. A sidewall 10 is formed on the side surface of the gate electrode 1 or the gate electrode 2, and then a metal electrode 9 is formed. The margin between the gate electrode 1 and the contact hole 8 and the margin between the contact hole 8 and the gate electrode 2 can be reduced, and miniaturization can be achieved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は絶縁ゲート型トラン
ジスタを有する半導体装置に関する。特に基板とのコン
タクトの構造に関するものである。
The present invention relates to a semiconductor device having an insulated gate transistor. In particular, it relates to a structure of a contact with a substrate.

【0002】〔発明の概要〕本発明は、絶縁ゲート型ト
ランジスタを有する半導体装置の製造方法において、第
一のゲート電極と第二のゲート電極間にコンタクトホー
ルを形成し、このコンタクトホールに導電膜を接続する
場合、第一のゲート電極および第二のゲート電極上に第
一の絶縁膜を形成し、その上に第二の絶縁膜を形成する
ことにより、マスク合わせ工程でのコンタクトホールと
ゲート電極との間の合わせずれが生じても、コンタクト
ホールに接続された導電膜とゲート電極との間の短絡を
防ぐことができるようにしたものである。また、下層の
導電膜上に2層の絶縁膜を残すようにコンタクトホール
を形成し、下層の導電膜上に延在する2層の絶縁膜を介
して上層の導電膜を延在させることにより、たとえ基板
と上層の導電膜とのコンタクトを取るためにオーバーエ
ッチングをしたとしても上層の導電膜と下層の導電膜と
のリークの心配がなく、高い信頼性を得ることができる
ものである。
SUMMARY OF THE INVENTION According to the present invention, in a method of manufacturing a semiconductor device having an insulated gate transistor, a contact hole is formed between a first gate electrode and a second gate electrode, and a conductive film is formed in the contact hole. Are connected, a first insulating film is formed on the first gate electrode and the second gate electrode, and a second insulating film is formed thereon, so that the contact hole and the gate in the mask alignment step are formed. Even if misalignment with the electrode occurs, a short circuit between the conductive film connected to the contact hole and the gate electrode can be prevented. Further, by forming a contact hole so as to leave two insulating films over the lower conductive film and extending the upper conductive film via the two insulating films extending over the lower conductive film, Even if overetching is performed to make contact between the substrate and the upper conductive film, there is no fear of leakage between the upper conductive film and the lower conductive film, and high reliability can be obtained.

【0003】[0003]

【従来の技術】従来の半導体装置の製造方法を図2を用
いて説明する。図2(a)において、第一の導電型の半
導体基板上に絶縁膜3を形成し、つづいて化学的気相成
長法を用いて多結晶シリコン層を形成し、写真触刻法に
より不要部分を除去して、多結晶シリコンによるゲート
電極1,2を形成する。次にこのゲート電極をマスクと
して第2導電型の不純物をイオン注入した後アニールす
ることにより、第2導電型の不純物層4を形成する。次
に図2(b)のように第一のシリコン酸化膜7を形成し
た後、図2(c)のように写真触刻法によりコンタクト
ホール8を形成する。その後金属電極9を形成する。
2. Description of the Related Art A conventional method for manufacturing a semiconductor device will be described with reference to FIG. In FIG. 2A, an insulating film 3 is formed on a semiconductor substrate of a first conductivity type, a polycrystalline silicon layer is formed by using a chemical vapor deposition method, and unnecessary portions are formed by photolithography. Is removed to form gate electrodes 1 and 2 of polycrystalline silicon. Next, using this gate electrode as a mask, a second conductivity type impurity is ion-implanted and then annealed to form a second conductivity type impurity layer 4. Next, after forming a first silicon oxide film 7 as shown in FIG. 2B, a contact hole 8 is formed by photolithography as shown in FIG. 2C. Thereafter, a metal electrode 9 is formed.

【0004】[0004]

【発明が解決しようとする課題】しかし前述の従来技術
では、ゲート電極1,2を形成するマスクと、コンタク
トホール7を形成するマスクのマスクずれが生じた場
合、ゲート電極1又はゲート電極2と金属電極9が短絡
してしまうため、ゲート電極1とコンタクトホール8お
よびコンタクトホール8とゲート電極2との間に十分余
裕をとる必要があり、微細化しにくい問題があった。そ
こで本発明はこのような問題点を解決するもので、その
目的とするところは、ゲート電極1とコンタクトホール
8、およびコンタクトホール8とゲート電極2との間に
十分余裕をとらなくとも、ゲート電極1またはゲート電
極2と金属電極9が短絡しない半導体装置を提供すると
ころにある。
However, in the above-mentioned prior art, when the masks for forming the gate electrodes 1 and 2 and the mask for forming the contact holes 7 are misaligned, the gate electrode 1 or the gate electrode 2 cannot be moved. Since the metal electrode 9 is short-circuited, it is necessary to provide a sufficient margin between the gate electrode 1 and the contact hole 8 and between the contact hole 8 and the gate electrode 2, and there is a problem that it is difficult to miniaturize. Therefore, the present invention solves such a problem, and an object of the present invention is to provide a gate electrode without a sufficient margin between the gate electrode 1 and the contact hole 8 and between the contact hole 8 and the gate electrode 2. An object of the present invention is to provide a semiconductor device in which the electrode 1 or the gate electrode 2 and the metal electrode 9 are not short-circuited.

【0005】[0005]

【課題を解決するための手段】本発明の半導体装置は、
半導体基板上に設けられた第1絶縁膜、前記第1絶縁膜
上に互いに離間して設けられた第1導電膜及び第2導電
膜、前記第1導電膜と前記第2導電膜とに挟まれた前記
半導体基板中に設けられた不純物拡散層、前記第1導電
膜及び前記第2導電膜と同じ幅を有する第2絶縁膜、前
記第1絶縁膜上、および少なくとも前記第2絶縁膜上に
おいて全面にわたって設けられた第3絶縁膜、前記第3
絶縁膜上に延在し設けられた第3導電膜、前記第3導電
膜と前記不純物拡散層を電気的に接続させるための前記
不純物拡散層上の前記第3絶縁膜に設けられたコンタク
トを有することを特徴とする。
According to the present invention, there is provided a semiconductor device comprising:
A first insulating film provided on a semiconductor substrate, a first conductive film and a second conductive film provided separately on the first insulating film, and sandwiched between the first conductive film and the second conductive film; An impurity diffusion layer provided in the semiconductor substrate, a second insulating film having the same width as the first conductive film and the second conductive film, on the first insulating film, and at least on the second insulating film. A third insulating film provided over the entire surface in
A third conductive film extending over the insulating film; and a contact provided on the third insulating film on the impurity diffusion layer for electrically connecting the third conductive film to the impurity diffusion layer. It is characterized by having.

【0006】[0006]

【発明の実施の形態】図1(a)〜(C)は本発明の実
施例を示す図である。
1A to 1C are views showing an embodiment of the present invention.

【0007】以下図を参照しながら詳細に説明する。図
1(a)において、第一の導電型の半導体基板5の表面
上に第一の絶縁膜3を形成し、つづいて第一の導電膜た
とえば多結晶シリコン膜を形成し、次に第二の絶縁膜た
とえばシリコン酸化膜を形成する。次に写真触刻法によ
り、不要なシリコン酸化膜および多結晶シリコン膜を除
去して、シリコン酸化膜6と多結晶シリコン1,2から
なるゲート電極を形成する。この時、フォトレジストを
マスクとして第二の絶縁膜をエッチングし、この後フォ
トレジストを除去してから第二の絶縁膜をマスクとして
第一の導電膜をエッチングしてもよい。次にこのゲート
電極をマスクとして第二導電型の不純物をイオン注入し
た後、アニールすることにより第二導電型の不純物層4
を形成する。次に図1(b)のように第三の絶縁膜たと
えばシリコン酸化膜7を形成後、少なくとも前記シリコ
ン酸化膜6上の表面には前記シリコン酸化膜7が残るよ
うに、写真触刻法を用いて前記シリコン酸化膜7及び第
一の絶縁膜3の一部を除去しコンタクトホール8を形成
する。この場合ゲート電極1またはゲート電極2の側面
にはシリコン酸化膜7によるサイドウォール10が形成
される。次に第二の導電膜たとえば金属電極9を形成す
る。
The following is a detailed description with reference to the drawings. 1A, a first insulating film 3 is formed on a surface of a semiconductor substrate 5 of a first conductivity type, a first conductive film, for example, a polycrystalline silicon film is formed, and then a second conductive film is formed. An insulating film such as a silicon oxide film is formed. Then, unnecessary portions of the silicon oxide film and the polycrystalline silicon film are removed by photolithography to form a gate electrode composed of the silicon oxide film 6 and the polycrystalline silicon 1 and 2. At this time, the second insulating film may be etched using the photoresist as a mask, and then the photoresist may be removed, and then the first conductive film may be etched using the second insulating film as a mask. Next, the second conductivity type impurity is ion-implanted using the gate electrode as a mask and then annealed to thereby form the second conductivity type impurity layer 4.
To form Next, as shown in FIG. 1B, after a third insulating film, for example, a silicon oxide film 7 is formed, photolithography is performed so that the silicon oxide film 7 remains at least on the surface of the silicon oxide film 6. The contact hole 8 is formed by removing part of the silicon oxide film 7 and the first insulating film 3 by using the method. In this case, sidewalls 10 of silicon oxide film 7 are formed on the side surfaces of gate electrode 1 or gate electrode 2. Next, a second conductive film, for example, a metal electrode 9 is formed.

【0008】[0008]

【発明の効果】以上述べたように、本発明によれば、マ
スクの合わせずれにより、ゲート電極1とコンタクトホ
ール8が接近しても、ゲート電極上は、シリコン酸化膜
6及び7により絶縁が保たれ、ゲート電極側面はサイド
ウォールとして残るシリコン酸化膜10により絶縁が保
たれ、ゲート電極1と金属電極9の短絡がなくなる。従
って、ゲート電極1とコンタクトホール8およびコンタ
クトホール8とゲート電極2との間の余裕を減らすこと
ができ、微細化できるという効果を有する。
As described above, according to the present invention, even if the gate electrode 1 and the contact hole 8 approach each other due to misalignment of the mask, the insulation on the gate electrode is achieved by the silicon oxide films 6 and 7. The gate electrode side surface is kept insulated by the silicon oxide film 10 remaining as a sidewall on the side surface of the gate electrode, and a short circuit between the gate electrode 1 and the metal electrode 9 is eliminated. Therefore, the margin between the gate electrode 1 and the contact hole 8 and the margin between the contact hole 8 and the gate electrode 2 can be reduced, which has the effect of miniaturization.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)〜(c)は本発明の半導体装置の製造方
法の一実施例を示す主要断面図。
FIGS. 1A to 1C are main cross-sectional views showing one embodiment of a method for manufacturing a semiconductor device of the present invention.

【図2】(a)〜(d)は従来の半導体装置の製造方法
を示す主要断面図。
FIGS. 2A to 2D are main cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1・・・多結晶シリコンゲート 3・・・絶縁膜 4・・・第2導電型の不純物層 5・・・第1導電型の半導体基板 6,7・・・シリコン酸化膜 8・・・コンタクトホール 9・・・金属電極 10・・・サイドウオール DESCRIPTION OF SYMBOLS 1 ... Polycrystalline silicon gate 3 ... Insulating film 4 ... 2nd conductivity type impurity layer 5 ... 1st conductivity type semiconductor substrate 6, 7 ... Silicon oxide film 8 ... Contact Hall 9: Metal electrode 10: Side wall

─────────────────────────────────────────────────────
────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成9年4月21日[Submission date] April 21, 1997

【手続補正1】[Procedure amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】発明の名称[Correction target item name] Name of invention

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【発明の名称】 半導体装置の製造方法Patent application title: Method of manufacturing semiconductor device

【手続補正2】[Procedure amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】特許請求の範囲[Correction target item name] Claims

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【特許請求の範囲】[Claims]

【手続補正3】[Procedure amendment 3]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0001[Correction target item name] 0001

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【0001】[0001]

【発明の属する技術分野】本発明は絶縁ゲート型トラン
ジスタを有する半導体装置の製造方法に関する。特に、
基板と導電膜とのコンタクト構造を有する半導体装置の
製造方法に関するものである。
The present invention relates to a method for manufacturing a semiconductor device having an insulated gate transistor. Especially,
The present invention relates to a method for manufacturing a semiconductor device having a contact structure between a substrate and a conductive film.

【手続補正4】[Procedure amendment 4]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0002[Correction target item name] 0002

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【0002】〔発明の概要〕本発明は、絶縁ゲート型ト
ランジスタを有する半導体装置の製造方法において、第
一のゲート電極と第二のゲート電極間にコンタクトホー
ルを形成し、このコンタクトホールを通して半導体基板
と導電膜を接続する場合、第一のゲート電極および第二
のゲート電極上に第一の絶縁膜を形成し、その上に第二
の絶縁膜を形成することにより、マスク合わせ工程での
コンタクトホールとゲート電極との間の合わせずれが生
じても、コンタクトホールに接続された導電膜とゲート
電極との間の短絡を防ぐことができるようにしたもので
ある。
SUMMARY OF THE INVENTION According to the present invention, in a method of manufacturing a semiconductor device having an insulated gate transistor, a contact hole is formed between a first gate electrode and a second gate electrode, and a semiconductor substrate is formed through the contact hole. When connecting the conductive film and the conductive film, a first insulating film is formed over the first gate electrode and the second gate electrode, and a second insulating film is formed thereover, so that the contact in the mask alignment step is performed. Even if misalignment occurs between the hole and the gate electrode, a short circuit between the conductive film connected to the contact hole and the gate electrode can be prevented.

【手続補正5】[Procedure amendment 5]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0005[Correction target item name] 0005

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【0005】[0005]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板上に第1絶縁膜を形成する工程、
前記第1絶縁膜上に、互いに離間して設置され、かつそ
れそれが上部に第2絶縁膜を有する第1のゲート電極お
よび第2ゲート電極を形成する工程、前記第1及び前記
第2ゲート電極に挟まれた前記半導体基板中に不純物層
を形成する工程、前記第1および前記第2ゲート電極上
部に第3絶縁膜を形成し、前記第1及び前記第2ゲート
電極の側面にサイドウォールを形成する工程、前記第3
絶縁膜および前記サイドウォール上に延在し、前記不純
物層と接続される第3導電膜を形成する工程、を有する
ことを特徴とする。
A method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming a first insulating film on a semiconductor substrate;
Forming a first gate electrode and a second gate electrode on the first insulating film spaced apart from each other and having a second insulating film thereon; the first and second gates; Forming an impurity layer in the semiconductor substrate sandwiched between electrodes; forming a third insulating film on the first and second gate electrodes; and forming sidewalls on side surfaces of the first and second gate electrodes. Forming the third step;
Forming a third conductive film extending over the insulating film and the sidewall and connected to the impurity layer.

【手続補正6】[Procedure amendment 6]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0008[Correction target item name] 0008

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【0008】[0008]

【発明の効果】以上述べたように、本発明によれば、マ
スクの合わせずれにより、ゲート電極とコンタクトホー
ルが接近しても、ゲート電極上は第2の絶縁膜によっ
て、またゲート電極側面はサイドウォールとによって絶
縁が保たれ、ゲート電極と導電膜の短絡がなくなる。従
って、第1ゲート電極とコンタクトホールおよび第2ゲ
ート電極とコンタクトホールとの間の余裕を減らすこと
ができ、微細化できるという効果を有する。
As described above, according to the present invention, even if the gate electrode and the contact hole approach each other due to misalignment of the mask, the second insulating film on the gate electrode and the side surface of the gate electrode can be used. Insulation is maintained by the sidewall, and a short circuit between the gate electrode and the conductive film is eliminated. Therefore, the margin between the first gate electrode and the contact hole and the margin between the second gate electrode and the contact hole can be reduced, and the effect of miniaturization can be obtained.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に設けられた第1絶縁膜、前
記第1絶縁膜上に互いに離間して設けられた第1導電膜
及び第2導電膜、前記第1導電膜と前記第2導電膜とに
挟まれた前記半導体基板中に設けられた不純物拡散層、
前記第1導電膜及び前記第2導電膜と同じ幅を有する第
2絶縁膜、前記第1絶縁膜上、および少なくとも前記第
2絶縁膜直上において全面にわたって設けられた第3絶
縁膜、前記第3絶縁膜上に延在し設けられた第3導電
膜、前記第3導電膜と前記不純物拡散層を電気的に接続
させるための前記不純物拡散層上の前記第3絶縁膜に設
けられたコンタクトを有すること特徴とする半導体装
置。
A first insulating film provided on a semiconductor substrate; a first conductive film and a second conductive film provided on the first insulating film so as to be separated from each other; An impurity diffusion layer provided in the semiconductor substrate sandwiched between a conductive film,
A second insulating film having the same width as the first conductive film and the second conductive film, a third insulating film provided over the entire surface on the first insulating film, and at least directly on the second insulating film; A third conductive film extending over the insulating film; and a contact provided on the third insulating film on the impurity diffusion layer for electrically connecting the third conductive film to the impurity diffusion layer. A semiconductor device, comprising:
JP9086559A 1997-04-04 1997-04-04 Method for manufacturing semiconductor device Expired - Lifetime JP2828089B2 (en)

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Related Parent Applications (1)

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JP60181354A Division JPH0831599B2 (en) 1985-08-19 1985-08-19 Semiconductor device

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JPH1032252A true JPH1032252A (en) 1998-02-03
JP2828089B2 JP2828089B2 (en) 1998-11-25

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019093534A (en) * 2017-11-28 2019-06-20 株式会社ソディック Wire electric discharge machining device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58115859A (en) * 1981-12-28 1983-07-09 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58115859A (en) * 1981-12-28 1983-07-09 Fujitsu Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019093534A (en) * 2017-11-28 2019-06-20 株式会社ソディック Wire electric discharge machining device

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