JPH1032269A - Semiconductor device - Google Patents

Abstract

(57) [Problem] In a conventional EEPROM, when a memory cell is miniaturized for further higher integration, a high voltage applied to a drain at the time of writing leaks to an adjacent cell.
There is a problem that the channel length varies, the read current amount varies, and the coupling capacitance between the floating gate and the source decreases the controllability of the control gate voltage to the floating gate. SOLUTION: A silicon pillar 2 having a conical, cylindrical, or polygonal pyramid shape is formed on a substrate 1, and a floating gate 3 and a control gate 4 are formed so as to surround the silicon pillar 2.
To form a cell transistor, and by arranging a plurality of the cell transistors in a direction perpendicular to the substrate,
Increase the degree of integration per unit area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically erasable nonvolatile semiconductor memory device (hereinafter referred to as "EEPROM").
More particularly, the present invention relates to a three-dimensionally formed nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art Currently used EEPROMs include:
There are two types: NAND type and NOR type. NAND type, N
In each of the OR type memory cells, one cell includes a floating gate, a control gate, a source portion, and a drain portion. The floating gate is formed in a self-aligned manner with respect to the control gate. By injecting electrons or holes into the floating gate, the threshold voltage (hereinafter, referred to as Vth) of the memory cell transistor is controlled, and a voltage is applied to the drain and control gate of the memory cell transistor at the time of reading, By detecting the amount of current flowing from the drain, 1/0 of the data is determined. In other words, a memory cell in which electrons are injected into the floating gate and the threshold voltage Vth is rising is determined as a “0” cell, and a memory cell in which electrons are not injected into the floating gate is determined as a “1” cell.

FIG. 12 shows a general NOR type EEPROM cell. FIG. 13 shows an equivalent circuit of FIG. FIG.
2 and a portion surrounded by a broken line MC shown in FIG. 13 is a memory pattern required to hold 1-bit data.

In a NOR type EEPROM, a cell transistor Tr is connected to a bit line 6 in parallel. That is, the drain of the cell transistor Tr is connected to the bit line 6
And the gate is connected with the gate of the adjacent cell transistor Tr to form the word line 9. The sources of the cell transistors Tr are commonly connected to a source line 7. In data reading, a potential for reading is applied to the selected word line 9 and bit line 6, and a current flows from the bit line 6 to the source line 7 in a cell at the intersection of the selected word line 9 and bit line 6. Is detected, and 1/0 of the data is determined.

In the above NOR type cell, a contact for connecting the drain to the bit line 6 and a connection to the source line 7 are required, and the contact occupies a large part of the cell area. In order to reduce the area, the connection to the drain contact and the source line 7 is shared by the two cell transistors, but the area of the memory cell is still large,
It was not suitable for high integration.

[0006] On the other hand, a NAND type EEPROM can increase the degree of integration. FIG.
Shows a NAND type pattern, and FIG. 15 shows an equivalent circuit of FIG. A portion surrounded by a broken line MC shown in FIGS. 14 and 15 is a pattern of a memory cell required to hold 1-bit data.

In a NAND type memory, a group in which a plurality of memory cell transistors Tr are connected in series, and a select gate SG for selecting a cell group at both ends of the cell group.
1, SG2. The drain of one select gate SG1 is connected to bit line 6. The gate of this select gate SG1 is connected to the gate of the select gate of another adjacent cell group to form a select line 8a. The source of the other select gate SG2 is connected to the source line 7 together with the sources of the select gates of the other cell groups, and similarly forms the select line 8b.

In reading data from the NAND type memory, a read potential is applied to a bit line 6 connected to a cell group including a cell from which data is to be read, and a voltage is applied to a select gate to make a select transistor conductive. A voltage (for example, VDD) is applied to the gate of the unselected cell via the word line 9 to make the cell transistor conductive,
A read voltage (eg, 0 V) is applied to the gate of the cell to be selected.
V). The voltage applied to the gates of the selected cell and the non-selected cell differs depending on whether the memory cell is a depletion type or an enhancement type. Data is read by detecting whether or not a current flows through the bit line 6 when a read voltage is applied. The NAND type cell has a disadvantage that an extra area is required for the select gate connected to the cell group. However, as the number of source / drain contacts is small and the number of cells is increased, the area of the select gate per cell is reduced. Therefore, when viewed comprehensively, the integration degree of the NAND type is higher than that of the NOR type. Become.

[0009]

However, even in the case of a NAND type cell with a high degree of integration, if the miniaturization is advanced to improve the degree of integration, the following problems will occur as long as the cell transistors are arranged on a plane. Occurs.

First, a high voltage is applied to the drain portion of a memory cell when writing data. At present, the high voltage applied to the drain leaks due to ion implantation or element isolation using a field oxide film. Is prevented. However, when the isolation width between the drains is narrowed to increase the degree of integration of the memory cells, the potential leaks to the drains of the adjacent memory cells, which is an obstacle to miniaturization.

Further, as the channel length of the memory cell is reduced in order to increase the degree of integration, the influence of processing variations of the gate electrode appears. For example, if the channel length is 0.7 μ
m, processing variation of gate electrode is 0.05 μm on one side
If there is, the channel length is in the range of 0.1 μm, that is, 1
It varies more than 0%. For this reason, variations occur in the amount of writing at the time of writing data and the current at the time of reading data.

In order to increase the degree of integration, the distance between the control gate of the memory cell and the drain or source of the cell may be reduced. However, since the drain portion is provided with a contact for connecting to the bit line, the control gate and the bit line may be short-circuited due to misalignment of the mask. Also,
If the control gate overlaps with the source, the capacitance due to the coupling between the floating gate formed in a self-aligned manner and the source serving as the diffusion layer increases, and the voltage applied to the control gate at the time of reading or writing increases. Since the ratio of addition to the floating gate is reduced, the controllability of the control gate to the floating gate is reduced.

As described above, various problems arise when memory cells are miniaturized in a planar manner. The present invention has been made in view of the above problems, and has as its object to create a cell array capable of increasing the degree of integration of memory cells.

[0014]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a first conductive type silicon pillar formed on a semiconductor substrate and a direction in which the silicon pillar extends near a surface of the silicon pillar. A source region and a drain region of a second conductivity type sequentially formed at a predetermined interval; a first insulating film surrounding an outer peripheral side surface located between the source and drain regions of the silicon pillar; A floating gate provided on an outer peripheral side surface of the insulating film; a second insulating film provided on an outer peripheral side surface of the floating gate;
An electrically erasable semiconductor memory cell comprising a control gate provided on an outer peripheral side surface of the second insulating film and an interlayer insulating film formed on a side surface of a source region and a drain region of the silicon column, A semiconductor memory cell group provided with two or more semiconductor memory cells stacked in the direction in which the semiconductor memory cells extend.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a longitudinal sectional view of an embodiment of the present invention. FIG. 2 is a circuit diagram of the embodiment of FIG. FIG. 3 is a horizontal sectional view taken along line 3-3 in FIG.

As shown in FIGS. 1 and 3, a plurality of silicon pillars 2 having a circular cross section, for example, are formed on a substrate 1. A floating gate 3 is formed on these silicon pillars 2 via a thin insulating film 11 so as to surround the periphery thereof.
, A control gate 4 is formed. The floating gate 3 and the control gate 4 are formed in a direction perpendicular to the substrate with an interlayer insulating film 13 interposed therebetween. The silicon pillar 2 is doped with, for example, a p-type impurity. In the region 10 of the silicon pillar 2 surrounded by the floating gate, a channel region of a depletion type transistor is formed by doping with impurities. In addition, for example, an n-type impurity is doped into the side surface region 5 of the silicon pillar 2 which is located above and below each of the channel regions and is surrounded by the interlayer insulating film 13.
Source / drain regions are formed.

In the above configuration, a portion surrounded by a broken line MC shown in FIG. 1 functions as one memory cell. A plurality of nonvolatile memory cells are formed along the silicon pillar 2. Also, as shown in FIGS. 1 and 3, the control gates 4 stacked in the vertical direction are connected to similar control gates of other silicon pillars to form word lines 9. The word line 9 is driven by a decoder (not shown) provided outside the cell array.

Further, as shown in FIGS. 1 and 2, select gates SG1 and SG2 are provided above and below a cell group constituting a storage element in the silicon pillar 2, and are surrounded by select lines 8a and 8b. On the surface of the silicon pillar,
For example, a channel region of an enhancement transistor is formed by doping with impurities. A bit line 6 is provided at the tip of each of the silicon pillars 2, and this bit line 6 is connected to the drain region of the select gate SG1. The source region of the select gate SG2 is connected to the source line 7. By applying a voltage to the select lines 8a and 8b, a cell group formed on the silicon pillar or the source line 7 is electrically connected or disconnected.

Next, an example of writing, reading and erasing data in the present memory cell will be described. The operation of this cell is
This is similar to a conventional NAND type memory cell, and uses FN (Fowler-Nordheim) tunneling phenomenon for both writing and erasing.

First, a case where data in a memory cell is erased will be described. FIG. 4 shows the state of electrons when erasing a memory cell. FIG. 5 shows a voltage application state during data erasing. When erasing data, a low voltage (for example, 0 V) is applied to the control gate 4 of the memory cell, and a high voltage, for example, 18 V, at which a tunnel current flows from the floating gate 3 to the silicon column 2 toward the silicon column 2. Is applied. By doing so, electrons are extracted from the floating gate 3 by FN tunneling, holes are injected into the floating gate 3, and the floating gate 3 is positively charged.
The threshold voltage Vth of the memory cell becomes a negative value.

Next, a case where data is written to a memory cell will be described. FIG. 6 shows a voltage application state when a voltage is written to a memory cell. Memory cell MC in FIG.
When writing data to a selected control gate, a high voltage, for example, 18 V is applied to a selected control gate, and 9 V is applied to a non-selected control gate. Also, select line 8
For example, 11 V is applied to a and 8b. When writing “0” data, the selected bit line 6 is set to a low voltage, for example, 0V.
And 9V is applied to the non-selected bit lines. In this voltage application state, electrons are injected into the floating gate by FN tunneling, and the threshold voltage of the memory cell increases. Also,"
When writing 1 "data, the selected bit line 6 is set to a high voltage, for example, 9 V. Under this condition, electrons are not injected into the floating gate, so that the threshold voltage of the memory cell does not change.

Next, a case where data is read from a memory cell will be described. FIG. 7 shows a voltage application state of the memory cell array at the time of reading. When reading data from the memory cell MC shown in FIG. 7, a low voltage, for example, 0 V is applied to the selected control gate. To the control gate of the non-selected memory cell, a voltage higher than both the threshold voltage when the written data is “1” and the threshold voltage when the written data is “0”, for example, 5 V is applied.
A selection potential, for example, 5 V is applied to the select lines 8a and 8b for selecting a cell block. A voltage for reading, for example, 2 V, is applied to the selected bit line 6. By doing so, in the unselected memory cells, a voltage exceeding the threshold voltage is applied to the control gate regardless of the stored data, so that a current flows from the drain side to the source side. Since a low voltage is applied to the control gate of the selected memory cell, no current flows when the data of the selected memory cell is "0" and the threshold voltage is high, and when the data is "1" and the threshold voltage is low, Electric current flows.
Data is determined by detecting whether or not this current flows.

In the above embodiment, a plurality of silicon pillars 2 are formed on a substrate 1, a plurality of memory cell channel portions are vertically arranged on side surfaces of the silicon pillar 2, and a floating gate and a control gate are Is placed,
The degree of integration can be improved without reducing the channel length, and an increase in the memory cell area can be prevented.

When the silicon pillar has a conical shape, the elements can be separated by selectively processing the bottom of the cone. Further, it is theoretically possible to increase the number of stages of the floating gate up to the limit of the current that can be passed by the resistor.

FIG. 8 shows a second embodiment of the present invention. In this embodiment, in order to reduce the coupling capacitance between adjacent word lines 9, the arrangement directions of the adjacent word lines 9 in the vertical direction of the same silicon pillar 2 are made different by 90 degrees.
When word lines are arranged in a plane, the word lines always run in the same direction. If a configuration in which all word lines are arranged in the same direction in a three-dimensional configuration is employed, the capacitance of the upper and lower word lines is capacitively coupled in the form of a parallel plate. When reading data, a low voltage is applied to the word line of the selected control gate, and a non-selected high voltage is applied to the unselected word lines. For this reason, when the word lines run in the same direction, the access time at the time of reading data decreases due to the capacitance between the upper and lower word lines. However, as in this embodiment, the coupling capacitance can be reduced by making the direction of the word line 9 different in the upper and lower directions, and it is possible to prevent a decrease in access time.

In the present invention, the word lines and select lines are driven by the output of the decoder. Regarding the connection between the decoder and the word line or the select line, the word line or the select line has a high density at the end thereof. Therefore, it is conceivable that the decoder is also formed as a vertical structure and connected to the word line or the select line. Alternatively, a method is conceivable in which the ends of the word lines and the select lines are formed in a vertical structure, a flag is provided as a connecting portion at the end, and the flag is connected to the output terminal of the decoder. FIG. 9A shows a case in which the terminal portion of the word line 9 or the select line 8 has a vertical structure to provide a step-like portion, and the word line 9 or the select line 8 is sequentially exposed at this portion to provide the flag 15. FIG. This flag 15
And, for example, the output terminal of a decoder provided on a plane,
They are connected by bonding wires. FIG. 9 (b)
FIG. 10 shows a top view of the structure shown in FIG. FIG. 9A is a sectional view taken along line 9a-9a in FIG. 9B.

In the cell array according to the present invention, since the bit lines from which data is read are not highly integrated, it is desirable that sensing be performed in the same chip. FIG. 10 shows a third embodiment of the present invention. FIG.
11 is a circuit diagram of the embodiment of FIG. In the first embodiment, the bit line is provided at the tip of the silicon pillar 2, but in this embodiment, the bit line 6 and the source line 7 are connected to the side wall of the silicon pillar. In the present embodiment, the structure of the memory cell group arranged along the silicon pillar shown in FIG. 1 and the bit line and the source line connected via select gates arranged above and below the memory cell group is repeated. It has a stacked structure.

With such a configuration, a plurality of bit lines 6 and source lines 7 can be connected to one silicon pillar, and the adjustment of the read current amount, which is the limit of the configuration of FIG. Since the division can be performed, the storage capacity per unit area increases.

[0029]

As described above, in the present invention, the degree of integration per unit area can be increased by arranging the constituent elements of each part of the memory cell which has been conventionally arranged two-dimensionally. be able to.

Since the memory cells can be integrated three-dimensionally, the degree of integration can be maintained even if the spacing between the silicon pillars is increased to some extent and the element isolation width between adjacent memory cells is increased. In this case, the high voltage applied to the drain of the memory cell can be prevented from leaking to the drain of the adjacent memory cell.

Further, in the present invention, since the interlayer insulating film and the control gate or the floating gate are alternately formed in the vertical direction, the source or the drain does not overlap with the control gate or the floating gate. The controllability of the control gate with respect to the floating gate does not decrease. Further, since an interlayer insulating film is always formed between the bit line and the control gate, there is no short circuit between the bit line and the control gate.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of the embodiment of FIG.

FIG. 3 is a horizontal sectional view of the embodiment of FIG. 1;

FIG. 4 is a diagram showing a behavior when data is erased from a cell.

FIG. 5 is a diagram showing a state of voltage application when data is erased from a cell in the cell array of the present invention.

FIG. 6 is a diagram showing a voltage application state at the time of writing data to a cell in the cell array of the present invention.

FIG. 7 is a diagram showing a voltage application state at the time of reading data from a cell in the cell array of the present invention.

FIG. 8 is a diagram showing a second embodiment of the present invention.

9A is a cross-sectional view when a word line and a select line are arranged with flags, and FIG. 9B is a top view of the flag arrangement shown in FIG. 9A.

FIG. 10 is a diagram showing a third embodiment of the present invention.

FIG. 11 is a circuit diagram of the embodiment of FIG. 10;

FIG. 12 is a circuit pattern diagram showing a cell array of a NOR type EEPROM.

FIG. 13 is a circuit diagram of the cell array of FIG.

FIG. 14 is a circuit pattern diagram showing a cell array of a NAND type EEPROM.

FIG. 15 is a circuit diagram of the cell array of FIG. 14;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Silicon pillar, 3 ... Floating gate, 4 ... Control gate, 5 ... Source / drain, 6 ... Bit line, 7 ... Source line, 8 ... Select line, 9 ... Word line.

Claims (7)

[Claims] A first conductive type silicon pillar formed on a semiconductor substrate; and a second conductive type silicon pillar sequentially formed in the vicinity of a surface of the silicon pillar at a predetermined interval in a direction in which the silicon pillar extends. A source region and a drain region, a first insulating film surrounding an outer peripheral surface located between the source and drain regions of the silicon pillar, a floating gate provided on an outer peripheral surface of the first insulating film, The second provided on the outer peripheral side surface of the floating gate
Electrically erasable semiconductor memory, comprising: an insulating film, a control gate provided on an outer peripheral side surface of the second insulating film, and an interlayer insulating film formed on side surfaces of a source region and a drain region of the silicon pillar. A semiconductor memory cell group comprising: two or more semiconductor memory cells arranged in a direction in which the silicon pillar extends. A first selector transistor provided on the silicon pillar, having a source region connected to a drain region of an uppermost semiconductor memory cell of the semiconductor memory cell group, and a drain region connected to a bit line; The semiconductor device according to claim 1, further comprising a second selector transistor having a drain region connected to a source region of a lowermost semiconductor memory cell in the semiconductor memory cell group and a source region connected to a source line. Semiconductor device. 3. A silicon pillar of a first conductivity type formed on a semiconductor substrate, at least one bit line provided on a side surface of the silicon pillar, and at least one source provided on a side surface of the silicon pillar. A second conductivity type provided on the silicon pillar located between the source line and the bit line, and formed in the vicinity of the surface of the silicon pillar at predetermined intervals in a direction in which the silicon pillar extends. A first insulating film surrounding an outer peripheral side located between the source and drain regions of the silicon pillar; a floating gate provided on an outer peripheral side of the first insulating film; A second gate provided on an outer peripheral side surface of the floating gate;
Electrically erasable semiconductor memory, comprising: an insulating film, a control gate provided on an outer peripheral side surface of the second insulating film, and an interlayer insulating film formed on side surfaces of a source region and a drain region of the silicon pillar. A plurality of semiconductor memory cell groups in which two or more cells are provided in the direction in which the silicon pillar extends; and a semiconductor memory cell provided in the silicon pillar and having a source region at one end of each of the semiconductor memory cell groups. A first selector transistor having a drain region connected to the bit line, a drain region connected to the bit line, and a drain region connected to a source region of a semiconductor memory cell at the other end of each semiconductor memory cell group. And a second selector transistor connected to the source line. 4. The semiconductor device according to claim 1, wherein said silicon pillar has one of a conical shape, a cylindrical shape, a polygonal pyramid shape, and a polygonal prism shape. 5. A word line formed by providing a plurality of silicon pillars provided with the semiconductor memory cell group and connecting the control gates of different silicon pillars,
4. The semiconductor device according to claim 1, wherein the semiconductor device extends in a direction other than at least one of the upper and lower word lines. 6. The semiconductor device according to claim 5, wherein said word lines extend in a direction perpendicular to at least one of upper and lower word lines. 7. A stepped portion is provided at a terminating end of a word line connected to the control gate and a select line connected to the gate of the selector transistor,
4. The semiconductor device according to claim 1, wherein the word line and the select line are sequentially exposed for each of the steps, and a flag is provided.