JPH1032673A - Imaging device having charge storage type light receiving unit - Google Patents

Abstract

(57) [PROBLEMS] To improve the removal effect of the afterimage removal scan for removing the charge signal left behind during the readout scanning in the charge storage type light receiving unit of the solid-state imaging device. A scan clock used for driving a shift register has an asymmetric duty ratio in order to secure an S / N ratio of an image signal. The inversion pulse output unit 230 includes an inverter 232 and a switch 234 for inverting the scanning clock, and outputs a scanning clock at the time of reading scanning and an inverted scanning clock at the time of afterimage removal scanning. These clocks are used as reset control pulses and the reset switch 2
26 is opened and closed. Thereby, at the time of readout scanning,
The S / N ratio of the image signal is secured by extending the charge signal accumulation time of the charge detection capacitor 216, and the closing time of the reset switch 226 during the afterimage removal scanning, that is, the reset time of the light receiving unit 202, during the readout scanning. It will be longer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for a facsimile, an image scanner, or the like, and includes a plurality of light receiving sections for storing charge signals corresponding to the amount of received light, and sequentially reads out the charge signals from these light receiving sections by switching. The present invention relates to an imaging device that outputs an image signal, and more particularly to a driving circuit that reduces an afterimage in an image signal caused by incomplete reading of a charge signal from a light receiving unit.

[0002]

2. Description of the Related Art FIG. 11 is a circuit diagram of a conventional solid-state imaging device in which a plurality of phototransistors are arranged one-dimensionally as light receiving units. Each light receiving unit 2 includes a phototransistor 4 and a capacitor 6 provided between its collector and base. The collector of the phototransistor 4 is supplied with a voltage from a power supply terminal 8 (VDD). The capacitor 6 is charged with electric charge in the reset state, and is discharged according to the amount of incident light. This discharge amount is taken out from the light receiving section 2 as a charge signal.

In this one-dimensional image sensor, each light receiving unit 2 is provided with a pixel selection switch 10. When the switch 10 is opened and closed (on / off), the light receiving unit 2 is opened.
A current corresponding to the charge signal accumulated in the output signal line is taken out to the output signal line 12. The current is stored in the charge detection capacitor 16 connected between the output terminal 14 and the ground, whereby a voltage corresponding to the charge signal is generated at the output terminal 14. By sequentially turning on / off the switch 10, an image signal for one line is obtained. A one-dimensional image sensor provided with such a scanning unit is often used as an image scanner for reading an image into a computer or a facsimile as a contact type image sensor for reading an original without using a reduction optical system. Incidentally, in recent years, an image scanner capable of capturing a color image using this sensor has been developed.

[0004] In addition to the above components, components for turning on / off the pixel selection switch 10 and resetting signal charges are formed on the solid-state imaging device. ON / OFF of the pixel selection switch 10 is performed by the shift register 18. The shift register 18 has a structure in which D flip-flops 20 are connected in a line. Shift register 1
Reference numeral 8 designates a start pulse (SI) as a start pulse terminal 22.
, The pixel selection switches 10 are turned on / off sequentially in synchronization with the scanning clock (CLK) supplied from the clock terminal 24. Here, the pixel selection switch 10 is, for example, an analog switch. The analog switch receives the pixel selection pulse from the shift register 18 at the gate and controls the connection between the light receiving unit 2 and the output signal line 12. The reset switch 26 is provided between a reset terminal 28 connected to the ground and the output signal line 12,
It is turned on / off by the scanning clock, and resets the capacitor 6 and the charge detection capacitor 16 of the light receiving unit 2.

FIG. 12 is a timing chart showing a driving method of the conventional solid-state imaging device. The low duty ratio of the scan clock 30, which is also used as a reset control pulse for opening and closing the reset switch 26, that is, the ratio of the low level in one cycle of the scan clock is, for example, 75%. When one start pulse having a width corresponding to one scan clock cycle is input from the start pulse terminal 22 to the shift register 18, the first stage D flip-flop 20 outputs a pixel selection pulse having one scan clock cycle width. Thereafter, when each D flip-flop 20 receives a pixel selection pulse from the preceding D flip-flop, it delays it by one cycle of the scan clock 30 and outputs it to the next stage. That is, the pixel selection pulse 32 output from the i-th stage D flip-flop and the (i + 1) -th stage D flip-flop
Each of the pixel selection pulses 34 output from the flip-flop has a width of one cycle of the scanning clock.
Is delayed by one scan clock cycle from the pulse 32.

The pixel selection pulse output from the D flip-flop at the i-th stage (i is arbitrary) is supplied to the gate of an analog switch constituting the i-th pixel selection switch 10. The analog switch is turned on while receiving the pixel selection pulse, and the emitter of the phototransistor 4 is connected to the output signal line 12. Then, the light receiving unit 2
Based on the charge signal stored in the capacitor 6 of FIG.
An emitter current is generated, and the phototransistor 4 amplifies this current and outputs a collector-emitter current to the output signal line 12.
Output to

The analog switch constituting the reset switch 26 is in the off state while the scan clock 30 is at a low level, so that the current output to the output signal line 12 is charged in the charge detection capacitor 16 and the output signal is output. Is converted to a voltage signal 36. As shown in FIG. 12, the voltage signal 36 rises when the pixel selection switch 10 is turned on (waveform 38). If the ON state continues, the voltage value gradually approaches a voltage level 40 corresponding to the charge signal amount of the capacitor 6. This is because the charge signal of the capacitor 6 is gradually reset by the base-emitter current, and the base-emitter voltage is reduced due to the rise of the emitter-side potential. Is asymptotic to zero.

In order to read out the (i + 1) -th light-receiving section 2 following the i-th light-receiving section 2, it is necessary to discharge and reset the charge detection capacitor 16 charged by reading out the i-th light-receiving section 2. is there. This reset is performed by turning on the transistor switch constituting the reset switch 26 when the scanning clock 30 becomes high level. When the reset switch 26 is turned on, the output signal line 12 is grounded, whereby the charge detection capacitor 16 is reset (waveform 4).
2). At the same time, the pixel selection switch 10 also resets the charge signal remaining in the capacitor 6 of the i-th light receiving unit 2 connected to the output signal line 12.
The resetting of the light receiving section 2 is performed by grounding the output signal line 12, increasing the base-collector voltage of the phototransistor 4, and charging up the capacitor 6.

In a device using this solid-state imaging device, for example, a scanner, a high frequency, for example, several MH, is used as a scanning clock to secure a document reading speed.
A clock of z is used. Therefore, before the charge signal of the capacitor 6 is sufficiently read, the reset of the charge detection capacitor 16 and the light receiving unit 2 is started. For the same reason, before this reset operation is completely performed,
The read operation of the (i + 1) -th light receiving unit 2 is started. Usually, the charge signal is extracted as large as possible and S /
In order to secure the N ratio, the low level period of the scan clock is made longer than the high level period (for example, the low duty ratio is set to 75% as described above). 6 is likely to be insufficiently reset. The charge signal remaining in the light receiving unit 2 is read out by being mixed with the charge signal accumulated in the light receiving unit 2 by the imaging of the next one line, and an afterimage phenomenon occurs.

FIG. 13 is a timing chart for explaining the concept of the afterimage phenomenon. The light emitting diode (LED) emits light for the light emitting period TL by the pulse 50, and irradiates a plain original. The light receiving section 2 receives the reflected light from the document.
Subsequently, when the read operation from the light receiving unit 2 is performed a plurality of times by the start pulse 52 input to the start pulse terminal 22, the image signals 54, 56,
8 is output. Of these, the image signals 54 and 56 obtained by the second and subsequent read operations are based on the charge signals left in the light receiving unit 2 in the first read operation, and this is an afterimage. Assuming that the level of the image signal 54 is V0, the level Vn of the image signal by the n-th read operation is approximately expressed by the following equation using a constant κ. For example, κ = about 0.5.

Vn = V0 · κ ^{n -1} This afterimage appears as a phenomenon in a monochrome image in which the image trails in the original reading direction. Color image is 1
The line is obtained by scanning (scanning) the line in order using light of a plurality of colors, for example, light of three primary colors of red (R), green (G), and blue (B). In this color image, the afterimage appears as a phenomenon of color mixture in which an image signal corresponding to a certain color is superimposed with a charge signal in a preceding scan by another color and output. This color mixture degrades the color saturation of the color image. FIG. 14 is a conceptual diagram illustrating this color mixing phenomenon. The scanning of each of RGB is performed sequentially.
The scanning of each color is performed during a light emitting period T of a light emitting diode (LED).
L and a subsequent reading period TR of the light receiving unit 2. Each of the RGB LEDs has a pulse 70, 72, 7 respectively.
4 emits light during those pulse widths TL. The readout period TR of each color is started by a start pulse 76 input to the start pulse terminal 22. For example, in the image signal 78 that should include only the signal of the blue LED light, the color mixture includes the green component 8 in addition to the blue component 80.
2. The red component 84 is included. The green component 82 and the red component 84 are afterimage components generated in the preceding scan.

As described above, the afterimage causes deterioration in image quality in both monochrome images and color images. Conventionally, in order to reduce the image quality deterioration due to the afterimage, a scan for reading out and discarding the charge signal remaining in the light receiving portion 2 repeatedly after reading out the charge signal of the light receiving portion 2 to obtain an image signal has been conventionally performed. This is called an afterimage removal scan).

FIG. 15 is a timing chart for explaining the conventional driving method of the afterimage removal scanning. The figure shows driving for a color image. The scanning of each color is performed during a light emitting period TL of the LED and a reading scanning period T of the light receiving unit 2 following the light emitting period TL.
R and an afterimage removal scanning period TC. Each L of RGB
The EDs emit light during their pulse width TL with pulses 90, 92, 94, respectively. The start pulse 96 is generated twice after each LED emits light. First pulse 9
Reference numeral 8 denotes a state immediately after the light emission of the LED, whereby the charge signals corresponding to RGB stored in the light receiving unit 2 become image signals 100,
It is read out as 102 and 104. Second pulse 1
06 is generated after the reading of the image signals 100, 102, and 104 is completed. Therefore, the interval between the two start pulses 98 and 106 is TR. In this conventional driving method for reducing the afterimage, the operation of the solid-state imaging device started by the second pulse 106 is the same as the read operation by the first pulse 98. The difference is that each of the RGB signals 11 read by the second pulse 106 is different.
Numerals 0, 112 and 114 are not used for forming an image and are discarded. As a result, for example, the afterimage components 116 and 118 of R and B mixed in the G image signal 102 are reduced to κ times (κ <1) in the case shown in FIG. Readout period T
R and pixel selection switch 1 in afterimage removal scanning period TC
0, the operation of the reset switch 26 is performed in exactly the same manner. That is, for example, using the scan clock 30 and the pixel selection pulses 32 and 34 shown in FIG. 12, the readout scan in the period TR and the afterimage removal scan in the period TC are performed. Therefore T
The length of C is equal to the length of TR.

[0014]

As described above, the conventional driving method of the solid-state imaging device in the afterimage removing scan for removing the afterimage is the same as the driving method in the readout scan for obtaining the image signal. The driving method of the removal scanning itself does not have any special consideration for removing the residual image. Therefore, there is a problem that the effect of removing the afterimage is not always sufficient.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image pickup apparatus for performing afterimage removal scanning which can obtain a higher afterimage removal effect.

[0016]

In the imaging apparatus according to the first aspect, the reset control circuit closes the reset switch longer in the afterimage removal scan than in the readout scan. According to the present invention, the period during which the light receiving section is connected to the predetermined potential via the reset terminal is longer in the afterimage removal scan than in the readout scan. As a result, in the readout scan, a longer charge period from the light receiving section to the charge detection capacitor can be taken, and a voltage signal corresponding to the pixel signal can be taken out at a good S / N ratio. The removal of the pixel signal left in the light receiving section is performed favorably.

According to a second aspect of the present invention, in the imaging apparatus according to the first aspect, the reset switch is opened / closed in accordance with a pulse width of a reset control pulse output from the reset control circuit, and the reset control circuit performs a read scan. An inversion pulse output unit that outputs the reset control pulse whose duty ratio is inverted between the time and the afterimage removal scanning.

According to the present invention, since the duty ratio of the reset control pulse is inverted between the read scan and the afterimage removal scan, the closed period of the reset switch is longer in the afterimage removal scan than in the read scan. Is done. Whether the reset switch is closed by the high level or the low level of the reset control pulse can be arbitrarily configured. For example, in the case where the reset switch is configured to be closed at the high level of the reset control pulse, the duty ratio of the reset control pulse (the ratio of the high level period to one cycle) at the time of readout scanning is α. (Α <0.5).

According to a third aspect of the present invention, in the imaging apparatus according to the second aspect, the scan clock has an asymmetrical duty ratio, and the inversion pulse output unit includes an inverter for inverting the scan clock; A switch for switching between a scan clock and an output of the inverter in response to the time and the afterimage removal scanning, and outputting the output as the reset control pulse. According to the present invention, a reset control pulse can be obtained with a simple circuit configuration by diverting a scan clock used for driving a pixel scanning circuit.

According to a fourth aspect of the present invention, in the imaging apparatus according to the first aspect, the reset switch is opened and closed in accordance with a pulse width of a reset control pulse output from the reset control circuit, and the reset control circuit performs read scanning. A pulse width switching unit for switching the duty ratio of the reset control pulse between the time and the afterimage removal scanning. According to the present invention, since the closed period of the reset switch is set independently during the readout scan and the afterimage removal scan, each of the image signal readout operation and the afterimage removal operation is performed under optimal conditions.

According to a fifth aspect of the present invention, in the imaging apparatus according to the fourth aspect, the reset switch is kept closed during the afterimage removal scanning. According to the present invention, the reset switch is kept closed during the afterimage removal scanning in which the accumulation of the charge signal in the charge detection capacitor is unnecessary, so that the removal rate of the charge signal left in the light receiving section is improved. .

According to a sixth aspect of the present invention, in the image pickup apparatus, the pixel scanning circuit continues the closed state of each pixel selection switch for a predetermined number of scanning clocks during the afterimage removal scanning. Further, the imaging device according to the seventh invention is the first imaging device.
In any one of the fifth to fifth inventions, the pixel scanning circuit comprises:
The closed state of each pixel selection switch is continued for a predetermined number of scanning clocks.

According to the present invention, at the time of the afterimage removal scanning, for example, the i-th pixel selection switch is closed for k cycles of the scanning clock, and the (i + 1) -th pixel selection switch is switched from the i-th pixel selection switch by the scanning clock. It is closed one cycle later. That is, adjacent pixel selection switches are closed simultaneously over the scan clock (k-1) cycle. Since the charge signal taken out of the light receiving portion by the afterimage removal scanning is not used as an image signal and is discarded from the reset terminal, the plurality of pixel selection switches are simultaneously closed as described above, and the charge from the light receiving portion is output on the output signal line. There is no problem if the signals are mixed. With this configuration, the closing time of the reset switch per light receiving unit can be increased by k times, and the removal rate of the charge signal remaining in the light receiving unit is improved.

[0024]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

[First Embodiment] FIG. 1 is a circuit diagram of a solid-state imaging device to which the present invention is applied. In FIG.
Components having functions similar to those of the conventional apparatus shown in FIG. 11 are denoted by reference numerals obtained by adding 200 to the reference numerals in FIG. 11, and description thereof will be omitted. In this device, a circuit related to a charge signal, such as the light receiving unit 202, and a pixel scanning circuit (shift register 218) have the same configuration as that of the related art. The feature of the configuration of this device lies in the drive circuits of these circuits. The drive circuit of the present apparatus serves as a reset control circuit for controlling on / off of the reset switch 226, and an inversion pulse output unit 230 for inverting the scan clock
Having.

The inversion pulse output section 230 includes an inverter 232 and a switch 234. The inverter 232 receives the scan clock and outputs an inverted scan clock. Switch 234
Receives a scan clock and an inverted scan clock, and outputs one of them according to the voltage level of the switching signal (SEL). The switching signal is supplied from the selector terminal 236. The inverted scan clock output from the inverted pulse output unit 230 is supplied to the reset switch 226. Since the shift register 218 operates in synchronization with the falling timing of the scan clock, the scan clock 2
Inverted scan clock 2 having the same period as this instead of 56
The same operation is performed even if 58 is used. Therefore, in this device, the output of the inverted pulse output unit 230 is also used for driving the shift register 218.

FIG. 2 is a timing chart for explaining a driving method of the present apparatus. As shown in FIG. 9A, in the driving method of the present apparatus, two start pulses 250 and 252 are input to the shift register 218 per one line of the image signal, and the readout scan and the afterimage removal scan are performed. The operation is the same as the conventional driving method described with reference to FIG. The scanning of each line includes an LED light emission period TL, a readout scanning period TR, and an afterimage removal scanning period TC. The first start pulse 250 is LE
Immediately after the light emission of D, the signal is input to the pixel scanning circuit, and the shift register 218 starts reading scanning (period TR) of the light receiving unit 202. The second start pulse 252 is provided after the end of reading of the image signal, that is, at an interval of TR from the first start pulse 250,
8, and the shift register 218 removes the charge signal left in the light receiving unit 202 and performs the afterimage removal scan (period T
Start C).

Next, the difference between the driving method of the present apparatus and the conventional driving method will be described. The pulse 254, which is a switching signal input to the selector terminal 236, goes low during the readout scanning period TR and goes high during the afterimage removal scanning period TC. The switch 234 detects the pulse 2
In the period TR corresponding to the scan clock 256,
In the period TC, the inversion scanning clock 258 is output.
The low duty ratio ρ of the scan clock 256 is, for example, 7
5%. At this time, the low
The duty ratio ρ is 25%. The driving method of this device is as follows.
The on / off of the reset switch 226 is controlled using clocks 256 and 258 having different duty ratios in the periods TR and TC. Since the scan clock 256 and the inverted scan clock 258 have the same cycle, the lengths of the periods TR and TC are equal.

FIGS. 2B and 2C show the periods TR and TR, respectively.
It is a timing chart which expanded a part of TC. When a first start pulse 250 having a width corresponding to one scan clock cycle (τ) is input from the start pulse terminal 222 to the shift register 218, each D flip-flop 220
Delays the pixel selection pulse of width τ by τ and
Transfer to the flip-flop 220. That is, the i-th stage D
When the pixel selection pulse 260 is output from the flip-flop, the pixel selection pulse 262 is output from the (i + 1) th stage D flip-flop with a delay of τ. The same applies to the case where the second start pulse 252 (width τ) is input to the shift register 218. The pixel selection pulses 264 and 266 output from the i-th and (i + 1) -th D flip-flops are mutually different. The timing is shifted by τ.

As described above, the D flip-flop 220
Operates in synchronization with the falling edge of the clock, so that the pixel selection pulse 260 in the period TR and the period TC
And the pixel selection pulse 264 at clock 25
The high level is maintained during the period from the beginning of the low level period 6, 258 to the end of the high level period. However, the lengths of the periods TR and TC are different between high and low. That is, in the period TR, the charge time tch of the charge detection capacitor 216 by the charge signal accumulated in each light receiving unit 202 is 0.75τ, and the reset time trst for resetting the charge detection capacitor 216 and the light receiving unit 202 is:
0.25τ. On the other hand, in the period TC, the charging time t′ch is 0.25τ, and the reset time t′rst is 0.75τ.

As described above, by making the charging time tch longer than the reset time trst in the read scanning period TR, the image signal 268 generated at the output terminal 214 increases, and the S / N ratio of the image signal is secured. This is as described in the prior art. The feature of this device is that the reset time t'rst in the afterimage removal scanning period TC is longer than the reset time trst in the read scanning period TR. In the afterimage removal scanning period TC, the reset time t'rst
Is longer than the charging time t′ch,
2 is sufficiently removed to reduce the afterimage. Since the signal 270 generated at the output terminal at this time is not used as an image signal, its voltage value may be small.

The low duty ratio ρ of the scanning clock is
It can be selected in the range of 0.5 <ρ <1.0. Also,
Since inversion and non-inversion are relative, the inversion scanning clock is used not as the period TC but as a reset control pulse in the read scanning period TR, and the scanning clock is used as the period T
Instead of R, it may be used as a reset control pulse in the afterimage removal scanning period TC. However, at this time, ρ of the scanning clock must be selected in the range of 0 <ρ <0.5. When the reset switch 226 is configured by a transistor switch that is turned on at the low level of the reset control pulse and turned off at the high level, the scan clock ρ is selected in the range of 0 <ρ <0.5. . In addition, according to the present invention, the ratio trst / τ of the reset time in one cycle of the scanning clock is inverted between the readout scanning period TR and the afterimage removal scanning period TC by using the scanning clock and the inverted scanning clock, and the ratio trst / τ. Is made larger in the afterimage removal scanning period TC than in the readout scanning period TR. Further, in the present apparatus, the reset control pulse is generated by using the scan clock in order to simplify the circuit configuration. However, the reset control pulse is generated by using another clock having the same cycle as the scan clock but different in ρ. Configurations are also possible.

[Second Embodiment] FIG. 3 is a circuit diagram of a second solid-state imaging device to which the present invention is applied. 3, components having the same functions as those of the device according to the first embodiment shown in FIG. 1 are denoted by reference numerals obtained by adding 100 to the reference numerals in FIG. 1, and description thereof will be omitted. The structural features of this device are as follows:
As in the first embodiment, the present embodiment is provided in a drive circuit. The drive circuit of this device has a pulse width switching unit 330 that switches the duty ratio of the reset control pulse as a reset control circuit that controls on / off of the reset switch 326.

The pulse width switching section 330 includes a switch 334. In this apparatus, a scan clock is input from the outside to a scan clock terminal 324, and a reset clock terminal 33
8, a reset clock (RCLK) having the same cycle as the scan clock but having a different duty ratio is input. The switch 334 receives the scan clock and the reset clock, and outputs one of them according to the voltage level of the switch signal. The switching signal is supplied from a selector terminal 336. The reset control pulse output from the pulse width switching unit 330 is supplied to the reset switch 326. Note that the scan clock is a clock used for driving the shift register 318. In this apparatus, the scan clock is also used to control the reset switch 326 in order to reduce the types of external input clocks and simplify the circuit configuration. However, apart from the scan clock, two reset clocks having different duty ratios are used. It is also possible to adopt a configuration in which these two reset clocks are input to the pulse width switching unit 330 by preparing the types.

FIG. 4 is a timing chart for explaining a driving method of the present apparatus. 4, clocks or pulses having functions similar to those of the device of the first embodiment shown in FIG. 2 are denoted by reference numerals obtained by adding 100 to the reference numerals in FIG. 2, and description thereof will be omitted. The difference between the driving method of the present apparatus and the driving method in the first embodiment is that a reset clock 358 is used instead of the inverted scanning clock 258.

FIGS. 4B and 4C are the same as FIG.
5 is a timing chart in which a part of periods TR and TC shown in FIG. Pulse 3 input to selector terminal 336
Reference numeral 54 denotes the same as the pulse 254, and the switch 334 outputs the scan clock 356 in the period TR and the reset clock 358 in the period TC in response to the pulse 354. The low duty ratio ρ of the scanning clock 356 is, for example, 75%, and the value of ρ is set so that the S / N ratio of the image signal is mainly ensured. On the other hand, ρ of the reset clock can be set independently of ρ of the scan clock. While the reset clock 358 is at a high level, the reset switch 326 is turned on, and the charge signal is removed from the light receiving section 302 to reduce the afterimage. Therefore, basically, the ρ of the reset clock is reduced so that the effect of reducing the afterimage is increased. Ρ of the reset clock is, for example, ρ = 10%.

The basic feature of the present apparatus is that the reset time t'rst in the afterimage removal scanning period TC is made longer than the reset time trst in the readout scanning period TR, thereby improving the effect of reducing the afterimage. . The present apparatus has a scan clock 35
6 is used. That is, when setting the reset time t'rst in the period TC,
Since there is no restriction on the readout scan, t'rst can be adjusted so that a high residual image removal effect in the residual image removal scan is realized.

[Third Embodiment] FIG. 5 is a circuit diagram of a third solid-state imaging device to which the present invention is applied. 5, components having the same functions as those of the device according to the second embodiment shown in FIG. 3 are denoted by reference numerals obtained by adding 100 to the reference numerals in FIG. 3, and description thereof will be omitted. The feature of the configuration of the present apparatus lies in the drive circuit as in the above-described embodiment. As in the second embodiment, the drive circuit of this apparatus includes a pulse width switching unit 430 including a switch 434 as a reset control circuit.

The switch 434 operates using a scan clock input from the scan clock terminal 424 and a switching signal input from the selector terminal 436. Switch 434
Receives a scan clock and a switching signal, and outputs one of these two inputs in accordance with the voltage level of the switching signal.

FIG. 6 is a timing chart for explaining a driving method of the present apparatus. 6, clocks or pulses having the same functions as those of the device according to the second embodiment shown in FIG. 4 are denoted by reference numerals obtained by adding 100 to the reference numerals in FIG. 4, and description thereof will be omitted. The difference between the driving method of the present apparatus and the driving method in the second embodiment is that a switching signal 454 is used instead of the reset clock 358.

FIGS. 6B and 6C are the same as FIG.
5 is a timing chart in which a part of periods TR and TC shown in FIG. The switching signal 454 input to the selector terminal 436 is similar to the pulse 354, and the switching device 434 outputs the scanning clock 456 in the period TR and the switching signal 454 in the period TC in response to the switching signal 454. That is, the reset control pulse output from the pulse width switching unit 430 during the afterimage removal scanning period TC is a constant signal at a high level. In the low duty ratio ρ of the reset control pulse in the period TR, the balance between charging and resetting of the charge detection capacitor 416 is adjusted, and S in the image signal is adjusted.
While the condition that the / N ratio is secured is imposed, the reset control pulse in the period TC does not. The reset control pulse in the period TC may be used to reset the light receiving unit 402 with high efficiency. To achieve this purpose, the device is driven to keep the reset switch 426 on during the period TC while the pixel selection switch 410 is on.

Since the present apparatus holds the reset switch in the ON state during the afterimage removal scanning period TC, a high afterimage removal effect can be obtained. This device is realized by a simple configuration in which a switch 434 is added to a conventional device and a switch signal 454 is supplied.

As in the second embodiment, in order to reduce the number of external input clocks and simplify the circuit configuration, this apparatus uses a reset switch 426 to control the scan clock used to drive the shift register 418. Is also used to control However, apart from the scanning clock, a reset clock having a different duty ratio from the scanning clock is supplied to the pulse width switching unit 4.
A configuration is also possible in which the reset switch 426 is supplied to the power supply 30 for control.

[Fourth Embodiment] FIG. 7 is a circuit diagram of a fourth solid-state imaging device to which the present invention is applied. 7, components having the same functions as those of the apparatus according to the first embodiment shown in FIG. 1 are denoted by reference numerals obtained by adding 300 to the reference numerals in FIG. 1, and description thereof will be omitted. A structural feature of this device resides in a drive circuit of the shift register 518.

The clock for transferring the pixel selection pulse between the D flip-flops 520 constituting the shift register 518 of the present apparatus is a scan clock input to the scan clock terminal 524 as in the conventional apparatus. This apparatus uses this scan clock as the reset switch 52 as in the conventional apparatus.
6 is also used for on / off control. The configuration of this apparatus is characterized in that two start pulse terminals 522 and 540 to which a start pulse is input and one of two types of start pulses input from the start pulse terminals 522 and 540 are selected and output. And a switching unit 542 that performs the switching.

FIG. 8 is a timing chart for explaining a driving method of the present apparatus. 8, clocks or pulses having the same functions as those of the device of the first embodiment shown in FIG. 2 are denoted by reference numerals obtained by adding 300 to the reference numerals in FIG. 2, and description thereof will be omitted. A feature of the driving method of the present apparatus is that pixel selection pulses having different pulse widths are used in the readout scanning period TR and the afterimage removal scanning period TC.

The switching signal 554 input to the selector terminal 536 is the same as the pulse 254, and the switch 542 responds to the switching signal 554 in the period TR by the start pulse 570 from the start pulse terminal 522 and in the period TC. A multi-width start pulse 572 is output from another start pulse terminal 540.

FIGS. 8B and 8C are the same as FIG.
5 is a timing chart in which a part of periods TR and TC shown in FIG. In the read scanning period TR, a start pulse 570 having a pulse width of about one cycle (τ) of the scanning clock 556 is supplied from the switch 542 to the shift register 518.
Is input to Subsequent readout scanning of the charge signal accumulated in the light receiving unit 502 is the same as that in the above-described conventional apparatus and the apparatus of each of the above-described embodiments, and a description thereof will be omitted.

In the afterimage removal scanning period TC, nτ
A multi-width start pulse 572 having a pulse width corresponding to (n is a natural number of 2 or more, where n = 2) is input from the switch 542 to the shift register 518. The first-stage D flip-flop 520 of the shift register 518 is
The value of the start pulse 570 is stored at the falling timing of the scanning clock 556 to generate a pixel selection pulse of nτ width. Hereinafter, each D flip-flop 52
0 delays the output of the D flip-flop of the previous stage by τ and outputs it to the next stage. That is, the pixel selection pulse 574 output from the i-th D flip-flop and (i
The pixel selection pulse 576 output from the (D) flip-flop of the (+1) th stage has a width of nτ, and the pulse 5
76 is delayed by τ from pulse 574. The pixel selection pulses 574 and 576 overlap each other for a period corresponding to (n-1) τ.

Since the pulse width of the pixel selection pulse 574 is nτ, each light receiving unit 502 resets the period trst by n.
Receive twice. When this is added up, it corresponds to n times the reset time of the conventional device. As a result, the present apparatus can obtain a high effect of removing the afterimage. Incidentally, in this driving method, basically, n pixel selection pulses are simultaneously generated by overlapping, and the n pixel selection switches 510 can be simultaneously turned on. Therefore, the afterimage removal scanning period TC does not become n times the readout scanning period TR, and is a period substantially equal to the period TR. If the number of light receiving units 502 arranged in one line is, for example, about 1000, n can be about 10. As n is increased, the effect of removing the afterimage is improved.

[Fifth Embodiment] FIG. 9 is a circuit diagram of a fifth solid-state imaging device to which the present invention is applied. 9, components having functions similar to those of the apparatus shown in FIGS. 1 and 7 are denoted by reference numerals obtained by adding 400 to the reference numerals in FIG. 1, and adding 100 to the reference numerals in FIG. 7, and a description thereof will be omitted.

The present apparatus is a solid-state apparatus using both the configuration of the apparatus of the fourth embodiment using a multi-width pixel selection pulse during the afterimage removal scanning period TC and the inverted pulse output unit of the apparatus of the first embodiment. An imaging device.

FIG. 10 is a timing chart for explaining a driving method of the present apparatus. 10, FIG. 8, FIG.
2 are denoted by the same reference numerals as those in FIG. 2 with 400 added and the reference numerals in FIG.

FIGS. 10B and 10C are timing charts in which a part of the periods TR and TC shown in FIG. 10A are enlarged. In each of the readout scanning period TR and the afterimage removal scanning period TC, the time during which the reset switch 626 is in the ON state for each light receiving unit 602 is defined as t1 and t2, respectively. Assuming that the low duty ratio ρ of the scanning clock 656 is 75%, t1 = 0.25τ. On the other hand, if the pixel selection pulse 674 in the period TC is nτ,
t2 = 0.75nτ. Therefore, in the present apparatus, the reset time t2 of the light receiving unit 602 in the period TC is 3n times the reset time t1 in the period TR, and a high afterimage removal effect can be obtained.

The configuration using the multi-width pixel selection pulse is also used in the devices of the second and third embodiments, and the effect of removing the afterimage can be improved.

[0056]

According to the first aspect, the period during which the light receiving section is connected to the predetermined potential via the reset terminal is longer in the afterimage removal scan than in the readout scan. As a result, in the readout scan, a longer charge period from the light receiving section to the charge detection capacitor can be taken, and a voltage signal corresponding to the pixel signal can be taken out at a good S / N ratio. The effect is obtained that the pixel signal left in the light receiving section is removed favorably.

According to the second aspect of the present invention, the change of the duty ratio between the scan for reading the reset control pulse and the scan for removing the residual image is realized by inverting one pulse. The effect is obtained.

According to the third aspect, since the reset control pulse and the scan clock used for driving the pixel scanning circuit are shared, the above-described effect of the first aspect can be obtained with a simpler circuit configuration. is there.

According to the fourth aspect, the duty ratio of the reset control pulse in the afterimage removal scan can be set independently of the duty ratio of the reset control pulse in the read scan, so that the S / N ratio of the image signal in the read scan is ensured. The effect of achieving both the elimination of the afterimage removal effect and the afterimage removal scanning can be obtained.

According to the fifth aspect of the present invention, in the afterimage removing scan, the afterimage is removed over the entire period in which the light receiving section is connected to the output signal line, so that the S / N ratio of the image signal is secured. There is an effect that a high afterimage removal effect can be obtained.

According to the sixth and seventh aspects, during the afterimage removal scanning, the closed state of each pixel selection switch is set to k of the scanning clock.
Since it continues over a period (k is a natural number of 2 or more),
The closing time of the reset switch per light receiving section is k times, and the effect of removing the afterimage is improved.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a timing chart illustrating a method for driving the solid-state imaging device according to the first embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of a solid-state imaging device according to a second embodiment of the present invention.

FIG. 4 is a timing chart illustrating a method for driving a solid-state imaging device according to a second embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of a solid-state imaging device according to a third embodiment of the present invention.

FIG. 6 is a timing chart illustrating a method for driving a solid-state imaging device according to a third embodiment of the present invention.

FIG. 7 is a circuit configuration diagram of a solid-state imaging device according to a fourth embodiment of the present invention.

FIG. 8 is a timing chart illustrating a method for driving a solid-state imaging device according to a fourth embodiment of the present invention.

FIG. 9 is a circuit configuration diagram of a solid-state imaging device according to a fifth embodiment of the present invention.

FIG. 10 is a timing chart illustrating a method for driving a solid-state imaging device according to a fifth embodiment of the present invention.

FIG. 11 is a circuit configuration diagram of a conventional solid-state imaging device.

FIG. 12 is a timing chart illustrating a driving method of a conventional solid-state imaging device.

FIG. 13 is a timing chart illustrating the concept of the afterimage phenomenon.

FIG. 14 is a conceptual diagram illustrating a color mixing phenomenon due to an afterimage.

FIG. 15 is a timing chart illustrating a driving method of a conventional afterimage removal scan.

[Explanation of symbols]

202 light receiving section, 204 phototransistor, 212
Output signal line, 214 output terminal, 216 charge detection capacitor, 218 shift register, 220D flip-flop, 226 reset switch, 230 inverted pulse output section, 232 inverter, 234, 334, 542
Switch, 256 scan clock, 258 inverted scan clock, 260, 262, 264, 266 pixel selection pulse, 330 pulse width switching section, 358 reset clock, 570 start pulse, 572 multi-width start pulse.

Claims (7)

[Claims] 1. A plurality of charge storage type light receiving units, an output signal line for guiding a pixel signal output from these light receiving units to an output terminal, and a charge connected to the output terminal for converting the pixel signal into a voltage signal A detection capacitor, a pixel selection switch provided between each of the light receiving units and the output signal line, and a circuit that performs scanning that sequentially opens and closes each of the pixel selection switches in synchronization with a scanning clock; A pixel scanning circuit that performs a read scan for extracting the pixel signal from the light receiving unit to the output signal line and an afterimage removal scan for extracting the pixel signal remaining on the light receiving unit to the output signal line following this read scan; The reset terminal held,
A reset switch provided between the reset terminal and the output signal line, and closing the reset switch in at least a part of a closing period of each of the pixel selection switches; each of the light receiving units and the charge detection capacitor; An imaging apparatus comprising: a reset control circuit that controls reset of the imaging apparatus; wherein the reset control circuit closes the reset switch longer in the afterimage removal scan than in the readout scan. 2. The reset switch is opened and closed according to a pulse width of a reset control pulse output from the reset control circuit. The reset control circuit has a duty ratio between a read scan and an afterimage removal scan. The imaging apparatus according to claim 1, further comprising an inverted pulse output unit that outputs the inverted reset control pulse. 3. The scan clock has an asymmetrical duty ratio, the inversion pulse output unit includes: an inverter that inverts the scan clock; and an inverter corresponding to the read scan and the afterimage removal scan. 3. The image pickup apparatus according to claim 2, further comprising a switch for switching between the scan clock and the output of the inverter and outputting the reset control pulse. 4. The reset switch is opened and closed in accordance with a pulse width of a reset control pulse output from the reset control circuit. The reset control circuit is configured to reset a reset control pulse between a read scan and an afterimage removal scan. 2. The apparatus according to claim 1, further comprising a pulse width switching unit for switching a duty ratio.
An imaging device according to any one of the preceding claims. 5. The imaging apparatus according to claim 4, wherein the reset switch is kept closed during the afterimage removal scanning. 6. A plurality of charge storage type light receiving units, an output signal line for guiding a pixel signal output from these light receiving units to an output terminal, and a charge connected to the output terminal for converting the pixel signal into a voltage signal. A detection capacitor, a pixel selection switch provided between each of the light receiving units and the output signal line, and a circuit that performs scanning that sequentially opens and closes each of the pixel selection switches in synchronization with a scanning clock; A pixel scanning circuit that performs a read scan for extracting the pixel signal from the light receiving unit to the output signal line and an afterimage removal scan for extracting the pixel signal remaining on the light receiving unit to the output signal line following this read scan; The reset terminal held,
A reset switch provided between the reset terminal and the output signal line, and closing the reset switch in at least a part of a closing period of each of the pixel selection switches; each of the light receiving units and the charge detection capacitor; A reset control circuit for controlling resetting of the pixel, wherein the pixel scanning circuit continues the closed state of each of the pixel selection switches for a predetermined number of scanning clocks during the afterimage removal scanning. apparatus. 7. The imaging device according to claim 1, wherein the pixel scanning circuit continues the closed state of each of the pixel selection switches for a predetermined number of scanning clocks. .