JPH1032713A - Image processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an operation processing, to reduce the scale of the picture delay memory of a two-dimensional processing part to half, to reduce cost and to realize a high speed processing by converting the picture signal of an L bit unto an M bit, executing a picture processing and converting the picture signal of the M bit into an S bit. SOLUTION: The irregularity of the picture signal which is read by a solid- state image pickup element (sensor) 2 is uniformly corrected in a shading correction part 3 and the color of the filter of the sensor 2 is corrected in a color space conversion part 4. A luminance signal from the color space conversion part 4 is converted into a signal having the density level of eight bits ion a logarithm conversion part 8, and the signal is converted into the preudo halftone signal of four bits in a halftone processing part A9. The density signal which is artificially halftone-processed by the four bits of three colors is color-corrected by the characteristic of a color material used in a recording part 6 by a color correction part 10. A halftone processing part B15 artificially halftone-processes the picture signal which is artificially halftone-processed into four bits to one bit and a binary recording signal is outputted to a recording part 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called image processing apparatus for processing an image signal, such as a copying machine, a facsimile, a printer, etc., and more particularly to a pseudo halftone process for converting an input image signal into an image signal having a level lower than the input level. The present invention relates to an image processing device.

[0002]

2. Description of the Related Art Conventionally, an error diffusion method has been widely used for pseudo halftone processing in such a device, for example, a digital copying machine. The error diffusion method binarizes an input 8-bit image signal with a predetermined threshold value, and distributes a binarization error in the binarization to an input signal in the vicinity of a target pixel and at a pixel position to be binarized from now on. This is a method of expressing halftones in a pseudo manner by correcting.

Conventionally, this digital copying machine is: 400D
Images were read and recorded at a density of PI, but printers have recently become 600 DPI, 720 DPI, and 1200 DPI.
And higher resolution is progressing.

[0004]

In order to increase the resolution of a copying machine having the function of a printer, a so-called image processing unit for reading and processing an image is required to have a high speed, and a memory of a two-dimensional processing unit is required. And the cost is problematic. For example, if the resolution of the system is increased from 400 DPI to 600 DPI, in order to achieve the same copying speed, the processing speed of each image processing unit after reading the image is 2.2.
In order to obtain the same function, the spatial filter composed of 5 * 5 pixels has to be processed in a wide area of 7 * 7 pixels or more, and the delay memory has also become 2.25 times. There was a disadvantage.

The present invention eliminates the above-mentioned drawbacks of the prior art. By reducing the number of bits in the processing of each pixel for a multi-valued image signal by half, the operation scale can be reduced and the image of the two-dimensional processing unit can be reduced. It is an object of the present invention to provide an image processing apparatus capable of halving the scale of a delay memory, significantly reducing costs, and performing high-speed processing.

It is another object of the present invention to provide an image processing apparatus capable of performing image processing after reducing the number of bits and thereafter obtaining a high-quality image even if the number of bits is further reduced.

[0007]

In order to achieve the above object, an image processing apparatus according to the present invention converts an L-bit image signal into an M-bit image signal.
(<L) first halftone processing means for performing pseudo halftone processing on bits, image processing means for processing the M-bit image signal, and converting the M-bit image signal image-processed by the image processing means to S A second halftone processing means for performing pseudo halftone processing on (<M) bits, and an output means for outputting based on the S bit signal.

[0008]

Embodiments of the present invention will be described below in detail.

In the present embodiment, an example in which an L (8) bit image signal is converted into M (4) bits, image processing is performed, and then the M bit image signal is converted into S (1) bits. Will be described.

FIG. 1 shows a configuration of an image processing apparatus according to an embodiment of the present invention. The shading correction unit 3 uniformly corrects the unevenness of the image signal read by the solid-state imaging device (sensor 2) at a density of 400 DPI, and the color space conversion unit 4 performs the color correction of the filter of the sensor 2. The luminance RGB signal from the color space conversion unit 4 is converted into a CMY signal having an 8-bit density level by a logarithmic conversion unit 8, and this signal is converted into a pseudo 4-bit pseudo halftone signal by a halftone processing unit A9. Convert.

In the pseudo halftone processing in the intermediate processing unit A9, only 4 bits and 16 levels of density level can be expressed in each pixel unit, but when viewed spatially in a predetermined area including a plurality of pixels, the density level of 8 bits is obtained. Is expressed. The density signals subjected to pseudo halftone processing for each of the four bits of each of the three colors Y, M, and C are color-corrected by a color correction unit 10 according to the characteristics of the color materials used in the recording unit 6. The magnification is changed by the conversion unit 11 as necessary, and then 400
Data of I (Dot Per Inch) is 600DP
Convert to I density. The conversion process in the resolution conversion unit 12 and the conversion process in the scaling unit 11 may be performed simultaneously. The spatial filter 13 corrects sharpness,
And moiré removal. The density adjustment is performed by the γ correction unit 13. On the other hand, the image area separation unit 6 performs image recognition processing for performing the adaptive processing according to the attributes of the image in the processing units of the resolution conversion unit 12 and the spatial filter 13 described above. Particularly, in order to sharply record a black character portion in an image with a single black color, an image area determination of a black character and other image areas is performed. The halftone processing unit B15 further performs pseudo halftone processing on the image signal that has been subjected to the pseudo halftone processing to 4 bits up to 1 bit, and outputs a binary recording signal to the recording unit 16. The external IF 5 and the external I / F are interfaces for inputting and outputting 8-bit and 1-bit image signals to and from the outside. Here, the feature of the present embodiment is that, as described above, the processing of each pixel for a so-called multi-valued image signal is halved by using the pseudo halftone processing unit A9, and the color correction unit 10 is used. Can be reduced, and the scale of the image delay memory of the two-dimensional processing unit such as the scaling unit 11 and the spatial filter 13 can be reduced by half. Therefore, significant cost reduction and high-speed processing can be achieved.

(Embodiment 1 of the halftone processing section A9) FIG.
Is an embodiment of the halftone processing unit A9 for one color of the 8-bit density signal CMY logarithmically converted by the logarithmic conversion unit 8. The other two colors can be realized with the same configuration. The density signal 92 from the logarithmic converter 8 is multiplied by 1 by a multiplier 91.
If it is multiplied by / 17, the result is a 4-bit signal. On the other hand, when this signal is multiplied by 17 in the multiplier 93 and subtracted from the original 8-bit signal 92 in the adder 98, the density signal 92 is multiplied by 1 in the multiplier 91.
/ 17 times the remainder (0-16). The remainder signal is obtained from 0 to 1 obtained by the pseudo random number generator 97 without including the equal sign.
A 1-bit signal can be obtained by binarizing the comparator 95 with 1 when the signal is larger than 6 and 0 when the signal is smaller than 6. The 1-bit comparison result is added by an adder 94 to a 4-bit signal obtained by multiplying the density signal 92 described above by 1/17 in a multiplier 91, and
A 4-bit pseudo-halftone processing signal 96 is obtained.

Since the pseudorandom numbers almost uniformly generate values of 0 to 16 in a region of 17 pixels or more in the vicinity, a density of approximately 8 bits is pseudo-expressed in a region of 17 pixels. Therefore, even if the 8-bit data is reduced to 4-bit data, the subsequent image processing can be performed faithfully on the input data.

(Embodiment 2 of Halftone Processing Unit A9) FIG.
Divides the 8-bit signal described in FIG. 2 by 17 (4
This is an example of performing the so-called LUT conversion using the memory 99 and the remaining 0 to 16 signals, and can be implemented by a 256-word 9-bit RAM or ROM. Since the logarithmic conversion is performed at the same time, the input of the memory 99 is the output signal 80 of the color space converter 4 before the logarithmic conversion. Since the embodiment of FIG. 3 can be implemented only by increasing the LUT memory for normal logarithmic conversion by 1 bit width, it can be implemented at lower cost.

(Embodiment 3 of the halftone processing section A9) FIG.
Is another example in which binarization by random numbers and addition are performed by LUT conversion in addition to the embodiment of FIG.
Is added as a 5-bit random number. Therefore, the memory 9
9 is 4 bits of 8K words, but is effective in a low-speed system or when implemented by software on a computer.

The 8-bit to 4-bit pseudo-halftone processing unit A9 is not limited to the embodiment shown in FIGS. 2 to 4 of the present invention. For example, an error diffusion method with error correction,
The pseudo-halftone processing of the density-preserving type, such as the method disclosed in Japanese Patent Application Laid-Open No. 2-210963 already disclosed by the present inventor, can be all applied. Also, in the present embodiment, an example of 8 bits to 4 bits has been disclosed, but when the resolution of recording and reading is sufficiently high, the same effect can be obtained by processing from 8 bits to 3 bits and 2 bits.

Next, the details of the color correction section 10 of FIG. 1 will be described.

(Embodiment of Color Correction Unit 10) Next, an embodiment of the color correction unit 10 will be described in detail with reference to FIG. Basically, black generation and color correction performed by a conventional matrix operation may be performed on 4-bit C, M, and Y input signals. However, since the number of input bits is reduced by half, LUT conversion is performed. , A so-called direct mapping system using That is, the CMYK four-color signals, which have been color-corrected for the combinations of the CMY signals obtained in advance by using the 4K word, 16-bit memory 100, are assigned to four bits and stored.

Although each input pixel is reduced to a 16-bit expression color number, as described above, it can be said that a 32-bit color expression is possible when viewed averagely for 17 pixels.

In the scaling unit 11, the resolution conversion unit 12, and the spatial filter 13, a conventionally known method is used. However, the number of bits of a memory for delay-holding an image associated with each processing in units of lines is reduced by half. The uniform 8-bit signal is 4-bit in the above-described pseudo halftone processing unit A9, and the level randomly fluctuates by one level between adjacent pixels. * If the filter has 5 pixels and the filter has a weight coefficient at all 25 pixels, the reference pixel area of the processing is the aforementioned 17 pixel.
Since the number of pixels is equal to or larger than the number of pixels, generation of unnecessary noise is extremely small. In addition, in the case of a general Laplacian filter, a good result can be obtained similarly if the edge is emphasized using only the Laplacian component corresponding to the change of level 2 or more.

In general, for a character, the visual characteristics of a person are 4 lines / m because the finer the thin line, the more difficult it is to identify the gradation.
Even from the knowledge that a 4-bit gradation number is sufficient for a thin line of about m, the resolution characteristics do not deteriorate.

(Embodiment 1 of the Halftone Processing Unit B15) FIG. 6 shows an embodiment of the halftone processing unit B15. The halftone processing unit B15 outputs the 4-bit image signal 1 from the γ conversion unit 14.
Pseudo halftone processing of 40 into 1 bit.

A binarization error obtained at the time of binarization of an adjacent pixel is added to an input signal 140 by an adder 151 and binarized by a comparator 152. The threshold value at the time of binarization is such that the binarized signal
A sum-of-products operation 154 is performed by storing the binary data held in the line delay holding memory 153 and binarized in the past and the weighting coefficient 155.
To obtain the sum of products. The total sum of the weight coefficients used is 15.

The difference between the threshold value and the error-corrected signal is obtained by an adder 157. This is a binarization error. The error is divided into two by an error distributor 158, one of which is added to the adder 161 as an error at the time of binarization of the next pixel, and the other is delayed by a line by a delay holding memory 159 for one line,
Add to 1.

Therefore, the binarization error of the target pixel (*) is obtained by adding the immediately preceding binarization error one line before and by the adder 161, and the input signal 140 is corrected by the adder 151.

The binarization method of the halftone processing section B15 is not limited to the above-described embodiment, but may be a density-conserving type such as an error diffusion method. If the recording / display device has a 2-bit, that is, 4-value expression capability, the 4-bit signal is processed into a 2-bit signal.

As described above, according to the present embodiment, in order to reduce the hardware scale when performing various types of image processing, the number of bits is reduced by using multi-value pseudo halftone processing for input image data. After performing various processes such as color correction, binarization for recording is performed again by pseudo halftone processing.

Here, in order to express a halftone with a good texture by using the error diffusion method, it is known that an error diffusion region is set to be sufficiently wide, and when an 8-bit image data is processed. As shown in FIG. 7, at least about E / 48 (E
Requires an error distribution of a binarization error generated in the target pixel). The error that occurs is about the range of the input image signal. In the case of a 4-bit image signal, the distribution error due to this error distribution ratio is almost zero. That is, substantially 1
It is impossible to correct an error in a two-pixel area with a desired distribution ratio. That is, it is difficult to obtain a good halftone image as in the related art for an image signal having a small number of bits.

Therefore, a pseudo halftone processing method capable of diffusing the binarization error over a wide range even for an image having a small number of input bits and expressing a halftone with a good texture is described in the embodiment of the halftone processing section B15. This will be described below.

(Embodiment 2 of the Halftone Processing Unit B15) FIG. 8 shows an embodiment in which the 4-bit (0 to 15) image signal F from the gamma conversion unit 14 is binarized. An adder 218 adds error correction data, which will be described later, and an input signal F, and outputs the output 208 to a comparator 206 using a predetermined threshold value T.
Value.

The binarization error E of the target pixel is: E = (F + ＦE ^* R) −B ^* 15 where B is the binarization result 15 of the target pixel, and ΔE ^* R is the binarization result near the target pixel. This is a weighted average value of the binarization error generated at the pixel position where the pixel has ended and the error with respect to the target pixel using the weight coefficient R.

Therefore, the error E is obtained by subtracting the value obtained by multiplying the binarization result 215 by 15 by the multiplier 207 from the error-corrected image data 208 by the adder 209.

The FIFs 202 and 203 hold this error one line at a time and input it to the weighted average circuit 201 together with the binarization error of the pixel line of interest.

The weighted average circuit 201 is a product-sum operation unit that can simultaneously reference (by a latch circuit, not shown) a binarization error generated at a pixel position of 12 pixels near the target pixel for which binarization has already been completed. The weighting factor to be calculated is 2
Multiply and add the quantification error. The sum of the weighting factors is 16
Therefore, if the result is multiplied by 1/16 in the multiplier 205, a correction error E for the target pixel position is obtained.

The feature of this embodiment is that the binarization error generated at the target pixel position is not distributed to several pixels, but the generated error itself is delayed and held, and the weighted average is used when binarizing the target pixel. To obtain a correction error.

As a result, it is possible to reflect an error with a small distribution ratio (a small weight value) on the target pixel without a calculation error.

In the multiplier 205, a maximum of 15
Error occurs. FIG. 9 shows an example in which this calculation error is further corrected.

In FIG. 9, if the calculation result of the multiplier 205 is multiplied by 16 by the multiplier 211 and subtracted from the input value to the multiplier 205 by the adder 217, a calculation error, that is, a truncation error is obtained. The error is calculated by the flip-flop 216 as 1
The delay is maintained during the pixel processing, and is added to the above-mentioned weighted average value by the adder 204, thereby completing the correction.

That is, the correction can be made on the pixel next to the truncation error. Thereby, complete error correction becomes possible. When the sum of the weighting coefficients is large, the correction in this example is effective, and higher-quality halftone reproduction can be performed.

FIG. 10 further shows error memories 203 and 202.
This is an example in which the bit width is reduced. The aforementioned error E requires 6 bits including a polarity bit for a 4-bit image signal. To reduce the number of bits by 2 bits, a multiplier 2
The lower 2 bits of the error obtained in step 13 are discarded. The result is quadrupled by the multiplier 214 and subtracted by the adder 212 from the input value of the multiplier 213 to obtain a truncation error.
This error can be corrected by holding the error with a delay of one pixel by the flip-flop 210 and adding it to the adder 218. That is, the lower 2 bits of the generated error are truncated,
The bit width of the error memory is reduced to reduce the cost, and the truncated two bits are sequentially corrected for error in the next pixel binarization.

Although the description is omitted, in this case, it is needless to say that the average value calculation unit 201 calculates each input error data by bit shifting it four times.

The above processing may be further performed at the output unit of the FIFO 203. That is, in the FIFO 202, the weighting coefficient of the present example is as small as 2 for the pixel that is the farthest reference to the line including the target pixel. Therefore, the number of bits can be further reduced. Also in this case, the reduced data is corrected by the next pixel, so that the binarized image does not deteriorate.

Similarly, by limiting the binarization error of the pixel of interest obtained by the adder 209 within a predetermined range, the FIFO
3, 2 bits can be reduced. That is, the generated error is limited to a range of -15 to +15 to be 5 bits, and if it exceeds this range, the excess error is corrected at the time of the next pixel binarization, as in the error correction processing of FIG. . Normally, since the error of the maximum value +15 cannot occur continuously, correction on adjacent pixels is possible.

Incidentally, the weight coefficient for obtaining the error is not limited to that of the present embodiment, and for example, the one shown in FIG. 11 can be used.

As described above, according to the second embodiment of the halftone processing section B, the error diffusion method is used for an image signal having a small number of bits in density, and the binarization error can be diffused over a wider range. The halftone can be reproduced with good texture. Also, the hardware scale can be reduced.

It goes without saying that the present invention is not limited to recording and display systems such as electrophotography using ink jet, LED, and laser. In the embodiment, the color device is used.
Similar effects can be obtained even with a monochrome device.

[0047]

As described above, according to the present invention, an extremely inexpensive and high-quality image expression can be realized even if the resolution of the image is increased.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment.

FIG. 2 is a block diagram illustrating a configuration of a halftone processing unit A according to the first embodiment.

FIG. 3 is a block diagram showing a configuration of a halftone processing unit A according to a second embodiment.

FIG. 4 is a block diagram showing a configuration of a halftone processing unit A according to a third embodiment.

FIG. 5 is a block diagram illustrating a configuration of a color correction unit.

FIG. 6 is a block diagram showing a configuration of a halftone processing unit B according to the first embodiment.

FIG. 7 is a block diagram showing an example of an error diffusion matrix.

FIG. 8 is a block diagram showing a configuration of a halftone processing unit B according to a second embodiment.

FIG. 9 is a block diagram showing another configuration of the halftone processing unit B.

FIG. 10 is a block diagram showing another configuration of the halftone processing unit B.

FIG. 11 is a block diagram showing an example of an error diffusion matrix.

Claims (5)

[Claims] A first halftone processing unit that performs pseudo halftone processing on an L-bit image signal into M (<L) bits; an image processing unit that processes the M-bit image signal; and the image processing unit A second halftone processing unit that performs pseudo halftone processing on an M-bit image signal that has been subjected to image processing according to (1) to S (<M) bits, and an output unit that outputs an image based on the S-bit signal. Characteristic image processing device. 2. The method according to claim 1, wherein the second halftone processing unit delays and retains an error generated when the second halftone processing unit has already converted the bit into S bits.
Means for calculating a weighted average value using a conversion error of a plurality of pixel positions adjacent to the pixel of interest and an integer coefficient, and an error for correcting an input image signal of the pixel of interest by a value obtained by dividing the weighted average value by the sum of coefficients 2. The image processing apparatus according to claim 1, further comprising: a correction unit; a conversion unit configured to convert the correction value into an S-bit signal; and a unit configured to calculate an error generated by the conversion. 3. The image processing apparatus according to claim 2, wherein the error correction unit corrects an error generated by the division when converting adjacent pixels. 4. The image processing apparatus according to claim 2, wherein said error calculating means further corrects an error generated by rounding of a bit when converting an adjacent pixel. 5. The apparatus according to claim 2, wherein said error calculating means includes means for reducing an error generated and a value within a predetermined value, and corrects an error generated by the reduction processing when converting adjacent pixels. Image processing device.