JPH10340920A5 - - Google Patents
Info
- Publication number
- JPH10340920A5 JPH10340920A5 JP1997151749A JP15174997A JPH10340920A5 JP H10340920 A5 JPH10340920 A5 JP H10340920A5 JP 1997151749 A JP1997151749 A JP 1997151749A JP 15174997 A JP15174997 A JP 15174997A JP H10340920 A5 JPH10340920 A5 JP H10340920A5
- Authority
- JP
- Japan
- Prior art keywords
- pad portion
- opening
- conductive
- wiring
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Description
【発明の名称】半導体装置の製造方法および半導体装置 [Title of Invention] Semiconductor device manufacturing method and semiconductor device
【０００１】
【発明の属する技術分野】
本発明は半導体装置の製造方法および半導体装置に関し、特に搭載基板の導電部と半導体チップの配線とのワイヤーボンディングに適用される半導体装置の製造方法および半導体装置に関する。[0001]
[Technical Field to which the Invention Belongs]
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device and a manufacturing method thereof that are applicable to wire bonding between conductive parts of a mounting substrate and wiring of a semiconductor chip.
【００５０】
【発明の効果】
以上説明したように本発明の半導体装置の製造方法および半導体装置によれば、開口部内にＡｌを含む導電材料からなる導電膜を形成してパッド部を得た後、パッド部と搭載基板の導電部とをワイヤーボンディングするようにしたことにより、たとえワイヤーとの接合が困難な配線材料を外側に臨ませた状態で開口部が形成されていても、パッド部とワイヤーとが密着性良く接合することができる。また、配線が薄膜化したＡｌからなっていても、このＡｌ配線上にＡｌを含む導電膜を形成してパッド部を得ることから、パッド部のＡｌとワイヤーとの固層拡散を十分に進ませることができ、接合部におけるボイドの発生を防止できる。したがって、電気的信頼性が高い高集積ＬＳＩからなる半導体装置を実現することができる。[0050]
[Effects of the Invention]
As described above, according to the semiconductor device manufacturing method and semiconductor device of the present invention, a conductive film made of a conductive material containing Al is formed in an opening to obtain a pad, and then the pad is wire-bonded to a conductive portion of a mounting substrate. This allows for good adhesion between the pad and the wire, even if the opening is formed with a wiring material that is difficult to bond to the wire exposed to the outside. Furthermore, even if the wiring is made of thin Al, the pad is obtained by forming a conductive film containing Al on the Al wiring, which allows for sufficient solid-state diffusion between the Al in the pad and the wire, preventing the occurrence of voids at the bond. Therefore, a semiconductor device with a highly integrated LSI having high electrical reliability can be realized.
Claims (5)
前記パッド部を形成した半導体チップを搭載基板に搭載して、前記パッド部と前記搭載基板の導電部とをワイヤーボンディングする工程とを有している
ことを特徴とする半導体装置の製造方法。a step of using a semiconductor chip having wiring on the top surface of a substrate, an insulating film covering the wiring, and an opening formed in the insulating film to expose the wiring to the outside, and selectively forming a conductive film made of a conductive material containing aluminum within the opening of the semiconductor chip to obtain a pad portion;
a step of mounting the semiconductor chip on which the pad portion is formed on a mounting substrate, and wire-bonding the pad portion to a conductive portion of the mounting substrate.
ことを特徴とする請求項１記載の半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of obtaining the pad portion, the conductive film is formed by selectively growing aluminum in the opening by chemical vapor deposition.
ことを特徴とする請求項１記載の半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of obtaining the pad portion, a film of the conductive material is formed on the entire surface of the insulating film and the opening is filled with the conductive material, and then the conductive film is formed by using a chemical mechanical polishing method to remove the film of the conductive material up to a position where the top surface of the insulating film is exposed while leaving the conductive material that filled the opening.
ことを特徴とする請求項１記載の半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming a barrier metal film so as to cover the inner surface of the opening prior to the step of obtaining the pad portion.
前記半導体チップは、基体の上面に配線とこれを覆う絶縁膜と該絶縁膜に形成されて前記配線を外側に臨ませる開口部とを有しており、the semiconductor chip has, on the upper surface of a base, wiring, an insulating film covering the wiring, and an opening formed in the insulating film to expose the wiring to the outside;
前記パッド部は、前記開口部内に選択的にアルミニウムを含む導電材料からなる導電膜を形成してなるThe pad portion is formed by selectively forming a conductive film made of a conductive material containing aluminum in the opening.
ことを特徴とする半導体装置。A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15174997A JP3906522B2 (en) | 1997-06-10 | 1997-06-10 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15174997A JP3906522B2 (en) | 1997-06-10 | 1997-06-10 | Manufacturing method of semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPH10340920A JPH10340920A (en) | 1998-12-22 |
| JPH10340920A5 true JPH10340920A5 (en) | 2005-03-17 |
| JP3906522B2 JP3906522B2 (en) | 2007-04-18 |
Family
ID=15525454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15174997A Expired - Fee Related JP3906522B2 (en) | 1997-06-10 | 1997-06-10 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3906522B2 (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW426980B (en) * | 1999-01-23 | 2001-03-21 | Lucent Technologies Inc | Wire bonding to copper |
| JP2003031575A (en) | 2001-07-17 | 2003-01-31 | Nec Corp | Semiconductor device and manufacturing method thereof |
| JP2003303848A (en) * | 2002-04-12 | 2003-10-24 | Nec Compound Semiconductor Devices Ltd | Semiconductor device |
| KR20040045109A (en) * | 2002-11-22 | 2004-06-01 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| JP2004221098A (en) | 2003-01-09 | 2004-08-05 | Renesas Technology Corp | Semiconductor device and method of manufacturing the same |
| JP2008091454A (en) * | 2006-09-29 | 2008-04-17 | Rohm Co Ltd | Semiconductor device and manufacturing method of semiconductor device |
| US7485564B2 (en) * | 2007-02-12 | 2009-02-03 | International Business Machines Corporation | Undercut-free BLM process for Pb-free and Pb-reduced C4 |
| JP4701264B2 (en) * | 2008-04-18 | 2011-06-15 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| JP5582879B2 (en) * | 2010-06-09 | 2014-09-03 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| JP5621712B2 (en) * | 2011-06-06 | 2014-11-12 | 株式会社デンソー | Semiconductor chip |
| JP2014222742A (en) * | 2013-05-14 | 2014-11-27 | トヨタ自動車株式会社 | Semiconductor device |
| DE102016101801B4 (en) | 2016-02-02 | 2021-01-14 | Infineon Technologies Ag | LOAD CONNECTION OF A POWER SEMICONDUCTOR ELEMENT, POWER SEMICONDUCTOR MODULE WITH IT AND MANUFACTURING PROCESS FOR IT |
| JP7379845B2 (en) * | 2019-03-28 | 2023-11-15 | セイコーエプソン株式会社 | Semiconductor devices, semiconductor device manufacturing methods, electronic devices, electronic equipment, and mobile objects |
-
1997
- 1997-06-10 JP JP15174997A patent/JP3906522B2/en not_active Expired - Fee Related
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