JPH1041402A - Overcurrent protection type DMOS FET - Google Patents

Abstract

(57) Abstract: A high-breakdown-voltage DMOS FE having a built-in protection structure for determining an upper limit value of a flowing current in order to prevent an overcurrent.
Implement T. An overcurrent protection type DMOS FET according to the present invention is provided.
A drain layer having a high concentration of the second type impurity formed in a second type impurity semiconductor layer formed on the first type impurity semiconductor substrate, and a drain electrode connected thereto;
A first type impurity semiconductor layer formed in the seed impurity semiconductor layer at a position separated from the drain layer, and a first type impurity formed on the side of the first type impurity semiconductor layer close to the drain layer. A semiconductor layer having a high concentration, a source layer having a second-type impurity concentration also formed on the far side, a source electrode commonly connected to the source layer and the semiconductor layer having a high-type impurity concentration, A junction type FET comprising a gate electrode formed on a side of the source electrode far from the drain electrode and opposed to the source layer and the first type impurity semiconductor layer via an insulating film; and a DMOS FET.
Are connected in series to form an integrated structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a high breakdown voltage DMOS FET for preventing an overcurrent from flowing.

[0002]

2. Description of the Related Art A conventional high withstand voltage DM having a double diffusion structure.
In the case of an OS FET, when an overcurrent occurs due to an abnormality in a load or the like when the gate is ON (the channel is in a conductive state),
The current may pass through the high-breakdown-voltage DMOS FET as it is and destroy elements located downstream. FIG. 3 is a sectional view showing the structure of a conventional high-breakdown-voltage DMOS FET. Reference numeral 1 denotes a silicon substrate made of a p-type impurity. Reference numeral 2 denotes an n-type semiconductor layer made of an epitaxial layer or a diffusion layer formed on the p-type substrate 1. Reference numeral 3 denotes a p-type semiconductor region formed in the n-type semiconductor layer 2. 4 is the p
It is a source region of a high-concentration n-type semiconductor formed in the type semiconductor region 3. Hereinafter, regions in which impurities are diffused are formed respectively. 5 is a source region of a high concentration p-type semiconductor, and 6 is a drain region of a high concentration n-type semiconductor. Reference numeral 7 denotes a drain electrode, 8 denotes a gate electrode, and 9 denotes a source electrode, which are extracted from the respective impurity layers. Reference numeral 10 denotes an insulating film (silicon oxide film). The gate electrode 8 extends over the p-type semiconductor region 3 and the source layer 4 via the insulating film. In such a structure, when a positive voltage is applied to the gate electrode 8, the polarity of the p-type semiconductor region 3 at the portion opposed to the gate electrode 8 and separated by the insulating film is inverted to n-type. This part is called an n-type channel. The withstand voltage and the ON resistance (R _ON ) of the channel are determined by the impurity concentration (doping concentration) of this portion and the shape and dimensions of the layer. In this way, the drain layers 6 to n
All of the paths are connected by the n-type semiconductor to the source region 4 through the type semiconductor layer 2 and the channel portion whose polarity is inverted to the n-type, and a current path is formed. Therefore, when a high voltage is applied to the drain electrode 7, the current flowing into the drain region 6 of the high-concentration n-type semiconductor flows through the above-described path and flows into the source electrode 9. This current can be obtained by V _D / R _ON from the voltage V _D applied to the drain region 6 and the value of R _ON . This current needs to be limited because it becomes excessive depending on the values of V _D and R _ON .

[0003]

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-breakdown-voltage DMOS FE having a built-in protection structure for determining an upper limit value of a flowing current in order to prevent the above-mentioned overcurrent.
It is to realize T.

[0004]

An overcurrent protection type D according to the present invention is provided.
The MOS FET includes a drain layer (6) having a high concentration of the second type impurity formed in a second type impurity semiconductor layer (2) formed on the first type impurity semiconductor substrate (1) and connected thereto. A drain electrode (7); a first-type impurity semiconductor layer (3) formed in the second-type impurity semiconductor layer (2) at a position separated from the drain layer (6); A semiconductor layer (5) having a high concentration of the first type impurity formed on the side closer to the drain layer (6) in the impurity semiconductor layer (3), and a source having a high concentration of the second type impurity also formed on the side farther from the drain layer (6). Layer (4), this source layer (4) and said 1
A source electrode (9) commonly connected to the semiconductor layer (5) having a high seed impurity concentration, and the source layer (4) and the source electrode (9) on a side of the source electrode (9) far from the drain electrode (7). It is described that a junction type FET constituted by a gate electrode (8) formed with an insulating film opposed to the first type impurity semiconductor layer (3) and a DMOS FET are formed in an integrated structure of series connection. Features.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a conventional high breakdown voltage DMOS FET described above and a junction type FMOS having a current limiting characteristic.
A high voltage DMOS FET having a current protection structure is realized by integrally configuring an ET (hereinafter, referred to as a JFET). Hereinafter, the present invention will be described with reference to the drawings. FIG. 1A is a cross-sectional view of an overcurrent protection type high breakdown voltage DMOSFET showing an example of an embodiment of the present invention. First
An example in which the seed impurity is a p-type impurity and the second impurity is an n-type impurity will be described. It can also be manufactured by replacing p and n. Reference numeral 1 denotes a silicon substrate made of a p-type impurity. Reference numeral 2 denotes an n-type semiconductor layer of an epitaxial layer or a diffusion layer formed on a p-type substrate. The breakdown voltage and the ON resistance (channel resistance R _ON ) are determined by the impurity concentration (doping concentration) and the shape of the layer. Reference numeral 3 denotes a p-type semiconductor region formed by appropriately diffusing, for example, boron through masking and etching processes. Reference numeral 4 denotes a source region of a high-concentration n-type semiconductor, for example, a region in which phosphorus is diffused at a high concentration. 5 is a source region of a high concentration p-type semiconductor, and 6 is a drain region of a high concentration n-type semiconductor. A drain electrode 7 is connected to the drain region 6. A gate electrode 8 faces the p-type semiconductor region 3 with an insulating film interposed therebetween. This part is called a channel. A source electrode 9 is connected to the source regions 4 and 5. Reference numeral 10 denotes an insulating film. The gate electrode 8 extends over the drain layer with the insulating film (silicon oxide film) interposed therebetween.

The structure of FIG. 1A is characterized by the positions of the high-concentration n-type semiconductor regions 4 and the high-concentration p-type semiconductor regions 5 formed on the surface of the p-type semiconductor region 3 shown in FIG.
Is that the position of has been replaced. With this arrangement, the drain current _ID is increased by JFET and DMO.
It is characterized in that the maximum current is limited for the following reasons because it passes through the SFET in series. FIG.
FIG. 4A is a diagram showing that the depletion layers (e) and (f) expand as the potential of the drain electrode 7 becomes higher than the potential of the source electrode 9 shown in FIG. When a positive voltage is applied to the gate, the polarity of the channel portion of the p-type semiconductor region 3 separated from the gate electrode 8 by the insulating film is inverted to n-type.
Source region 4, n-type semiconductor layer 2, p-type semiconductor region 3
A channel made of an n-type semiconductor comprising a channel portion having the polarity inverted and a drain region 6 is formed. Therefore, when a high voltage is applied to the drain electrode 7, the current _ID flowing into the drain region 6 flows through the above-described path, and the current _ID flows into the depletion layers (e) and (f) formed in the n-type semiconductor layer 2. It passes through the gap, passes through point (g), flows into the source electrode 9 through the n-type inversion layer facing the gate electrode 8. After the point (g) in the middle of the current path, the high voltage DMOS FET portion controlled by the gate electrode 8 and flowing to the source region 4 when the current flows through the channel portion is connected in series to the subsequent stage of the JFET. Structure. The size of the gap between the depletion layers (e) and (f) becomes smaller as the voltage applied to the drain electrode 7 increases, and the resistance of the current path increases, so that the drain current _ID is limited. Become. Therefore, the drain current _ID is 0 < _ID <V _Dsat / R
_An upper limit can be brought into the range of _ON (= I _MAX ). The voltage V _{Dsat at} which the current is saturated according to the structure and the impurity concentration can also be obtained by the following equation. (V _G =
0) q: electron charge, N _D : impurity concentration in the channel region d: JFET channel width, K _S = dielectric constant of Si, ε ₀ : dielectric constant of vacuum, Φ _B : diffusion voltage of gate junction (A. (S. Grove has a description related to Chapter 8 of Basics of Semiconductor Devices (published by Ohmsha).)

FIG. 2 shows the above-mentioned high voltage DMOS FET and JMOS.
3 shows an equivalent circuit in which an FET and an FET are connected in series. The drain (D), gate (G) and source (S) in FIG.
Since they correspond to 8 and 9, the symbols are also shown. (G) point in FIG.
This is the same potential point indicated by point (g) in (b). Generally JF
ET is such that when the drain voltage V _D is increased by setting the source and gate potentials to zero and the drain voltage V _D is increased, when the drain current I _D reaches a certain value V _Dsat , even if a higher voltage is applied, the drain current I _{D D} saturates and does not increase. The reason is that as the drain voltage V _D is increased, J
A depletion layer (e) formed near the gate of the FET portion (in the case of the figure, the p-type semiconductor region 3 acts as a gate);
This is because the gap with the depletion layer (f) formed in the n-type layer 2 on the surface of the p-type substrate becomes narrow, and the drain current _ID is limited because the resistance of the current path increases. This effect protects the high breakdown voltage DMOS FET from overcurrent.

[0008]

According to the present invention, a conventional high-breakdown-voltage DMOS is
The overcurrent flowing when the gate of the FET is ON is J
By having an integrated structure in which FETs are inserted in series, it is possible to limit to an arbitrary design value.

[Brief description of the drawings]

FIG. 1 shows a high breakdown voltage DM showing an example of an embodiment of the present invention.
FIG. 3 is a cross-sectional view of an OS FET.

FIG. 2 is an equivalent circuit of the high voltage DMOS FET of the present invention.

FIG. 3 is a cross-sectional view of a conventional high-breakdown-voltage DMOS FET.

[Explanation of symbols]

 1 is a p-type silicon substrate 2 is an n-type semiconductor layer 3 is a p-type semiconductor region 4 is a high concentration n-type semiconductor source region 5 is a high concentration p-type semiconductor source region 6 is a high concentration n-type semiconductor drain region 7 is a drain electrode 8 Indicates a gate electrode 9, a source electrode 10, an insulating film g, and a point having the same potential in FIGS. 1 and 2. e is a depletion layer surrounding the p-type semiconductor region 3 f is a depletion layer generated in the n-type semiconductor layer 2

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication location H01L 29/808 9447-4M H01L 29/80 P 21/338 29/812

Claims (1)

[Claims] 1. A drain layer having a high concentration of a second type impurity formed in a second type impurity semiconductor layer formed on a first type impurity semiconductor substrate, and a drain electrode connected thereto.
A first type impurity semiconductor layer formed in the second type impurity semiconductor layer at a position away from the drain layer; and a first type impurity semiconductor layer formed in the first type impurity semiconductor layer on a side closer to the drain layer. A semiconductor layer having a high concentration of one type impurity, a source layer having a high concentration of a second type impurity also formed on the far side,
A source electrode commonly connected to the source layer and the semiconductor layer having a high concentration of one type of impurity; and a source electrode and the first layer on a side of the source electrode remote from the drain electrode.
A junction type FET composed of a gate electrode formed with an insulating film opposed to the seed impurity semiconductor layer;
An overcurrent protection type DMOS FET, wherein the FET and the FET have an integrated structure connected in series.