JPH1041504A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Problem] To sufficiently lower the sheet resistance of a gate electrode and a source / drain region. A heat treatment is performed on a silicon substrate at a temperature higher than 700 ° C. so that a titanium film and a source / drain region, and a titanium film and a gate electrode, each having a thickness of 35 nm or less, are heated. Let react. The reaction product thus formed is subjected to a heat treatment at 800 ° C. or more to remove a reaction product between the titanium film 9 ′ and the source / drain region 8 and a reaction product between the titanium film 9 ′ and the gate electrode 7. Each phase transition is performed, and the C ₅₄ TiSi ₂ crystal already formed by the thermal reaction is used as a growth nucleus to facilitate the growth of C ₅₄ TiSi ₂ in the phase transition step.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MIS type semiconductor device having a gate structure and source / drain regions.

[0002]

2. Description of the Related Art In recent years, in a MOS type semiconductor device which is a kind of MIS type semiconductor constituting a super LSI, it has become necessary to reduce the resistance of a source / drain region and a gate electrode in order to shorten a processing time. ing. FIG. 9 shows a general example of such a low resistance. This semiconductor device has a gate structure 100 in advance.
(Including a gate oxide film 101 and a gate electrode 102), a source / drain region 103, and a silicon film 105 on which a sidewall 104 has been formed. Further, by performing heat treatment, the titanium film is selectively reacted with the source / drain region 103 and the gate electrode 102 to form a titanium silicide 106. The unreacted titanium film is then removed. Note that reference numeral 107 in the figure denotes a field oxide film.

In the semiconductor device in which the titanium silicide 106 is formed as described above, the source / drain region 10
3 and the gate electrode 102 are reduced in resistance by the titanium silicide 106 formed thereon in a self-aligned manner. (For example, T. Tsukamoto et al. Ext. Abst. On SS
DM, pp45, 1984).

However, in this structure, in order to form the titanium silicide 106 having a low resistance characteristic, it is necessary to perform a heat treatment at a high temperature of 700 ° C. or more, and, as shown in FIG. , Titanium silicide 106 on the side of gate electrode 102 and source / drain region 103
Side titanium silicide 106 grows in a lateral direction and comes into contact with each other. ・ The reactant of silicon oxide and titanium forming side wall 104 forms side wall 104 from gate electrode 102 to source / drain region 103. There is a possibility that a phenomenon such as formation on the surface may occur, causing a short circuit between the gate electrode 102 and the source / drain region 103 to cause a junction leak.

Therefore, conventionally, titanium silicide 10
By performing the heat treatment for forming No. 6 twice at a low temperature and a high temperature, the occurrence of the junction leak was prevented. Hereinafter, a conventional method of manufacturing a semiconductor device in which junction leakage is prevented will be described with reference to FIG.

That is, first, as shown in FIG. 10A, a titanium film is formed on a silicon substrate 105 on which a field oxide film 107, a gate structure 100, a sidewall 104, and a source / drain region 103 have been formed. 110 is deposited by a sputtering method.

Next, as shown in FIG. 10B, the first heat treatment is performed by a lamp annealing method in a nitrogen atmosphere of 1 atm or less at a heating temperature (700 ° C. or less) and a treatment time (30 to 60 seconds). I do. By this step, the gate electrode 10
2, a selectively silicon and titanium on the source / drain region 103 to form an intermediate reactant layer 111 made of the reaction mainly C ₄₉ TiSi _2.

At this time, the reaction with nitrogen in the atmosphere proceeds on the surface of the titanium film 110, so that the intermediate reactant layer 11
1, sidewall 104, and field oxide film 2
A titanium nitride film 112 is formed thereon. However, unreacted titanium may remain on the sidewalls 104 and the field oxide film 107 in some cases. At this time,
Since the treatment is performed at a relatively low heating temperature of 700 ° C. or less,
No lateral growth of the intermediate reactant layer 111 that causes junction leakage occurs.

Next, as shown in FIG. 10C, H ₂ S
The titanium nitride 112 and the unreacted titanium film 110 are removed using a mixed solution of O ₄ : H ₂ O ₂ .

Next, as shown in FIG. 10 (d), a heating temperature (800 ° C. or higher) and a processing time (30 to 60 seconds) are usually set in a nitrogen atmosphere of 1 atm or less by a lamp annealing method.
A second heat treatment is performed. By the second heat treatment, the intermediate reactant layer 111 having a characteristic of high resistance (60 μΩcm)
Is a titanium silicide 10 mainly composed of C ₅₄ TiSi ₂ having a phase transition and low resistance (16 μΩ / cm).
Change to 6. (For example, K. Fujii et al. Symp. VLSI. Tec
h., pp57, 1995).

In this way, the titanium silicide 106
, The source / drain region 103
And the resistance value of the gate electrode 102 is set to a sheet resistance of 10Ω / sq. Required for speeding up the aAMOS type semiconductor device. It can be: In addition, the second heat treatment only causes a phase transition of the already formed intermediate reactant layer 111 to the titanium silicide 106, and does not grow titanium. No directional growth occurs.

[0012]

Incidentally, in recent semiconductor devices, as the size of the semiconductor device becomes smaller, the gate electrode 1 becomes smaller.
02 and the line width of the source / drain region 103 are becoming narrower. In the current generation semiconductor device, the line width of the gate electrode 102 is 0.6 μm or less, and the line width of the source / drain region 103 is smaller. It is 1 μm or less. On the other hand, the crystal size of C ₅₄ TiSi ₂ is several μm, which is larger than the line width of the gate electrode 102 and the source / drain region 103. In general, in the phase transition phenomenon, the region (in this case, the gate electrode 102 or the source / drain region 103) in which the phase transition occurs due to the crystal size of the substance formed by the phase transition (in this case, C ₅₄ TiSi ₂ ). It is known that the energy required for the phase transition becomes larger as the width becomes smaller. Therefore, FIG.
At the processing temperature in the second heat treatment step shown in (d), the temperature increases as the gate electrode 102 and the source / drain regions 103 become narrower.

However, if the processing temperature of the second heat treatment is excessively increased, the C ₅₄ TiSi ₂ crystal will aggregate, and silicon will re-grow between the aggregated C ₅₄ TiSi ₂ crystal. This causes a new problem that the sheet resistance of the gate electrode 102 and the source / drain region 103 increases.

As a countermeasure against such a problem, conventionally,
The coagulation described above was prevented by shortening the processing time of the second heat treatment at a high temperature (875 ° C.) (about 1 sec). (For example, K. Goto et al. IEICE TRANS ELECTRO
N., vol.E77-C, pp480, 1994).

However, in such a coagulation prevention measure,
4 Ω / sq. To the gate electrode 102 having a width of 0.5 μm. Although the sheet resistance of about 0.4 μm can be achieved, the sheet resistance of 0.4 μm width required for the latest generation is 1
0 Ω / sq. As a result, the sheet resistance could not be sufficiently reduced.

If the thickness of the titanium film 110 is increased in advance, the above-mentioned increase in the sheet resistance can be reduced. However, the titanium silicide 106 grows thickly on the source / drain region 103 and the source / drain region 103
However, this method does not solve the problem because it causes a new disadvantage that the junction leak increases because a large amount of silicon is consumed.

As described above, in the conventional method of manufacturing a semiconductor device, the heat treatment is divided into the first heat treatment at a low temperature and the second heat treatment at a high temperature, thereby preventing a short circuit between the gate electrode 102 and the source / drain region 103. Although it is possible, the sheet resistance of the titanium silicide 106 increases as the line width of the gate electrode 102 and the source / drain region 103 decreases.

[0018]

According to the present invention, a titanium film having a thickness of 35 nm or less is formed on a silicon substrate on which a gate structure and a source / drain region are formed in advance so as to cover the gate structure and the source / drain region. Forming a titanium film; forming a titanium film; and performing a heat treatment on the silicon substrate at a temperature higher than 700 ° C. to cause a thermal reaction between the titanium film and the source / drain region and between the titanium film and the gate electrode. A titanium film removing step of removing a reaction product between the titanium film and the silicon substrate and a reaction product between the titanium film and the gate electrode, and removing other reaction products and an unreacted titanium film, By subjecting the silicon substrate to a heat treatment at 800 ° C. or more, a reaction product between the titanium film and the source / drain region, The reaction product of over gate electrode, and a phase transition step of each phase transition, constitute a method of manufacturing a semiconductor device, to achieve a reduction of the sheet resistance.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a method for forming a film having a thickness of 35 nm or less on a silicon substrate on which a gate structure and a source / drain region have been formed in advance. A titanium film forming step of forming a thick titanium film and heat treatment of the silicon substrate at a temperature higher than 700 ° C.
A drain region, a thermal reaction step of thermally reacting the titanium film and the gate electrode, and a reaction product of the titanium film and the silicon substrate generated by the thermal reaction step, and a reaction product of the titanium film and the gate electrode. A titanium film removing step of removing the remaining reaction products and unreacted titanium film, and subjecting the silicon substrate to a heat treatment at 800 ° C. or more, so that the reaction product between the titanium film and the source / drain regions and titanium A method for manufacturing a semiconductor device is configured to include a phase transition step of phase-transferring a reaction product between the film and the gate electrode, thereby having the following operation.

That is, when a thermal reaction process at a temperature higher than 700 ° C. is applied to a silicon substrate, a C ₄₉ TiSi ₂ crystal and a C ₄₉ TiSi ₂ crystal are formed in a gate structure or a source / drain region having a reduced line width.
It is considered that ₅₄ TiSi ₂ crystals are mixed. Then, in the phase transition step, the C ₅₄ TiSi ₂ crystal already formed in the thermal reaction step serves as a growth nucleus to promote the growth of C ₅₄ TiSi ₂ in the phase transition step, and a gate structure having a narrow line width is obtained. The sheet resistance of the gate electrode and the source / drain regions and the source / drain regions is sufficiently low.

On the other hand, the processing temperature in the thermal reaction
Since the temperature is higher, there is a concern that titanium silicide (mainly C ₄₉ TiSi ₂ ) formed in the thermal reaction process may grow laterally and short-circuit the gate electrode and the source / drain region. Since the thickness is as thin as 35 nm, the lateral growth of titanium silicide is suppressed.

The invention according to claim 2 of the present invention has the following effects by setting the heat treatment time in the thermal reaction step to 30 seconds or less in the invention according to claim 1. That is, since the heat treatment time in the thermal reaction step is set to 30 seconds or less, the lateral growth of titanium silicide is further suppressed.

According to a third aspect of the present invention, in the first or second aspect, the thermal reaction step is performed in an atmosphere containing nitrogen or ammonia. Having. That is, since the thermal reaction step is performed in an atmosphere containing nitrogen or ammonia, the nitridation of silicon constituting the gate electrode and the source / drain regions is promoted, and the lateral growth of titanium silicide is further suppressed. .

[0024] The invention described in claim 4 of the present invention is characterized in that:
Forming a titanium film on the silicon substrate on which the gate structure and the source / drain regions have been formed by covering the gate structure and the source / drain regions with a titanium film; By performing a heat treatment on the silicon substrate, the titanium film and the source / drain regions, and the titanium film and the gate electrode are formed.
A thermal reaction step of performing a thermal reaction, a reaction product of the titanium film and the source / drain region generated by the thermal reaction step, and a reaction product of the titanium film and the gate electrode except for a reaction product, A titanium film removing step of selectively removing an unreacted titanium film and a heat treatment of the silicon substrate to form a reaction product between the titanium film and the source / drain region and a reaction product between the titanium film and the gate electrode. And a phase transition step of performing a phase transition respectively. Thus, a method for manufacturing a semiconductor device is constituted, thereby having the following operation. That is, since the thermal reaction step is performed by performing a heat treatment on the silicon substrate in an atmosphere containing nitrogen or ammonia and in a pressurized state, nitriding of titanium is promoted, and lateral growth of titanium silicide is suppressed. Will be.

According to a fifth aspect of the present invention, there is provided a gate / spacer forming step of forming a gate structure and a spacer on a silicon substrate with the spacer facing upward, and a sidewall covering the side surfaces of the gate structure and the spacer. Forming a source / drain region on a silicon substrate; forming a source / drain region on a silicon substrate; and removing a spacer before and after the source / drain region forming process; A titanium film forming a titanium film thinner than the spacer over the gate structure and the source / drain regions on the silicon substrate having undergone the / drain step and the spacer removing step, and subjecting the silicon substrate to a heat treatment. Titanium film and source / drain region of silicon substrate, and titanium film and gate electrode Each of the thermal reaction step of thermally reacting, the reaction product of the titanium film and the silicon substrate generated by the thermal reaction step, and the reaction product of the titanium film and the gate electrode, leaving the other reaction products, A titanium film removing step of removing the unreacted titanium film and a heat treatment of the silicon substrate to cause a phase transition between a reaction product between the titanium film and the silicon substrate and a reaction product between the titanium film and the gate electrode. The method for manufacturing a semiconductor device is configured to include the steps. This has the following operation. That is, since a titanium film thinner than the spacer is formed, the top surface of the titanium silicide formed by the phase transition step of covering the gate structure and the source / drain regions is formed at the top (top) of the sidewall.
It will be located below. Therefore, the sidewalls serve as barriers to prevent the lateral growth of titanium silicide.

The present invention according to claim 6 of the present invention is directed to claim 5
In the invention according to the first aspect, the thermal reaction step is performed in an atmosphere containing nitrogen or ammonia, thereby having the following operation. That is, since the thermal reaction step is performed in an atmosphere containing nitrogen or ammonia, the nitridation of silicon constituting the gate electrode and the source / drain regions is promoted, and the lateral growth of titanium silicide is further suppressed. .

According to a seventh aspect of the present invention, there is provided a gate forming step of forming a gate structure on a silicon substrate, a sidewall forming step of forming a sidewall covering a side surface of the gate structure, A source / drain forming step for forming a drain region, a gate removing step for selectively removing an upper layer portion of the gate electrode before and after the source / drain forming step, leaving a lower layer portion of the gate electrode; Forming a titanium film thinner than the upper layer of the removed gate electrode on the silicon substrate after the step and the gate removing step, covering the gate structure and the source / drain regions, and subjecting the silicon substrate to heat treatment By doing so, a thermal reaction step of thermally reacting the titanium film with the silicon substrate and the gate electrode, and the thermal reaction step A titanium film removing step of removing a reaction product between the formed titanium film and the silicon substrate and a reaction product between the titanium film and the gate electrode, and removing other reaction products and an unreacted titanium film; and By subjecting the substrate to heat treatment, a method for manufacturing a semiconductor device was configured to include a phase transition step in which a reaction product between the titanium film and the silicon substrate and a reaction product between the titanium film and the gate electrode undergo phase transition. This has the following operation.
That is, since the titanium film thinner than the upper layer portion of the removed gate electrode is formed, the upper surface of the titanium silicide formed by the phase transition step for covering the gate structure and the source / drain regions is formed on the uppermost portion of the sidewall. (The top). for that reason,
The sidewalls act as barriers to prevent lateral growth of titanium silicide.

According to an eighth aspect of the present invention, in the invention according to the seventh aspect, by performing the thermal reaction step in an atmosphere containing nitrogen or ammonia, the following effects are obtained. That is, since the thermal reaction step is performed in an atmosphere containing nitrogen or ammonia, the nitridation of silicon constituting the gate electrode and the source / drain regions is promoted, and the lateral growth of titanium silicide is further suppressed. .

Hereinafter, the present invention will be described with reference to an embodiment in which the present invention is applied to a method of manufacturing a MOS type semiconductor device.

First Embodiment First, the configuration of a MOS semiconductor device manufactured by the manufacturing method of the present embodiment will be described. This MOS type semiconductor device 1
Has a silicon substrate 4 on which a field oxide film 3 is formed with an active region 2 interposed therebetween. A gate structure 5 is provided on the central surface of the active region 2. Gate structure 5
A gate oxide film 6 provided in contact with the active region 2;
And a gate electrode 7 provided on the gate oxide film 6. Each of the active regions 2 on both sides of the gate structure 5 is a source / drain region 8. A titanium silicide 9 made of C ₅₄ TiSi ₂ is formed on the gate electrode 6 and the source / drain region 8, respectively. Further, the gate structure 5 and the titanium silicide 9 formed thereon are formed. Side wall 10 covering the side
Is provided.

Next, a manufacturing process which is a feature of the present embodiment will be described with reference to FIG.

First, as shown in FIG. 2A, a field oxide film 3 surrounding the active region 2 is formed on a silicon substrate 4, and a silicon oxide film 6 'serving as a gate oxide film 6 is formed on the active region 2. After the formation, a polycrystalline silicon film 7 ′ serving as a gate electrode 7 is deposited on the entire surface of the silicon substrate 4.

Next, as shown in FIG. 2B, the polycrystalline silicon film 7 'and the silicon oxide film 6' are patterned by photolithography and etching to form a gate oxide film 6 and a gate electrode 7 '. Gate structure 5 consisting of
To form After that, an insulating film (for example, a silicon oxide film) is deposited on the entire surface and then etched back,
Insulating sidewalls 1 covering both sides of gate structure 5
0 is formed.

Next, as shown in FIG. 2C, the source / drain regions 8 are formed by ion-implanting impurities into the silicon substrate 4 and activating them by heat treatment.

Next, as shown in FIG. 2D, a titanium film 9 'is deposited on the entire surface of the silicon substrate 4 to a thickness of 35 nm or less by a sputtering method.

Next, as shown in FIG. 2E, a first heat treatment as a thermal reaction step is performed on the silicon substrate 4 by a lamp annealing method. The conditions for the first heat treatment are as follows.

The atmosphere is a nitrogen atmosphere of 1 atm or lower pressure. The processing temperature is 700 ° C. or higher, about 725 ° C. in this example. The processing time is about 30 seconds. The first heat treatment Allows the gate electrode 7 and the source /
The silicon and titanium selectively react only on the drain region 8 to form an intermediate reactant layer 1 mainly composed of C ₄₉ TiSi _2.
1 is formed. At this time, the surface side of the titanium film 9 reacts with nitrogen in the atmosphere to form the titanium nitride film 12.

Next, as shown in FIG. ₂ (f), H 2 S
Using a mixed solution of O ₄ : H ₂ O _2, the titanium nitride film 12 and the unreacted titanium film 9 ′ are selectively etched and removed.

After the titanium nitride film 12 and the unreacted titanium film 9 'are selectively etched, a second heat treatment as a phase transition step is performed on the silicon substrate 4 by a lamp annealing method. The conditions of the second heat treatment are as follows.

The atmosphere is a nitrogen atmosphere of 1 atm or lower. The processing temperature is 800 ° C. or more, about 875 ° C. in this example. The processing temperature is about 5 seconds. Accordingly, an intermediate reaction layers 11 C ₅₄ Ti
The phase transition is made to titanium silicide 9 made of Si ₂ crystal to obtain MOS type semiconductor device 1 shown in FIG. C ₄₉ TiSi _2, which mainly constitutes the intermediate reactant layer 11, has a relatively high resistance (60 μΩcm), while C ₅₄ TiSi ₂ has a low resistance (10 μΩcm). Therefore, the above 2
In the MOS type semiconductor device 1 having the titanium silicide (C ₅₄ TiSi ₂ ) 9 formed by the second heat treatment (phase change step), the sheet resistance of the source / drain region 8 and the gate electrode 7 is higher than that of the MOS type semiconductor. 10 Ω / sq. The values are as follows. In addition, a similar resistance value can be obtained even when the gate electrode 7 or the source / drain region 8 has a small line width (0.6 μm or less for the gate electrode 7 and 1 μm or less for the source / drain region 8). Hereinafter, the reason will be described.

As described above in the section of the problem to be solved by the invention, as the line width of the gate electrode 7 becomes narrower, the heating temperature of the second heat treatment (phase transition step) rises, and accordingly, , C ₅₄ TiSi ₂ crystals are aggregated and silicon regrows, increasing the resistance of the gate electrode 7 and the source / drain region 8.

On the other hand, in the manufacturing method of the present embodiment,
By setting the temperature of the first heat treatment (thermal reaction step) higher than 700 ° C., the intermediate reactant layer 11 on the gate electrode 7 and the source / drain region 8 after the first heat treatment (thermal reaction step) in, C ₅₄ TiSi ₂ not only C ₄₉ TiSi ₂
Is also formed, and it is considered that crystals of these reactants are mixed. This can be inferred from the following.

That is, the sheet resistance of C ₄₉ TiSi ₂ is 1
6 Ω / sq. And the sheet resistance of C ₅₄ TiSi ₂ is 4Ω.
/ Sq. It is. On the other hand, as a result of measurement by the present inventor, the first heat treatment (thermal reaction) at a heating temperature of 750 ° C. was performed on the gate electrode 7 having a line width of 0.32 μm on which the titanium film 9 ′ was formed. Step), the sheet resistance of the gate electrode 7 becomes 9.5Ω / sq. 16Ω / a
q. And 4Ω / sq. And intermediate values between the two. From this, when the first heat treatment (thermal reaction step) is performed at a high treatment temperature of 700 ° C. or more, the intermediate reactant layer 11 located on the gate electrode 7 having a narrow line width of 0.32 μm has Due to the thermal reaction, 16Ω / sq. C ₄₉ TiSi ₂ having a sheet resistance of 4Ω / sq. C ₅₄ TiSi ₂ with a sheet resistance of 9.5 Ω / sq.
It seems to be an intermediate value.

Thus, C ₅₄ Ti is added to the intermediate reactant layer 11.
Since Si ₂ has been formed, the second heat treatment (phase change step) involves the C ₅₄ Ti existing in the intermediate reactant layer 11.
The growth of C ₅₄ TiSi ₂ is promoted using the crystal of Si ₂ as a growth nucleus. Therefore, the gate electrode 7 and the source /
Even if the heating temperature in the second heat treatment increases as the line width of the drain region 8 becomes narrower, C ₅₄ TiSi ₂ is less likely to aggregate. As a result, the silicon does not re-grow during the growing C ₅₄ TiSi ₂ and the resistance does not increase.

To support the above description, the inventor of the present application examined by experiment the correlation between the change in the heating temperature in the first heat treatment (thermal reaction treatment) and the line width of the gate electrode. The result is shown in FIG. FIG. 3 shows that in the gate electrode formed on n ⁺ polycrystalline silicon, the second heat treatment (phase change step) is fixed at 875 ° C. for 5 seconds, and then the first heat treatment (thermal reaction step) is performed. The graph shows a change in the sheet resistance of the gate electrode when the temperature is changed. The first and second heat treatments are all performed in a nitrogen atmosphere. In the figure, the horizontal axis shows the width of the gate electrode, and the vertical axis shows the sheet resistance. Further, in the figure, a shows that the first heat treatment (thermal reaction step)
° C, data for 30 seconds; b, data for the first heat treatment (thermal reaction step) at 750 ° C, 30 seconds; c, data for the first heat treatment (thermal reaction step). Step) is data at 725 ° C. for 30 seconds, and d indicates that the first heat treatment (thermal reaction step) is 700
C is the data when the temperature was set to 30 ° C. for 30 seconds, and E is the data when the first heat treatment (thermal reaction step) was set to 650 ° C. for 30 seconds.

As is clear from FIG. 3, when the line width of the gate electrode 7 is made as narrow as 0.32 μm, 1
Assuming that the heating temperature of the second heat treatment (thermal reaction step) is 650 ° C., the resistance of the gate electrode 7 is 24 Ω / sq. become,
At 700 ° C., 11 Ω / sq. In this,
The resistance of the gate electrode 7 is set to 10 Ω / sq., Which is the sheet resistance necessary for increasing the speed of the MOS semiconductor device. It turns out that it does not become the following values.

On the other hand, when the line width of the gate electrode 7 is made as narrow as 0.32 μm, the heating temperature of the first heat treatment (thermal reaction step) is set to 725 ° C. Has a sheet resistance of 6Ω / sq. become,
Similarly, at 750 ° C., 4.5 Ω / sq. Becomes 800
4 Ω / sq. And 10 Ω / sq., Which is the sheet resistance necessary for increasing the speed of the MOS semiconductor device. It can be seen that the following low resistance is sufficiently achieved.

Further, the inventor of the present application examined the relationship between the processing time of the first heat treatment (thermal reaction step) and the short circuit of the gate electrode 7 and the source / drain region 8 by experiments.
FIG. 4 shows the results. FIG. 4 shows a pair of gate electrodes (L / L) formed on a silicon substrate at an interval of 0.4 μm.
(S pattern), the leakage current between the gate electrodes was measured by measuring the leakage current between the gate electrodes at 25 points on the surface of the silicon substrate. The heating temperature of the first heat treatment,
The vertical axis shows the leak current value. Note that the length of the gate electrode is 2 mm.

As is apparent from FIG. 4, the leakage current does not increase regardless of the heating temperature of the first heat treatment. In the MOS type semiconductor device manufactured by this manufacturing method, the gate electrode 7 and the source / source voltage are not changed. It can be seen that there is no fear that the drain region 8 is short-circuited. This is based on the following reasons. That is, by setting the thickness of the titanium film 9 ′ to 35 nm or less and setting the processing time of the first heat treatment to 30 seconds or less, TiSi ₂ (in this case, C
It is considered that the lateral growth of ₄₉ TiSi ₂ and C ₅₄ TiSi ₂ ) was suppressed. The lateral growth of TiSi ₂ can be sufficiently suppressed only by setting the thickness of the titanium film 9 ′ to 35 nm or less.

In this embodiment, the first heat treatment
Although nitrogen was used as the atmosphere for the second heat treatment, ammonia which has a strong nitriding property and can suppress lateral growth may be used.

In the present embodiment, in the step shown in FIG. 2B, impurity ions are implanted at a low concentration, and a low concentration source / drain region is formed under the sidewall 10 to form an LDD structure. Needless to say, the same effect can be obtained.

In this embodiment, the sidewalls 10 are formed of a silicon oxide film, but a silicon nitride film or the like may be used.

Further, in this embodiment, in the step shown in FIG. 2F, the titanium nitride film 12 and the unreacted titanium film 9 'are selected by using a mixed solution of H ₂ SO ₄ : H ₂ O _2. However, the titanium nitride film 12 and the unreacted titanium film 9 ′ may be selectively etched using a mixed solution of NH ₄ OH: H ₂ O ₂ : H ₂ O.

Second Embodiment The structure of a MOS type semiconductor device manufactured in this embodiment is the same as that described in the first embodiment, and the same or similar parts have the same reference characters. , And detailed description thereof will be omitted.

Next, a manufacturing process which is a feature of this embodiment will be described with reference to FIG.

After a gate structure 5 including a gate oxide film 6 and a gate electrode 7, source / drain regions 8, and sidewalls 10 are formed on a silicon substrate 4, a titanium film 9 is formed on the silicon substrate 4. 'Deposit.
These steps are the same as the steps shown in FIGS. 2A to 2D, and thus description thereof will be omitted.

Next, as shown in FIG. 5A, a first heat treatment (thermal reaction step) is performed on the silicon substrate 4 by a lamp annealing method. The conditions for the first heat treatment are as follows.

The atmosphere is a nitrogen atmosphere in a pressurized state (preferably 6 atm or more). The processing temperature is 700 ° C. or more, about 725 ° C. in this example. The processing time is about 30 seconds. By the first heat treatment, silicon and titanium are reacted only on the gate electrode 7 and the source / drain region 8,
An intermediate reactant layer 15 mainly composed of C ₄₉ TiSi ₂ crystals is formed.

Next, as shown in FIG. 5B, H ₂ SO ₄ :
Using a mixed solution of H ₂ O ₂ , unreacted Ti
Is removed.

After the titanium nitride film 12 and the unreacted titanium film 9 ′ are selectively etched, a second heat treatment as a phase transition step is performed on the silicon substrate 4 by a lamp annealing method. The conditions of the second heat treatment are as follows.

The atmosphere is a nitrogen atmosphere of 1 atm or lower. The processing temperature is 800 ° C. or more, about 875 ° C. in this example. The processing temperature is about 5 seconds. The phase of the reactant layer 15 is changed to titanium silicide 16 made of C ₅₄ TiSi ₂ crystal to form a MOS.
Semiconductor device.

In this embodiment, in a pressurized state, preferably in a nitrogen atmosphere of 6 atm or more, the silicon substrate 4
Has been subjected to the first heat treatment, and thus the TiSi
₂ can suppress the lateral growth. This means
Japan Society of Applied Physics Spring 1990, Lecture No. 29a-ZA
4 (formed of TiN film by the high-pressure NH ₃ nitride Ti: Valley,
And others). That is, in this document, a heating temperature of 700 ° C.,
When the heat treatment is performed for a treatment time of 300 seconds, when the atmospheric pressure is 6 kg / cm ² (about 6 atm), titanium becomes titanium nitride (TiN). When it becomes difficult to become titanium nitride (TiN) and approaches a state of no pressure, all of titanium grows as titanium silicide (TiSi ₂ ), and titanium nitride (TiN) grows.
N).

The other operation and effect of the present embodiment are the same as those of the first embodiment, and the description thereof will be omitted.

In this embodiment, nitrogen is used as the atmosphere for the first heat treatment (thermal reaction step) and the second heat treatment (phase transition step). However, the nitridation is strong and the lateral growth is suppressed. Ammonia that can be used.

In this embodiment, the same effect can be obtained even in an LDD structure in which impurity ions are implanted at a low concentration and a low concentration source / drain region is formed below the sidewalls 10.

In this embodiment, the side wall 1
Although 0 is formed of a silicon oxide film, a silicon nitride film or the like may be used.

Further, in this embodiment, the second heat treatment is performed in an atmosphere of 1 atm or lower pressure, but may be performed in a pressurized state as in the first heat treatment. .

Third Embodiment First, the configuration of a MOS type semiconductor device manufactured by the manufacturing method of this embodiment will be described. This MOS type semiconductor device 2
0, as shown in FIG. 6, field oxide film 3, gate structure 5 (including gate oxide film 6 and gate electrode 21),
It has a source / drain region 8 and a side wall 22, and these structures are basically the same as those of the MOS type semiconductor device 1 described in the first embodiment. This MOS type semiconductor device 20 is characterized by the configuration of titanium silicide 23 formed on gate electrode 21 and source / drain region 8. That is, the thickness of the titanium silicide 23 is smaller than the separation distance between the surface of the gate electrode 21 and the upper end of the sidewall 22, and the top (top) of the sidewall 22 is located above the gate electrode 21. It protrudes.

Next, a method of manufacturing the MOS type semiconductor device 20 will be described with reference to FIGS. 7 (a) to 7 (f).

First, as shown in FIG. 7A, a field oxide film 3 surrounding an active region 2 is formed on a silicon substrate 4, and a thickness to become a gate oxide film 6 on the active region 2 is about 8 nm. Is formed. Further, a polycrystalline silicon film 21 'having a thickness of 200 nm and a spacer film 24' made of silicon nitride having a thickness of 50 nm are formed on the entire surface of the silicon substrate 4.

Next, as shown in FIG. 7B, the spacer film 2 is formed by photolithography and etching.
4 ′, the polycrystalline silicon film 21 ′ and the silicon oxide film 6 ′ are patterned to form the gate structure 5 including the gate oxide film 6 and the gate electrode 21 and the spacer 24. Thereafter, an insulating film, for example, a silicon oxide film is deposited on the entire surface of the silicon substrate 4 and is etched back to form an insulating sidewall 22 covering the side surfaces of the gate structure 5 and the spacer 24.

Next, as shown in FIG.
Wet etching is performed using an H ₃ PO ₄ solution heated to a certain degree to selectively remove the spacers 24 made of silicon nitride. Further, the source / drain regions 8 are formed by ion-implanting impurities into the silicon substrate 4 and activating them by heat treatment.

Next, as shown in FIG. 7D, after the natural oxide film formed on the silicon substrate 4 is etched with an HF solution, a titanium film 23 'is deposited on the silicon substrate 4 by a sputtering method. At this time, it is a feature of the manufacturing method that the thickness of the titanium film 23 ′ is smaller than the thickness of the removed spacer 24. Specifically, when the thickness of the spacer 24 is 50 nm, the titanium film 23 ′
Has a thickness of 40 nm or less.

Next, as shown in FIG. 7E, a first heat treatment is performed by a lamp annealing method. The conditions for the first heat treatment are as follows.

The atmosphere is a nitrogen atmosphere of 1 atm or lower. The processing temperature is 700 ° C. or more, about 725 ° C. in this example. The processing time is about 30 seconds. Allows the gate electrode 7 and the source /
Intermediate reactant layer 2 and the silicon and titanium only on the drain region 8 is made of a C ₄₉ TiSi ₂ mainly reacts selectively
5 are formed. At this time, the surface side of the titanium film 23 'reacts with nitrogen in the atmosphere to form the titanium nitride film 26.

Next, as shown in FIG. 7F, H ₂ S
Using a mixed solution of O ₄ : H ₂ O _2, the titanium nitride film 26 and the unreacted titanium film 23 ′ are selectively etched and removed.

After the titanium nitride film 26 and the unreacted titanium film 23 ′ are selectively etched, a second heat treatment as a phase transition step is performed on the silicon substrate 4 by a lamp annealing method. The conditions of the second heat treatment are as follows.

The atmosphere is a nitrogen atmosphere of 1 atm or lower pressure. The processing temperature is 800 ° C. or more, about 875 ° C. in this example. The processing temperature is about 5 seconds. (Phase transition step), mainly C ₄₉ Ti
Intermediate reactant layer 25 made of Si ₂ (resistance: 60 μΩcm)
Is transformed into titanium silicide 23 made of C ₅₄ TiSi ₂ (resistance: 16 μΩcm) crystal. This allows
The sheet resistance of the source / drain region 8 and the gate electrode 7 is set to a sheet resistance of 10Ω / sq. It can be:

In this manufacturing method, the titanium silicide 23
Is located below the top of the sidewall 22 even if the first heat treatment (thermal reaction step) is performed in a high temperature range of 700 ° C. or more, mainly C ₄₉ TiSi.
_The lateral growth of the intermediate reactant layer 25 made of ₂ is hindered by the sidewalls 22 rising to the side, and there is no fear of short-circuiting due to lateral growth.

In this embodiment, the first heat treatment
Although nitrogen was used as the atmosphere for the second heat treatment, ammonia which has a strong nitriding property and can suppress lateral growth may be used.

Further, in this embodiment, in the step shown in FIG. 7C, impurity ions are implanted at a low concentration to form a low concentration source / drain region under the side wall 22 so as to form an LDD. Needless to say, the same effect is obtained even when the structure is used.

In this embodiment, the sidewalls 22 are formed of a silicon oxide film, but a silicon nitride film or the like may be used.

In this embodiment, the etching solution used for removing the spacer 24 shown in FIG.
Any combination may be used as long as there is a liquid capable of etching only the spacer 24. For example, when the spacer 24 made of TiN is formed, the etching solution is H
₂ SO _4: a H ₂ O mixed solution of ₂ suitable, in the case of forming the spacer 24 made of Mo, the etchant HNO
A mixed solution of ₃ : H ₂ SO ₄ : H ₂ O = 1: 1: 3 is suitable.

Further, in the present embodiment, the spacer 2
Although the source / drain regions 8 are formed by implanting impurities into the silicon substrate 4 after removing the silicon substrate 4, the spacers 24 may be removed after forming the source / drain regions 8. By doing so, the spacer 24 serves as a cover when implanting impurities, so that the influence of the impurity implantation on the gate electrode 21 can be prevented.

Fourth Embodiment The structure of a MOS type semiconductor device manufactured in this embodiment is the same as that described in the third embodiment.
Identical or similar parts are denoted by the same reference numerals, and detailed description thereof will be omitted.

Next, a manufacturing process which is a feature of this embodiment will be described with reference to FIG.

First, as shown in FIG. 8A, a field oxide film 3 surrounding the active region 2 is formed on a silicon substrate 4. Further, a silicon oxide film 6 'having a thickness of about 8 nm serving as a gate oxide film is formed on the active region 2,
A polycrystalline silicon film 30 ′ having a thickness of 250 nm is deposited on the entire surface of the silicon substrate 4.

Next, as shown in FIG. 8B, an undeleted gate electrode 30 is formed by patterning the polycrystalline silicon film 30 ′ by using photolithography and etching. At this time, the silicon oxide film 6 'is not etched. After that, an insulating film made of, for example, silicon nitride is deposited on the entire surface of the silicon substrate 4 and is etched back to form insulating sidewalls 22 on both side surfaces of the undeleted gate electrode 30. At this time, the etching is stopped so that the silicon oxide film 6 'remains. In forming the undeleted gate electrode 30,
It is relatively easy to etch only the polycrystalline silicon film 30 'and the side wall (silicon nitride) 22 and leave the silicon oxide film 6'. this is,
This is because the silicon oxide film 6 ′ is different from the polycrystalline silicon film 30 ′ and silicon nitride in film type, so that selective etching can be easily performed by dry etching.

Next, as shown in FIG.
(Tetramethylammonium hydroxide) / I
The silicon substrate 4 is wet-etched using a mixed solution of PA (isopropyl alcohol), the undeleted gate electrode 30 is etched by 50 nm, and the gate electrode portion remaining after the etching is used as the gate electrode 21. In addition,
TMAH / IPA is undeleted gate electrode (polysilicon)
30 is selectively etched, and the side wall (silicon nitride) 22 and the silicon oxide film 6 'are not etched, which is suitable for such etching.

Thereafter, as shown in FIG. 8D, the silicon oxide film 6 'exposed on the surface of the silicon substrate 4 is removed by etching, leaving the silicon oxide film 6' only under the gate electrode 21. The remaining silicon oxide film 6 ′ is used as the gate oxide film 6.

After the gate oxide film 6 is formed, impurities are ion-implanted into the silicon substrate 4 and activated by heat treatment to form the source / drain regions 8.

The steps after the formation of the source / drain regions 8 are the same as those of the fourth embodiment shown in FIGS.
And the description thereof is omitted.

In this embodiment, as in the fourth embodiment, the uppermost part of the formed titanium silicide 23 is located below the top of the sidewall 22, and the high temperature region of 700.degree. Even if the first heat treatment (thermal reaction step) is performed, the lateral growth of the intermediate reactant layer 25 mainly composed of C ₄₉ TiSi ₂ is hindered by the sidewalls 22 rising to the side, and There is no need to worry about a short circuit caused by this.

In the present embodiment, nitrogen was used as the atmosphere in the first heat treatment (thermal reaction step) and the second heat treatment (phase transition step), but the nitridation was strong and the lateral growth was suppressed. Ammonia that can be used.

In the present embodiment, the sidewall 22 is formed of silicon nitride, but a silicon oxide film or the like may be used.

In this embodiment, a mixed solution of TMAH / IPA is used as an etching solution for etching the undeleted gate electrode (polycrystalline silicon) 30. However, the silicon oxide film 6 'and the side wall (silicon nitride) are etched. Any liquid may be used as long as there is a liquid capable of etching only the undeleted gate electrode 30 without etching the gate electrode 30. Specifically, ethylenediamine / pyrocatechol /
A mixed solution of water, an aqueous solution of KOH, an aqueous solution of NaOH, etc.
The etching solution can be used.

In a MOS type semiconductor device or the like, after a titanium silicide 9 is formed on the gate electrode 7 and the source / drain region 8, a low-resistance aluminum layer (3 Ωcm) is formed on the titanium silicide 9. Depositing a tungsten layer (9.5 Ωcm) has been performed. In such a structure, MOS-type semiconductor devices manufactured by the manufacturing methods of the third and fourth embodiments are convenient. That is, the film thickness of the gate electrode 21 and the titanium silicide 23 is adjusted to be thinner,
Is set to be larger than the thickness of the aluminum layer or the tungsten layer deposited on the titanium silicide 23. that way,
The sidewall 22 rises between the aluminum layer or tungsten layer on the gate electrode 7 side and the aluminum layer or tungsten layer on the source / drain region 8 side, and the growth of aluminum or tungsten is stopped by the sidewall 22. . As a result, the disadvantage that the gate electrode 7 and the source / drain region 8 are short-circuited by the lateral growth or non-selective growth of aluminum or tungsten does not occur.

[0098]

【The invention's effect】 Effect of Claim 1 Applying a thermal reaction process above 700 ° C to the silicon substrate
And gate electrode and source / drain with reduced line width
Region, the gate electrode and the source / drain region
The sheet resistance could be made sufficiently low.

Since the thickness of the titanium film is as thin as 35 nm, the lateral growth of titanium silicide is suppressed, and the gate electrode and the source / drain region caused by the lateral growth of titanium silicide are suppressed. Is also less likely to occur.

Since the heat treatment time in the thermal reaction step of claim 2 is set within 30 seconds, the lateral growth of titanium silicide is further suppressed, and a short circuit between the gate electrode and the source / drain region further occurs. It becomes difficult.

[0102] The nitride of silicon constituting the effective gate electrode and the source / drain region of claim 3 is promoted, the lateral growth of the titanium silicide is further suppressed, a short circuit between the gate electrode and the source / drain region Are more unlikely to occur.

Since the thermal reaction step of claim 4 is performed by subjecting the silicon substrate to a heat treatment in an atmosphere containing nitrogen or ammonia and under a pressurized state, the nitridation of titanium is promoted and the side of titanium silicide is promoted. Directional growth was suppressed. Thereby, a short circuit between the gate electrode and the source / drain region due to the lateral growth of titanium silicide is less likely to occur.

The side wall acts as a barrier to prevent the lateral growth of titanium silicide, and thereby, between the gate electrode and the source / drain region caused by the lateral growth of titanium silicide. Short circuits are less likely to occur.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a MOS type semiconductor device manufactured by a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A to 2C are cross-sectional views illustrating respective steps of a method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a relationship between a wiring width of a polycrystalline polysilicon gate manufactured by a first manufacturing method and its sheet resistance.

FIG. 4 is a diagram showing the relationship between the temperature of the first heat treatment (thermal reaction step) and the leak current in the first manufacturing method.

FIGS. 5A to 5C are cross-sectional views illustrating respective manufacturing steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention; FIGS.

FIG. 6 is a sectional view showing a structure of a MOS type semiconductor device manufactured by a method of manufacturing a semiconductor device according to the third and fourth embodiments of the present invention.

FIGS. 7A and 7B are cross-sectional views illustrating respective steps of a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a cross-sectional view showing each of the manufacturing steps of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 9 is a cross-sectional view for explaining a problem of a conventional MOS type semiconductor device.

FIG. 10 is a cross-sectional view showing each of the manufacturing steps of a conventional method for manufacturing a MOS type semiconductor device.

[Explanation of symbols]

Reference Signs List 4 silicon substrate 5 gate structure 6 gate oxide film 7 gate electrode 8 source / drain region 9 titanium silicide 9 'titanium film 10 sidewall 11 intermediate reactant layer 12 titanium nitride film

Claims (8)

[Claims] 1. A titanium film forming step of forming a titanium film having a thickness of 35 nm or less on a silicon substrate on which a gate structure and source / drain regions have been previously formed, covering the gate structure and source / drain regions; A thermal reaction step of thermally reacting the titanium film with the source / drain regions, and the titanium film with the gate electrode by subjecting the silicon substrate to a heat treatment at a temperature higher than 0 ° C .; and a titanium film and silicon produced by the thermal reaction step A titanium film removing step of removing a reaction product with the substrate and a reaction product between the titanium film and the gate electrode and removing other reaction products and an unreacted titanium film, and a heat treatment at 800 ° C. or more on the silicon substrate. By performing the reaction, a reaction product between the titanium film and the source / drain region and a reaction product between the titanium film and the gate electrode are removed. A method for producing a semiconductor device, the method comprising: 2. The heat treatment time in the thermal reaction step is 3
2. The method according to claim 1, wherein the time is within 0 seconds. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the thermal reaction step is performed in an atmosphere containing nitrogen or ammonia. 4. A titanium film forming step of forming a titanium film covering a gate structure and a source / drain region on a silicon substrate on which a gate structure and a source / drain region have been formed in advance, comprising: A thermal reaction step of thermally reacting the titanium film and the source / drain regions, and the titanium film and the gate electrode, respectively, by subjecting the silicon substrate to heat treatment in an atmosphere in a pressure state; A titanium film removing step of selectively removing a reaction product between the film and the source / drain region and a reaction product between the titanium film and the gate electrode, and selectively removing other reaction products and an unreacted titanium film; By subjecting the substrate to heat treatment, a reaction product between the titanium film and the source / drain region and a reaction product between the titanium film and the gate electrode are formed. A phase transition step of phase-transferring the reaction products. 5. A gate / spacer forming step of forming a gate structure and a spacer on a silicon substrate in a stacked manner with the spacer facing upward; a side wall forming step of forming a sidewall covering a side surface of the gate structure and the spacer; A source / drain forming step of forming source / drain regions in the silicon substrate; a spacer removing step of selectively removing spacers before and after the source / drain forming step; a source / drain forming step and a spacer removing step A titanium film forming step of forming a titanium film thinner than the spacer on the silicon substrate so as to cover the gate structure and the source / drain regions; and performing a heat treatment on the silicon substrate to form the titanium film and the source / drain regions; A thermal reaction step of thermally reacting the titanium film and the gate electrode, respectively, Titanium that removes the reaction product between the titanium film and the source / drain regions and the reaction product between the titanium film and the gate electrode, and removes other reaction products and unreacted titanium film, which are generated by the thermal reaction process. A film removing step, and a phase transition step of subjecting the silicon substrate to a heat treatment to cause a phase transition between a reaction product between the titanium film and the silicon substrate and a reaction product between the titanium film and the gate electrode. Semiconductor device manufacturing method. 6. The method for manufacturing a semiconductor device according to claim 5, wherein said thermal reaction step is performed in an atmosphere containing nitrogen or ammonia. 7. A gate forming step for forming a gate structure on a silicon substrate, a sidewall forming step for forming a sidewall covering a side surface of the gate structure, and a source / drain forming for forming a source / drain region in the silicon substrate. A silicon substrate having passed through a source / drain forming step, a gate removing step of selectively removing an upper layer portion of the gate electrode while leaving a lower layer portion of the gate electrode before and after the source / drain forming step; Forming a titanium film thinner than the upper layer portion of the removed gate electrode so as to cover the gate structure and the source / drain regions; and subjecting the silicon film to heat treatment by subjecting the titanium film to source / drain A thermal reaction step of thermally reacting the region and the gate electrode, and a titanium film generated by the thermal reaction step A titanium film removing step of removing a reaction product between the silicon film and the source / drain region and a reaction product between the titanium film and the gate electrode and removing other reaction products and an unreacted titanium film; A phase transition step of performing a phase transition of a reaction product between the titanium film and the source / drain region and a reaction product between the titanium film and the gate electrode. 8. The method according to claim 7, wherein the thermal reaction step is performed in an atmosphere containing nitrogen or ammonia.