JPH1051079A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1051079A JPH1051079A JP9133726A JP13372697A JPH1051079A JP H1051079 A JPH1051079 A JP H1051079A JP 9133726 A JP9133726 A JP 9133726A JP 13372697 A JP13372697 A JP 13372697A JP H1051079 A JPH1051079 A JP H1051079A
- Authority
- JP
- Japan
- Prior art keywords
- quantum well
- mask
- well structure
- semiconductor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 230000004888 barrier function Effects 0.000 claims abstract description 25
- 238000001947 vapour-phase growth Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 37
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000002356 single layer Substances 0.000 claims description 2
- 239000002994 raw material Substances 0.000 abstract description 10
- 239000007789 gas Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Landscapes
- Light Receiving Elements (AREA)
- Semiconductor Lasers (AREA)
Abstract
(57)【要約】
【課題】 単一の基板上に井戸幅が異なる複数の量子井
戸構造、あるいは井戸幅が部分的に異なる量子井戸構造
を有する量子井戸構造の半導体素子を提供する。
【解決手段】 ＩｎＰからなる基板１は表面に沿った所
定の方向に９つの領域に分割されている。これらの領域
には、両端に隣接する領域から１つおきにＳｉＮxのマ
スク２が形成されている。マスク２が形成されていない
基板１の表面上には、ＩｎＰからなる障壁層３とＧａＩ
ｎＡｓの井戸層４が気相成長により交互に積層されて、
量子井戸構造を形成している。気相成長時にマスク上に
供給された原料がマスクのない部分に移動することによ
り、マスク近傍の層の成長速度が増加して、位置により
井戸幅の異なる複数の特性の量子井戸構造を有する半導
体素子が得られる。
(57) [Problem] To provide a semiconductor device having a plurality of quantum well structures having different well widths on a single substrate or a quantum well structure having a quantum well structure having partially different well widths. A substrate 1 made of InP is divided into nine regions in a predetermined direction along a surface. In these regions, masks 2 of SiN x are formed every other region adjacent to both ends. On the surface of the substrate 1 where the mask 2 is not formed, a barrier layer 3 made of InP and a GaI
Well layers 4 of nAs are alternately stacked by vapor phase growth,
A quantum well structure is formed. A semiconductor having a quantum well structure having a plurality of characteristics with different well widths depending on the position by increasing the growth rate of the layer near the mask by moving the raw material supplied on the mask during the vapor phase growth to a portion without the mask. An element is obtained.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、一層もしくは多層
の量子井戸構造を有する半導体素子を基板上に有する半
導体装置に関する。[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a semiconductor element having a single or multilayer quantum well structure on a substrate.
【０００２】[0002]
【従来の技術】井戸幅の異なる量子井戸構造をレーザダ
イオードに用いると、発振波長の異なるレーザ装置を実
現できる。また、井戸幅の異なる量子井戸構造を受光素
子に用いると、受光感度の波長依存性が異なる受光装置
を実現できる。さらに、部分的に井戸幅が異なる量子井
戸構造を利用すれば、光導波路なども容易に実現でき
る。2. Description of the Related Art When quantum well structures having different well widths are used for laser diodes, laser devices having different oscillation wavelengths can be realized. Further, when quantum well structures having different well widths are used for light receiving elements, a light receiving device having different wavelength dependence of light receiving sensitivity can be realized. Furthermore, if a quantum well structure having a partially different well width is used, an optical waveguide or the like can be easily realized.
【０００３】[0003]
【発明が解決しようとする課題】従来、単一の基板上に
井戸幅の異なる複数の量子井戸構造を実現するために
は、一度の気相成長工程では単一の井戸幅のものしか得
られないため、二度の気相成長をしなければならなかっ
た。また、同一の量子構造において、井戸幅を部分的に
異ならせることは、容易ではなかった。Conventionally, in order to realize a plurality of quantum well structures having different well widths on a single substrate, only a single well width can be obtained in a single vapor growth step. Because of this, it was necessary to carry out vapor phase growth twice. Further, it is not easy to partially change the well width in the same quantum structure.
【０００４】このため、量子井戸構造からなる単一基板
上の各素子は特性が安定せず、高コストになりがちであ
った。For this reason, the characteristics of each element on a single substrate having a quantum well structure are not stable, and the cost tends to be high.
【０００５】そこで、本発明は、このような課題を解決
した半導体装置を提供することを課題とする。Accordingly, an object of the present invention is to provide a semiconductor device which solves such a problem.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置は、
同一基板上に空間的に異なる量子井戸構造を有する半導
体素子を形成した半導体装置において、一つあるいは複
数の半導体素子形成領域と、これに隣接する周辺領域と
を有する基板と、半導体素子領域の表面上に、障壁層と
井戸層をその井戸幅あるいは障壁幅に応じた被覆率ある
いは形状で該半導体素子領域に隣接する周辺領域に形成
された結晶成長を阻止するためのマスクを用いた気相成
長により交互に積層させて形成した一層または多層の量
子井戸構造からなる一つあるいは複数の半導体素子と、
を備え、半導体素子の少なくとも１つは、空間的に変化
する量子井戸構造あるいは他の半導体素子と異なる量子
井戸構造を有していることを特徴とする。According to the present invention, there is provided a semiconductor device comprising:
In a semiconductor device in which a semiconductor element having a spatially different quantum well structure is formed on the same substrate, a substrate having one or a plurality of semiconductor element formation regions and a peripheral region adjacent thereto is provided. Vapor growth using a mask for preventing crystal growth formed in a peripheral region adjacent to the semiconductor element region with a barrier layer and a well layer having a coverage or a shape corresponding to the well width or the barrier width. One or more semiconductor elements having a single-layer or multi-layer quantum well structure formed by alternately stacking
And at least one of the semiconductor elements has a spatially varying quantum well structure or a quantum well structure different from other semiconductor elements.
【０００７】これによれば、気相成長により、マスク近
傍の基板表面では障壁幅及び井戸幅が広く形成され、マ
スクから離れた基板表面では障壁幅及び井戸幅は狭く形
成される。また、マスクによる基板表面の被覆率が大き
い部分では障壁幅及び井戸幅が広く形成され、被覆率が
小さい部分では狭く形成される。したがって、マスクの
被覆率及び形状を制御することにより、障壁層及び井戸
層の幅が制御され、複数の量子井戸特性を有する量子井
戸構造が得られる。According to this, the barrier width and the well width are formed wide on the substrate surface near the mask, and the barrier width and the well width are formed narrow on the substrate surface away from the mask by the vapor phase growth. Further, the barrier width and the well width are formed wide in the portion where the coverage of the substrate surface by the mask is large, and narrow in the portion where the coverage is small. Therefore, by controlling the mask coverage and the shape, the widths of the barrier layer and the well layer are controlled, and a quantum well structure having a plurality of quantum well characteristics can be obtained.
【０００８】[0008]
【発明の実施の形態】以下、添付図面を参照して本発明
の実施形態を説明する。Embodiments of the present invention will be described below with reference to the accompanying drawings.
【０００９】図１は、本発明の一実施形態を示してお
り、同図（ａ）が平面図、同図（ｂ）がＣ−Ｃ線断面図
である。FIG. 1 shows an embodiment of the present invention. FIG. 1A is a plan view, and FIG. 1B is a sectional view taken along line CC.
【００１０】同図（ａ）に示されるようにこの半導体素
子は、ＩｎＰからなる基板１の表面をＣ−Ｃ線に沿った
方向に９つの領域に分割して図中左側から数えて偶数番
目の領域の基板１表面を被覆してＳｉＮxのマスク２1〜
２4が形成されている。マスク２1、２2は領域Ｓ３の両
側を３０μｍの幅で覆い、マスク２3、２4は領域Ｓ４の
両側を１０μｍの幅で覆っている。そして、基板１表面
上のマスク２1〜２4が形成されていない領域には、Ｉｎ
Ｐからなる障壁層３とＧａＩｎＡｓからなる井戸層４が
気相成長により交互に４層積層されて、量子井戸構造を
形成している。この量子井戸構造の井戸幅は、領域Ｓ３
で約１５ｎｍ、領域Ｓ４で約５ｎｍである。また、他の
領域では、マスク近傍で井戸幅が極大値をとり、マスク
から離れた部分で井戸幅が極小値をとるよう連続的に変
化している（同図（ｂ）参照）。As shown in FIG. 1A, this semiconductor device is divided into nine regions along the line CC along the surface of the substrate 1 made of InP, and the even-numbered regions are counted from the left side in the figure. coating the surface of the substrate 1 of the area mask 2 1 of SiN x and ~
24 are formed. Mask 2 1, 2 2 covers both sides of the-area S3 in the width of 30 [mu] m, the mask 2 3, 2 4 covers both sides of the area S4 in the width of 10 [mu] m. Then, in a region where the mask 21 to 24 on the substrate 1 surface is not formed, In
Four barrier layers 3 made of P and well layers 4 made of GaInAs are alternately stacked by vapor phase growth to form a quantum well structure. The well width of this quantum well structure is in the region S3
Is about 15 nm, and the area S4 is about 5 nm. In other regions, the well width has a local maximum value in the vicinity of the mask, and continuously changes so that the well width has a local minimum value in a portion away from the mask (see FIG. 3B).
【００１１】このような半導体素子は、量子井戸構造を
レーザダイオード、受光素子、光導波路などに利用する
ことができる。In such a semiconductor device, a quantum well structure can be used for a laser diode, a light receiving device, an optical waveguide, or the like.
【００１２】次に、図２を参照して本発明の実施形態の
製造工程を説明する。説明を簡単にするため、半導体素
子のうちマスクと量子井戸構造を有する領域の１領域ず
つを含む領域部分を例示して説明する。領域が複数存在
する場合も工程は同一である。図２は本発明の半導体素
子を製造する基本工程を示す素子断面図である。Next, the manufacturing process of the embodiment of the present invention will be described with reference to FIG. For simplicity of description, a description will be given by exemplifying a region portion including one region of a mask and one region having a quantum well structure in a semiconductor element. The process is the same when a plurality of regions exist. FIG. 2 is an element cross-sectional view showing a basic step of manufacturing the semiconductor element of the present invention.
【００１３】まず、同図（ａ）に示すように、基板１の
表面の一部をＳｉ3Ｎ4などのマスク２により被覆する。
マスクはＳｉＯ2でもよい。このような部分的な被覆
は、フォトレジストのパターニング等により容易に実現
できる。First, as shown in FIG. 1A, a part of the surface of a substrate 1 is covered with a mask 2 such as Si 3 N 4 .
The mask may be SiO 2. Such partial coating can be easily realized by patterning a photoresist or the like.
【００１４】次に、この基板１を気相成長装置（図示せ
ず）にセットして、原料Ａを含むガスを供給すると、マ
スク２に覆われていない基板１の表面に障壁層３1をな
す半導体が結晶成長される。このとき、マスク上に供給
された原料がマスクがない領域に移動してその領域の原
料濃度が高くなるために、成長速度が増加することが知
られている（「第３４回応用物理学関係連合講演会予稿
集」ｐ．１５０，１９８７、「第３５回応用物理学関係
連合講演会予稿集」ｐ．２７９，１９８８）。原料ガス
はマスク２の直上でよどむ境界層を形成し、この境界層
の中で、原料は原料濃度の高い場所から低い場所へ拡散
により移動している。マスク２の近傍では原料が基板に
吸収されて原料濃度が小さくなっている。これに対し
て、マスクにより覆われている領域では、原料が吸収さ
れることがないため、原料濃度は高くなっている。した
がって、原料はマスクのある領域からマスクのない領域
に向かって、拡散により移動する。これにより、マスク
の近傍の領域では、成長速度が増加する。障壁層３1は
厚く形成されることになる（同図（ｂ）参照）。[0014] Next, the substrate 1 was set in a vapor phase growth apparatus (not shown), when supplying the gas containing the raw material A, the barrier layer 3 1 to the surface of the substrate 1 not covered with the mask 2 The semiconductor to be formed is crystal-grown. At this time, it is known that the growth rate is increased because the raw material supplied on the mask moves to a region where there is no mask and the raw material concentration in that region is increased (see the 34th Applied Physics-related). Proceedings of the Alliance Lectures, p.150, 1987, and the 35th Applied Physics-related Lectures, p.279, 1988). The source gas forms a boundary layer that stagnates immediately above the mask 2, and in this boundary layer, the source material moves by diffusion from a location where the source concentration is high to a location where the source concentration is low. In the vicinity of the mask 2, the raw material is absorbed by the substrate and the raw material concentration is reduced. On the other hand, in the region covered by the mask, the raw material is not absorbed, so that the raw material concentration is high. Therefore, the raw material moves by diffusion from the region with the mask to the region without the mask. As a result, the growth rate increases in the region near the mask. Barrier layer 3 1 will be thicker (see FIG (b)).
【００１５】次に、別の原料Ｂを含むガスを供給する
と、障壁層３1の上にのみ井戸層４1をなす別の半導体が
結晶成長される。この場合、マスク２の近傍で井戸層４
1が厚く形成されるのは、障壁層３1の場合と同様である
（同図（ｃ）参照）。以下、供給するガスを原料Ａ、Ｂ
を含むものに交互に切り替えると、障壁層３2、井戸層
４2および障壁層３3の順に順次形成されていく（同図
（ｄ）参照）。Next, by supplying a gas containing another material B, another semiconductor forming the well layer 4 1 only on the barrier layer 3 1 is grown. In this case, the well layer 4 near the mask 2
The 1 is formed thick, the same as in the case of the barrier layer 3 1 (see FIG. (C)). Hereinafter, the supplied gases are referred to as raw materials A and B.
Switching to alternate those containing, barrier layer 3 2, are sequentially formed in this order of the well layer 4 2 and the barrier layer 3 3 (see FIG. (D)).
【００１６】上記の工程において、障壁層３1〜３3の半
導体のバンドギャップが、井戸層４1〜４2の半導体のバ
ンドギャップより大きくなるようにしておけば、部分的
に井戸幅が異なる量子井戸構造を一度の気相成長工程で
実現できる。また、例えば同図（ｄ）に示される領域Ｓ
１、Ｓ２以外の部分の障壁層３1〜３3及び井戸層４1〜
４2をエッチングで除去すれば、互いに井戸幅の異なる
２つの量子井戸構造を有する半導体素子が得られる。In the above steps, the semiconductor bandgap of the barrier layer 3 1 to 3 3, if set to be larger than the band gap of the well layer 41 to the second semiconductor, partially well width is different The quantum well structure can be realized by one vapor phase growth process. Further, for example, an area S shown in FIG.
1, the barrier layer in the portion other than the S2 3 1 to 3 3 and the well layer 4 1
By removing the 4 2 by etching, the semiconductor device can be obtained with two quantum well structure having different well widths.
【００１７】続いて、図３を参照して、本発明の第２の
実施形態について説明する。同図（ａ）が平面図、同図
（ｂ）がＣ−Ｃ線断面図である。この実施形態では、Ｉ
ｎＰからなる基板１の表面のＣ−Ｃ線に沿った中央の幅
の狭い領域Ｓ５をはさんで、基板１表面上にＳｉＮxか
らなる対象形状のマスク２が形成されている。これらの
マスクは、中央部の幅の広い領域２5と、両側部の幅の
狭い領域２6からなる。領域Ｓ５には、ＩｎＰからなる
障壁層３とＧａＩｎＡｓからなる井戸層４が気相成長に
より交互に積層されて量子井戸構造が形成されている。
この量子井戸構造の井戸幅は、幅の広いマスク２5の近
傍では大きく、幅の狭いマスク２6の近傍では小さくな
る。このように井戸幅を異ならせることにより、光の屈
折率が場所に応じて異なるので、光導波路として用いる
ことができる。Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line CC. In this embodiment, I
On the surface of the substrate 1 made of nP, a mask 2 having a target shape made of SiN x is formed on the surface of the substrate 1 across a narrow region S5 at the center along the line CC along the line CC. These masks comprise a wide region 25 at the center and a narrow region 26 at both sides. In the region S5, barrier layers 3 made of InP and well layers 4 made of GaInAs are alternately stacked by vapor phase growth to form a quantum well structure.
The well width of this quantum well structure is large near the wide mask 25 and small near the narrow mask 26 . By varying the well width in this way, the refractive index of light varies depending on the location, so that it can be used as an optical waveguide.
【００１８】[0018]
【発明の効果】以上、説明したように、本発明では、マ
スク近傍の基板表面では障壁層及び井戸層が厚く形成さ
れ、マスクから離れた基板表面では薄く形成されてい
る。また、マスクによる基板表面の被覆率が大きい部分
では障壁層及び井戸層が厚く形成され、被覆率が小さい
部分では薄く形成されている。したがって、マスク形状
や被覆率により障壁層及び井戸層の厚さを自在に設定し
た量子井戸構造の半導体素子が得られる。As described above, in the present invention, the barrier layer and the well layer are formed thick on the substrate surface near the mask, and thin on the substrate surface far from the mask. Further, the barrier layer and the well layer are formed thick in the portion where the coverage of the substrate surface by the mask is large, and thin in the portion where the coverage is small. Therefore, a semiconductor device having a quantum well structure in which the thicknesses of the barrier layer and the well layer are freely set depending on the mask shape and the coverage is obtained.
【図１】本発明の第１の実施形態の平面図及び断面図で
ある。FIG. 1 is a plan view and a cross-sectional view of a first embodiment of the present invention.
【図２】図１の装置の製造工程を示す図である。FIG. 2 is a diagram showing a manufacturing process of the device of FIG. 1;
【図３】本発明の第２の実施形態の平面図及び断面図で
ある。FIG. 3 is a plan view and a cross-sectional view of a second embodiment of the present invention.
１…基板、２…マスク、３…障壁層、４…井戸層。 DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Mask, 3 ... Barrier layer, 4 ... Well layer.
Claims (2)
造を有する半導体素子を形成した半導体装置において、 一つあるいは複数の半導体素子形成領域と、これに隣接
する周辺領域とを有する基板と、 前記半導体素子領域の表面上に、障壁層と井戸層をその
井戸幅あるいは障壁幅に応じた被覆率あるいは形状で該
半導体素子領域に隣接する周辺領域に形成された結晶成
長を阻止するためのマスクを用いた気相成長により交互
に積層させて形成した一層または多層の量子井戸構造か
らなる一つあるいは複数の半導体素子と、を備え、 前記半導体素子の少なくとも１つは、空間的に変化する
量子井戸構造あるいは他の半導体素子と異なる量子井戸
構造を有していることを特徴とする半導体装置。1. A semiconductor device having a semiconductor element having a spatially different quantum well structure formed on the same substrate, comprising: a substrate having one or a plurality of semiconductor element formation regions and a peripheral region adjacent thereto; A mask for preventing crystal growth formed in a peripheral region adjacent to the semiconductor element region on the surface of the semiconductor element region with a barrier layer and a well layer having a coverage or a shape corresponding to the well width or the barrier width. One or a plurality of semiconductor elements each having a single-layer or multilayer quantum well structure formed by alternately stacking the layers by vapor phase growth using GaN. At least one of the semiconductor elements has a spatially varying quantum A semiconductor device having a well structure or a quantum well structure different from other semiconductor elements.
造を有する半導体素子を形成した半導体装置において、 一つあるいは複数の半導体素子形成領域と、これに隣接
する周辺領域とを有する基板と、 前記基板表面の前記周辺領域に形成された結晶成長を阻
止するためのマスクと、 前記マスクで被覆された前記周辺領域に隣接する前記半
導体素子領域の表面上に、気相成長により障壁層と井戸
層を交互に積層させて形成した一層または多層の量子井
戸構造からなる一つあるいは複数の半導体素子と、を備
え、 前記半導体素子の少なくとも１つは、空間的に変化する
量子井戸構造あるいは他の半導体素子と異なる量子井戸
構造を有しており、前記マスクは隣接する領域に形成さ
れる前記半導体素子の量子井戸構造の井戸幅あるいは障
壁幅に応じて前記基板表面における被覆率あるいは形状
を異ならせていることを特徴とする半導体装置。2. A semiconductor device in which semiconductor elements having a spatially different quantum well structure are formed on the same substrate, comprising: a substrate having one or more semiconductor element forming regions and a peripheral region adjacent thereto; A mask for preventing crystal growth formed in the peripheral region on the substrate surface; and a barrier layer and a well formed on the surface of the semiconductor element region adjacent to the peripheral region covered with the mask by vapor phase growth. One or a plurality of semiconductor elements each having a single or multilayer quantum well structure formed by alternately stacking layers, wherein at least one of the semiconductor elements has a spatially varying quantum well structure or another quantum well structure. The semiconductor device has a quantum well structure different from that of the semiconductor device, and the mask corresponds to a well width or a barrier width of the quantum well structure of the semiconductor device formed in an adjacent region. The semiconductor device is characterized in that with different coverage or shape of the substrate surface Te.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13372697A JP3175148B2 (en) | 1997-05-23 | 1997-05-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13372697A JP3175148B2 (en) | 1997-05-23 | 1997-05-23 | Semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63310920A Division JPH02156586A (en) | 1988-12-08 | 1988-12-08 | Method of forming quantum well structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1051079A true JPH1051079A (en) | 1998-02-20 |
| JP3175148B2 JP3175148B2 (en) | 2001-06-11 |
Family
ID=15111483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13372697A Expired - Lifetime JP3175148B2 (en) | 1997-05-23 | 1997-05-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3175148B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6302080B1 (en) | 1998-07-31 | 2001-10-16 | Denso Corporation | Fuel injection system having pre-injection and main injection |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01321677A (en) * | 1988-06-23 | 1989-12-27 | Nippon Telegr & Teleph Corp <Ntt> | Waveguide type semiconductor optical element and manufacture thereof |
| JPH0262090A (en) * | 1988-08-29 | 1990-03-01 | Matsushita Electric Ind Co Ltd | Method for manufacturing optical semiconductor devices |
-
1997
- 1997-05-23 JP JP13372697A patent/JP3175148B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01321677A (en) * | 1988-06-23 | 1989-12-27 | Nippon Telegr & Teleph Corp <Ntt> | Waveguide type semiconductor optical element and manufacture thereof |
| JPH0262090A (en) * | 1988-08-29 | 1990-03-01 | Matsushita Electric Ind Co Ltd | Method for manufacturing optical semiconductor devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3175148B2 (en) | 2001-06-11 |
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