JPH1051436A - Frame synchronizing circuit for frame signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent data from being lost owing to a burst error generated nearby a specific position by deciding frame synchronism when a frame synchronizing word and a frame number word are both decided. SOLUTION: A frame synchronism deciding means 1 compares a PCM signal 21 after bit synchronization with a frame synchronizing word which is held inside to detect a signal whose bits are all or partially matching. Further, the presence of the frame at a normal position is evaluated and a frame synchronizing word establishment state signal 23 is outputted. A frame number deciding means 2 compares the received frame number word with a reference frame number word which is held while increased inside to evaluate whether all or some of the bits are matching, and the state value of the evaluation is outputted as a frame number word establishment state signal 24. A frame synchronism deciding means 3 outputs a frame synchronization establishment signal 26 indicating that frame synchronism is established on based on the state signals 23 and 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit, and more particularly to a frame synchronization signal detection circuit for detecting frame synchronization of a PCM signal.

[0002]

2. Description of the Related Art In general, a remote measurement technique performs data measurement at a remote point via a wireless line or the like, and is widely used for data measurement of flying objects, moving objects, and the like. The digital PCM (pulse code modulation) system has become mainstream.

Various data measured at remote points are input to a modulator, which takes into account a required number of bits and a sampling rate, and converts a PCM signal from a large number of measurement items, frame synchronization words, frame numbers, and the like. A frame is formed, and the modulation is performed continuously and repeatedly using the frame as a unit.

[0004] The PCM signal thus modulated is input to a demodulation device via a communication line such as a radio line, and the demodulation device performs bit synchronization and frame synchronization to separate measurement items in a frame, and performs monitoring and monitoring. It is for recording.

In such a frame synchronization circuit, the input PC
A frame synchronization word is detected from the M signal to synchronize with a frame configured on the modulation device side. Specifically, match detection is performed while sequentially comparing an input bit string with a specified frame synchronization word, and a frame position is specified from the bit string that matches the specified frame synchronization word.

In the PCM signal, a bit string other than the frame synchronization word may coincide with the frame synchronization word. Therefore, in order to prevent frame synchronization at an erroneous position, the frame synchronization word is determined at a specific position of several consecutive frames. For example, a technique such as frame synchronization by detecting the frame synchronization is used.

When data is transmitted / received via a wireless line, fluctuations in the reception intensity of radio waves due to fading,
Errors such as bit inversion, bit loss, and bit duplication for several bits to several seconds due to frequency fluctuations in the transceiver or propagation path occur, and when the frame synchronization is lost due to the error, measurement is performed until frame synchronization is restored. Data will be lost. Therefore, there is a need for a frame synchronization circuit capable of maintaining frame synchronization even when an error occurs and monitoring the state of error occurrence.

[0008]

Problems to be Solved by the Invention
In the frame synchronization circuit disclosed in Japanese Patent Laid-Open Publication No. H11-107, aiming to prevent a frame synchronization state at an erroneous position by an erroneous synchronization detection unit while maintaining stable frame synchronization by allowing inversion of an arbitrary number of bits. Has the following problems.

That is, since the erroneous synchronization state is determined only by the frame synchronization word, when bit loss, bit duplication, or a burst-like error over a long period of time occurs, erroneous synchronization is detected and frame synchronization is performed again. There is a problem that it takes a long time to be taken and data during that time is lost.

In the frame synchronization circuit disclosed in Japanese Patent Application Laid-Open No. 6-141024, prediction and determination of a frame number are performed using a frame number word incremented for each frame, thereby inverting, missing, and duplicating bits. And the like, but with the following problems.

That is, when a bit string other than the frame synchronization word has the same content as the frame synchronization word, an error is detected because the determination of the frame number word is performed at an incorrect position. If an error occurs even if the word or the frame number word is inverted by a single bit, the synchronization is lost, so that even if valid measurement data is included in the frame, it is lost.

An object of the present invention is to provide a frame signal frame synchronizing circuit capable of minimizing data loss with respect to bit loss, bit duplication, and burst errors over several frames. .

Another object of the present invention is to provide a frame synchronization circuit for a frame signal capable of establishing stable frame synchronization with respect to inversion of a bit such as a frame synchronization word and a frame number word occurring near a specific position in a frame. To provide.

[0014]

According to the present invention, there is provided a frame synchronization circuit for a frame signal including a frame synchronization word for frame synchronization and a frame number, which determines a frame synchronization word of an input frame signal. Frame synchronization word determination means, frame number word determination means for determining a frame number of the input frame signal, and frame of the input frame signal based on both determination results of the frame synchronization word detection means and the frame number word detection means A frame synchronization circuit characterized by including frame synchronization determination means for performing synchronization determination is obtained.

[0015] The frame synchronization determination means is characterized in that when the determination of the frame synchronization word and the determination of the frame number word are both performed, the frame synchronization determination of the input frame signal is performed. Further, the frame synchronization word determination means is characterized in that when all or a part of the frame synchronization word matches a prescribed frame synchronization word, it is determined that the frame synchronization word matches.

Further, the frame number word judging means judges that the frame number word matches when all or a part of the frame number word matches a prescribed frame number word. When the frame synchronization word is detected at a position separated from the specified position of the frame synchronization by a predetermined time, the frame synchronization word determination unit determines the subsequent frame synchronization word at the detected position. It is characterized by doing so.

More specifically, the frame synchronization word judging means counts the frame length after the first frame synchronization word is detected, and evaluates whether or not the frame synchronization word exists at a normal position of the frame. The state value of the evaluation is supplied to the frame synchronization judging means, and a reset signal from the frame synchronization judging means restarts from the detection of the first frame synchronization word.

The frame number word judging means evaluates the frame number word of the input frame signal, and supplies a state value of the evaluation to the frame synchronization judging means. The frame number word serving as a reference for evaluation is generated by holding the internally input frame number word and incrementing it for each frame. In addition, the processing is restarted from the input of the first frame number word by the reset signal from the frame synchronization determining means.

The frame synchronization determining means determines establishment of frame synchronization from the status values from the frame synchronization word determining means and the frame number word determining means. If synchronization is lost due to an error, a reset signal is output and frame synchronization is restarted. By doing so, the above object can be achieved.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, a frame synchronization circuit according to the present embodiment includes a frame synchronization word determination unit 1, a frame number word determination unit 2,
It is composed of frame synchronization determining means 3. As shown in FIG. 2, the frame synchronization word determining means 1
It comprises a comparator 5, a frame synchronization word holding register 6, a frame length counter 7, and a sequencer 8. The frame number word determining means 2 comprises a shift register 9, a frame number counter 10, a comparator 11, a frame number word position counter 12, and a sequencer 13, as shown in FIG.

The frame synchronization word judging means 1 will be described. The PCM signal 21 after the bit synchronization in the PCM demodulator is input to the shift register 4. The comparator 5 sequentially compares the contents of the shift register 4 and the contents of the frame synchronization word holding register 6, and sends a full match signal 31 to the sequencer 8 when all bits match, and a partial match signal 32 to the sequencer 8 when all bits match. Output each one.

The frame length counter 7 is reset by the frame synchronization signal 22 input from the sequencer 8, and outputs a frame synchronization word position signal 33 to the sequencer 8 at the timing of the next frame synchronization word input.

The sequencer 8 sends the frame synchronization signal 22 to the frame length counter 7 according to the operation flow chart shown in FIG.
And the state signal 23 to the frame number word determining means 2 and to the frame synchronization determining means 3. As shown in FIG. 4, the sequencer 8 has three states: an initial state, a frame synchronization word determined state, and a frame synchronization word undefined state. The status signal 23 outputs contents indicating the status of the sequencer 8.

The initial state is a state in which the frame synchronization word has not been detected, and the frame synchronization word is detected from a continuously input bit string. Specifically, the initial state is maintained until the all-match signal 31 is input from the comparator 5, and when the all-match signal 31 is input, the frame synchronization signal 22 is output and the state transits to the frame synchronization word determined state.

The frame synchronization word determination state is a state in which the frame synchronization word is detected, and it is evaluated that the frame synchronization word is normally arranged at a specific position for each frame.
More specifically, when either the full match signal 31 or the partial match signal 32 is input from the comparator 5 at the timing when the frame sync word position signal 33 is input, the frame sync word remains in the determined state. If neither signal is input at the same timing, the state transits to the frame synchronization word undefined state.
The frame synchronization signal 22 is output at the timing when the frame synchronization word position signal 33 is input.

The frame synchronization word undefined state is a state in which the frame synchronization word cannot be detected, and it is evaluated whether or not the frame synchronization word is arranged again at a specific position for each frame at a timing continued from the frame synchronization word determination state. Specifically, at the timing when the frame synchronization word position signal 33 is input, the full match signal 31 and the partial match signal 3 are output from the comparator 5.
When either one of the two signals is input, the state transits to the frame synchronization word determined state. When neither signal is input at the same timing, the frame synchronization word remains undefined. The frame synchronization signal 22 is output at the timing when the frame synchronization word position signal 33 is input.

The sequencer 8 includes a frame synchronization determination unit 3
When the reset signal 25 is input from the CPU, the processing is repeated from the detection of the first frame synchronization word. Specifically, sequencer 8
Transitions to the initial state regardless of which state is in FIG.

The frame number word judging means 2 will be described. The PCM signal 21 after the bit synchronization in the PCM demodulator is input to the shift register 9. The frame number counter 10 holds the contents of the shift register 9 when the load signal 41 is input from the sequencer 13, and increments the held contents when the count signal 42 is input from the sequencer 13.

The comparator 11 sequentially compares the contents of the shift register 9 and the frame number counter 10, and outputs a full match signal 43 when all the bits match, and a partial match signal 44 when all the bits match. Output to

The frame number word position counter 12 receives the frame synchronization signal 2 input from the frame synchronization word determination means 1.
2 and outputs a frame number word position signal 45 to the sequencer 13 at the timing when the frame number word is input to the shift register 9.

The sequencer 13 outputs a state signal 24 to the frame synchronization judging means 3 in accordance with the operation flowchart shown in FIG. The sequencer 13 is in the initial state as shown in FIG.
It has four states: a frame number word detection state, a frame number word fixed state, and a frame number word undefined state. State signal 2
4 outputs the contents indicating the state of the sequencer 13.

The initial state is a state in which the frame number word is not held in the frame number counter 10, and after the frame synchronization word is detected by the frame synchronization word determination means 1, the frame number word is stored in the frame number counter. Hold at 10. Specifically, the frame number word position counter 1
2 and remains in the initial state until the frame number word position signal 45 is input. When the frame number word position signal 45 is input, the load signal 41 is output and the state transits to the frame number word detection state.

The frame number word detection state evaluates whether the contents held in the frame number counter 10 in the initial state are frame number words. Specifically, when the all-match signal 43 is input from the comparator 11 at the timing when the frame number word position signal 45 is input from the frame number word position counter 12, the state transits to the frame number word determined state. If the all match signal 43 is not input at the same timing, the state transits to the initial state. Note that when the frame synchronization signal 22 is input from the frame synchronization determination means 1, a count signal 42 is output.

The frame number word determination state is a state in which the frame number word is detected, and evaluates that the frame number word of successive frames changes continuously. Specifically, at the timing when the frame number word position signal 45 is input from the frame number word position counter 12, the comparator 1
When either the full match signal 43 or the partial match signal 44 is input from 1, the frame number word is determined. If neither signal is input at the same timing, the state transits to the frame number word undefined state. When the frame synchronization signal 22 is input from the frame synchronization determination means 1, the count signal 4
2 is output.

The frame number word undefined state is a state in which the frame number word cannot be detected, and it is evaluated whether a continuous frame number word is rearranged from the frame number word determined state. Specifically, the frame number word position counter 1
When either the full match signal 43 or the partial match signal 44 is input from the comparator 11 at the timing when the frame number word position signal 45 is input from 2, the state transits to the frame number word fixed state. If neither signal is input at the same timing, the frame number word remains in an undefined state. Note that when the frame synchronization signal 22 is input from the frame synchronization determination means 1, a count signal 42 is output.

When the sequencer 11 receives the reset signal 25 from the frame synchronization determining means 3, the sequencer 11 starts over with the input of the first frame number word. Specifically, regardless of the state of the sequencer 11 in any state of FIG.

The frame synchronization determining means 3 will be described. The frame synchronization determination means 3 receives the status signal 23 from the frame synchronization word determination means 1 and the status signal 24 from the frame number word determination means 2 and converts the reset signal 25 to the frame synchronization according to the operation flowchart shown in FIG. The frame synchronization determination signal 26 is output to the word determining means 1 and the frame number word determining means 2 to a circuit for separating and monitoring the measurement items in the PCM demodulation circuit.

The frame synchronization determination means 3 has two states, an initial state and a frame synchronization determined state, as shown in FIG.

The initial state is a state in which frame synchronization has not been determined, and waits until a frame synchronization word and a frame number word are detected. Specifically, the status signal 23 from the frame synchronization word determining means 1 is in the frame synchronization word determined state, and the status signal 24 from the frame number word determining means 2 is
Transitions to the frame synchronization determined state when is set to the frame number word determined state. Otherwise, it stays in the initial state.

The frame synchronization determined state is a state in which the frame synchronization is determined, and the detection state of the frame synchronization word and the frame number word is evaluated. Specifically, while the status signal 23 from the frame synchronization word determination means 1 is in the frame synchronization word determination state, or the status signal 24 from the frame number word determination means 2 is in the frame number word determination state, the frame synchronization determination state Stay in. When the state signal 23 is in the frame synchronization word undefined state and the state signal 24 is in the frame number word undefined state, the reset signal 25 is output and the state transits to the initial state. The frame synchronization determination signal 26 is output when the frame synchronization determination unit 3 is in the frame synchronization determination state.

The PC from the frame synchronization determining means 3
The M demodulation circuit does not output a signal for monitoring the status of error occurrence to the circuit that separates and monitors the measurement items. However, by monitoring the status signal 23 and the status signal 24, the occurrence of the error is prevented. The situation can be monitored in detail.

Next, another embodiment of the present invention will be described. As shown in FIG. 7, the frame synchronization circuit according to the present embodiment includes a frame synchronization word determination unit 1, a frame number word determination unit 2, and a frame synchronization determination unit 3.

The frame synchronization word judging means 1 comprises a shift register 4, a comparator 5, a frame synchronization word holding register 6, a frame length counter 7, and a sequencer 8, as shown in FIG. The frame number word determining means 2 and the frame synchronization determining means 3 are the same as in the first embodiment.

The operation of the frame synchronization word judging means 1 will be described. The operations of the shift register 4, the comparator 5, and the frame synchronization word holding register 6 are the same as those in the first embodiment. The frame length counter 7 is reset by the frame synchronization signal 22 input from the sequencer 8, and outputs the frame synchronization word position signal 33 to the sequencer 8 at the timing of the next input frame synchronization word.

In order to determine before and after the timing at which the frame synchronization word position signal 33 is output from the sequencer 8, the frame length counter uses the bit loss determination signal 34 and the bit overlap determination signal 3 at the timing shown in FIG.
5 is output to the sequencer 8. Bit missing determination signal 34
And the bit duplication determination signal 35 is output during a period of の of the number of bits constituting the frame synchronization word.

According to the operation flow chart shown in FIG. 10, the sequencer 8 sends the frame synchronization signal 22 to the frame length counter 7 and the frame number word judging means 2, the state signal 23 to the frame synchronization judging means 3, the bit loss detection signal 27 And a bit duplication detection signal 28 are output to a circuit for separating and monitoring measurement items in the PCM demodulation circuit.

The sequencer 8 has three states: an initial state, a frame synchronization word determined state, and a frame synchronization word undefined state, as shown in FIG. The status signal 23 outputs contents indicating the status of the sequencer 8.

The operation in the initial state is the same as in the first embodiment. The frame synchronization word fixed state is a state in which the frame synchronization word is detected, and it is evaluated that the frame synchronization word is normally arranged at a specific position for each frame, and the frame synchronization word before the specific position is determined. If it is detected, it is determined that a bit has been lost, and the frame length count is corrected.

Specifically, the frame synchronization word position signal 33
Is input from the comparator 5 at the timing when
When either 1 or the partial match signal 32 is input, the frame synchronization signal 22 is output, and the frame synchronization word remains in the determined state. If neither signal is input at the same timing, the frame synchronization signal 22 is output and the state transits to the frame synchronization word undefined state.

When the all match signal 31 is input from the comparator 5 at the timing when the bit loss determination signal 34 is input, the frame synchronization signal 22 and the bit loss detection signal 2
7 is output and the frame synchronization word remains in the determined state. In this state, before the bit duplication determination signal 35 is input, the state transition is performed by the frame synchronization word position signal 33.
No bit duplication is detected.

The frame synchronization word undefined state is a state in which the frame synchronization word cannot be detected, and it is evaluated whether or not the frame synchronization word is arranged again at a specific position for each frame at a timing continued from the frame synchronization word determination state. ,
If a frame synchronization word is detected before or after the specific position, it is determined that a bit loss or bit duplication has occurred, and the frame length count is corrected.

Specifically, the frame synchronization word position signal 33
Is input from the comparator 5 at the timing when
When either 1 or the partial match signal 32 is input, the frame synchronization signal 22 is output and the state transits to the frame synchronization word fixed state. When neither signal is input at the same timing, the frame synchronization signal 22 is output and the frame synchronization word remains in an undefined state.

When the all match signal 31 is input from the comparator 5 at the timing when the bit loss determination signal 34 is input, the frame synchronization signal 22 and the bit loss detection signal 2
7 is output to make a transition to the frame synchronization word determined state. When the all match signal 31 is input from the comparator 5 at the timing when the bit duplication determination signal 35 is input, the frame synchronization signal 22 and the bit duplication detection signal 28 are output, and the state transits to the frame synchronization word fixed state.

The operation when the reset signal 25 is input to the sequencer 8 is the same as in the first embodiment.

With respect to the configuration of the frame synchronization circuit, in each of the above embodiments, the PCM signal 21 was input to both the frame synchronization word judging means 1 and the frame number word judging means 2. The present invention is also realized by a configuration in which 21 is parallelized into a word unit composed of a plurality of bits, the parallel data is output to the frame number word determining means 2, and the shift register 9 in the frame number word determining means 2 is changed to a register. it can.

Regarding the frame synchronization word determining means 1, the first
In the embodiment of the present invention, in order to allow a bit inversion occurring with a certain probability and to obtain stable frame synchronization, the full match signal 31 and the partial match signal 32 are set in the frame synchronization word fixed state and the frame synchronization word undefined state. Although treated equally, due to the tendency of errors occurring in the input PCM signal,
A more detailed input state may be set by changing the handling of both.

The method of generating the partial coincidence signal 32 includes:
Counting the number of matching bits to be valid if they match at or above a certain threshold, or if the number of matching words exceeds the threshold at which the number of matching words is counted compared to a word unit consisting of multiple bits For example, there is a method that is effective.

According to the present invention, in order to allow a bit inversion occurring at a certain probability and obtain a stable frame synchronization, any method for detecting a partial match with a frame synchronization word can be used. But it doesn't matter.

Regarding the frame number word determining means 2, in each of the above embodiments, the frame number word determined state and the frame number word indefinite state are set for the purpose of permitting bit inversion occurring with a certain probability and obtaining stable frame synchronization. In the state, the full match signal 43 and the partial match signal 44 are treated equally, but due to the tendency of errors occurring in the input PCM signal,
A more detailed input state may be set by changing the handling of both.

The method of generating the partial match signal 44 includes:
Counting the number of matching bits to be valid if they match at or above a certain threshold, or if the number of matching words exceeds the threshold at which the number of matching words is counted compared to a word unit consisting of multiple bits For example, there is a method that is effective.

According to the present invention, any method for detecting a partial match with a frame number word in order to allow a bit inversion occurring at a certain probability and obtain stable frame synchronization is provided. But it doesn't matter.

The value obtained by incrementing the content of the frame number word for each frame is arranged. However, if the content of the next frame can be predicted from the content of a certain frame, what kind of content is used. But it doesn't matter.
For example, a PCM in which a subframe number word is arranged in each frame and a mainframe is composed of a plurality of frames.
In a signal, the same effect can be obtained by treating the subframe number word in the same manner as the frame number word in each of the above embodiments.

In each of the above embodiments, the frame synchronization determining means 3 is changed from the frame synchronization determined state to the initial state when the frame synchronization word and the frame number word can no longer be detected. When the probability of occurrence of the frame synchronization word is extremely low, the number of frames in which both the frame synchronization word and the frame number word cannot be detected is counted by a counter or the like using the frame synchronization signal 22, and when a certain threshold or more is reached, the frame synchronization is determined. By transitioning from the state to the initial state, stable frame synchronization can be obtained even for burst-like errors over several frames.

In the initial state, the frame synchronization word and the frame number word are both detected, so that the transition from the initial state to the frame synchronization determination state is made. However, if there is enough time for the frame synchronization, the frame synchronization signal is output. The number of frames in which both the frame synchronization word and the frame number word are detected using the counter 22 is counted by a counter or the like. When the same contents as the word and the frame number word occur by chance in the frame, the possibility of synchronization at an incorrect frame position can be further reduced.

In order to determine before and after the timing at which the sequencer 8 outputs the frame synchronization word position signal 33, the frame synchronization word determination means 1 shown in FIG.
The bit loss determination signal 34 and the bit duplication determination signal 35 are generated. However, as long as it is possible to determine before and after the timing, the configuration of the signals may be any method.

In consideration of the possibility that bit strings other than the frame synchronization word may have the same contents as the frame synchronization word, and to obtain stable frame synchronization with an arbitrary frame synchronization word,
Although the output periods of the bit loss determination signal 34 and the bit duplication determination signal 35 are output for a period of １ ／ of the number of bits forming the frame synchronization word, the output periods of both signals may be arbitrary.

[0068]

As described above, according to the present invention, frame synchronization can be obtained by following bit loss or bit duplication, and burst errors over several frames can be obtained. Also, by quickly re-establishing frame synchronization, there is an effect that data loss can be reduced as much as possible.

In addition, stable frame synchronization can be obtained with respect to inversion of bits generated near a specific position in a frame such as a frame synchronization word, a frame number word, and the like, and the occurrence state of an error can be monitored in detail. .

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of a frame synchronization word determining unit 1 in FIG.

FIG. 3 is a block diagram of a frame number word determining means 2 in FIG.

FIG. 4 is a flowchart showing an operation of the sequencer 8 in FIG.

FIG. 5 is a flowchart showing an operation of the sequencer 13 in FIG.

FIG. 6 is a flowchart showing the operation of the frame synchronization determination means 3 in FIG.

FIG. 7 is a block diagram of a second embodiment of the present invention.

8 is a block diagram of the frame synchronization word judging means 1 in FIG.

9 is a timing chart of an output waveform of a frame length counter in FIG.

FIG. 10 is a flowchart showing the operation of the sequencer 8 in FIG.

[Explanation of symbols]

 1 Frame synchronization word determination means 2 Frame number word determination means 3 Frame synchronization determination means 4, 9 Shift register 5, 11 Comparator 6 Frame synchronization word holding register 7 Frame length counter 8, 13 Sequencer 10 Frame number counter 12 Frame number word position counter

Claims (5)

[Claims] 1. A frame synchronization circuit for a frame signal including a frame synchronization word for frame synchronization and a frame number, the frame synchronization word determining means for determining a frame synchronization word of an input frame signal; Frame number word determining means for determining a frame number of a signal, and frame synchronization determining means for performing frame synchronization determination of the input frame signal based on both determination results of the frame synchronization word detecting means and the frame number word detecting means. A frame synchronization circuit characterized by including: 2. The apparatus according to claim 1, wherein said frame synchronization determination means performs frame synchronization determination of said input frame signal when said frame synchronization word determination and said frame number word determination are both performed. Item 2. The frame synchronization circuit according to Item 1. 3. The frame synchronization word judging means is adapted to judge that a frame synchronization word matches when all or a part of the frame synchronization word matches a prescribed frame synchronization word. 3. The frame synchronization circuit according to claim 1, wherein 4. The frame number word judging means judges that a frame number word matches when all or a part of the frame number word matches a prescribed frame number word. 4. The frame synchronization circuit according to claim 1, wherein: 5. When the frame synchronization word is detected at a position separated by a predetermined time from a prescribed position of the frame synchronization, the frame synchronization word determination means determines a subsequent frame synchronization word at the detected position. 5. The frame synchronization circuit according to claim 1, wherein: