JPH1051808A - Digital image signal recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image recorder by which a moving image signal and a still image signal with higher definition are recorded and a still image signal with a different YC picture element ratio is recorded. SOLUTION: An HDS signal whose YC picture element ratio is 2:1 is stored in an HD frame memory 15 and its read address is controlled to divide image data of one frame of the HDS signal into 1/8 and dummy data are added and the HDS signal is converted into 8-frame of SD signal data. In this case, the chamber of picture elements of a Y signal is increased by the dummy data to convert the Y signal into SD signal data whose YC picture element number ratio is 4:1. The signal after conversion is given to a VTR section 2 of the digital video cassette recorder standards and the signal is recorded in a magnetic tape 41.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital image signal recording device and a recording / reproducing device, and more particularly to a device for recording / reproducing a high-definition still image signal.

[0002]

2. Description of the Related Art A standard called "DVC" (hereinafter referred to as "DVC standard") has been proposed as a standard of a digital VTR (video tape recorder) for compressing and recording image data.
eport Vol. 41 No.2 Apr. 1995 pages 48 to 55
page). The DVC standard includes a standard for recording an image signal (SD signal) having a normal resolution at a current broadcast level and a standard for recording an image signal (HD signal) having a high definition. The outline of the standard for recording the information is described below.

[0003] In the so-called 525/60 system (the NTSC system or the like corresponds to this), the video signal is (4:
1: 1). As for the luminance (Y) signal, the number of effective pixels in the horizontal direction is 720 pixels, the number of effective lines in the vertical direction is 480 in the frame, and the color difference (Cb, Cb).
r) For the signal, the number of effective pixels in the horizontal direction is 180 pixels, and the number of effective lines in the vertical direction is 480, which is the same as the luminance signal.

[0004] DCT (Discrete Cosine Transform) operation is performed by blocking these effective pixel data. A block for DCT operation (hereinafter, referred to as “DCT block”) is
Specifically, each of the luminance (Y) signal and the color difference (Cb, Cr) signal is configured by dividing one frame pixel into eight horizontal pixels × eight vertical pixels. Then, as shown in FIG. 8, Y corresponding to the same area at the same position on the screen
A 6 DCT block including four DCT blocks of a signal and one DCT block of a Cb signal and a Cr signal is called a “macro block”. Further, the screen of one frame is divided in units of 27 macro blocks to form a super block as shown in FIG. Then, one superblock is selected from each column in FIG. 9, one macroblock is extracted from each superblock, and one video segment is composed of five macroblocks. At the time of compression, control is performed so that the data amount is within a predetermined amount in video segment units.

The DCT operation includes a mode in which 8 × 8 DCT is performed with 8 horizontal pixels × 8 vertical pixels in frame units,
8 × 4 D with 8 horizontal pixels × 4 vertical pixels in field units
There is provided a mode for performing CT and taking the sum and difference of each DCT coefficient of two fields, and can be adaptively switched at the time of encoding. The DCT coefficient obtained by the DCT operation is selected by selecting a quantization table so that the data amount after the quantization and the variable length coding is equal to or less than a predetermined value and the value closest to the predetermined value. Be transformed into

The data after quantization and variable length coding are formatted in macroblock units as shown in FIG. 10, and further, as shown in FIG.
It is recorded on a magnetic tape in the form of a sync block to which a D code and a parity word for error correction are added. One frame of image data is recorded by being divided into ten tracks. One row of image data of the super block in FIG. 9 is recorded on one track. FIG.
Is a diagram showing an arrangement of data on one track.

The data formatted as shown in FIG. 10 also includes various parameters required for decoding (error and concealment information STA, selected quantization table number QNO, etc.). Here, data of one video segment is stored in five sync blocks. At this time, the DC component data is in the DC area (DC0 to DC5) in the figure.
And the AC component is stored in the AC area. The AC component is the corresponding DCT in the same sync block as the DC component.
Basically, the data is stored in the AC area of the block. However, if the amount of data becomes larger than the capacity of the allocated area, a vacant AC area in the same sync block or a vacant area in the same video segment is used. The existing AC area is diverted.

[0010] The ID code shown in FIG. 11 includes a track pair number indicating a sync block of a track of all 10 tracks constituting image data of one frame, and a number of tracks in one track. A sync block number indicating whether the block is the third sync block is stored. Further, the ID code of the sync block storing the image data includes a sequence number (SE
Q. No. ) Is stored. This is a series of 12
Numbers from 0 to 11 are assigned to frames.

In FIG. 12, ITI is ITI (Ins
ert and Track Information
n) A sector in which information mainly for facilitating tracking control during insert editing is recorded. AUDI
O is an audio sector, which is composed of nine sync blocks storing audio data and five sync blocks storing outer parity. VIDEO is a video sector and is composed of 135 sync blocks storing video data, three sync blocks storing auxiliary data called video AUX, and 11 sync blocks storing outer parity. SUBCO
DE is a subcode sector, which is an area where time code information and the like are recorded. In FIG. 12, the portions other than those described above are portions called gaps, and serve as margins for preventing other sectors from being destroyed during insert editing in sector units.

[0010] Standards for HD signals (hereinafter referred to as "HD-D
The “VC standard” is basically the same as the standard for the SD signal described above. So-called 1125/60
In the method, the number of effective pixels in the horizontal direction of the Y signal is 1008 pixels, and the number of effective lines in the vertical direction is 1024 in the frame.
For each of the color difference signals (Cb and Cr signals), the number of effective pixels in the horizontal direction is 336 pixels, and the number of effective lines in the vertical direction is recorded as 512 image signals in the frame.
As shown in FIG. 13, the macroblock in this case is an 8DCT block composed of six DCT blocks of Y signal and one DCT block of Cb and Cr signals corresponding to the same area at the same position on the screen. It consists of.

[0011]

The DVC standard includes a standard for recording and reproducing an SD signal and a standard for recording and reproducing an HD signal which is a high-definition moving image signal, as described above. A standard for recording and reproducing a still image signal with higher definition than a signal or a standard for recording and reproducing a still image signal with higher definition than an HD signal is not defined. Some image signals have different ratios (YC pixel number ratio) between the number of pixels of the luminance signal and the number of pixels of the color difference signal. Typically, the ratio of the number of YC pixels is 2: 1.
And 4: 1.

The present invention has been made by paying attention to this point, and is capable of recording a moving image signal and a still image signal with higher definition, and recording a still image signal having a different YC pixel number ratio. It is an object of the present invention to provide a digital image signal recording device capable of performing the above.

[0013]

According to a first aspect of the present invention, there is provided an image processing apparatus comprising: a luminance signal and two color difference signals; the number of pixels of the luminance signal and each pixel of the two color difference signals; A digital image signal recording apparatus for recording an image signal of a first definition, wherein the ratio of the number to the number is m: 1 (m is an integer of 2 or more), wherein the digital signal comprises a luminance signal and two color difference signals; And the ratio of the number of pixels to the number of pixels of each of the two color difference signals is n: 1 (where n is n
<M is an integer of 1 or more), and the still image signal of the second definition higher than the first definition is converted into the image signal of the first definition by dividing the image signal into s (an integer of 2 or more). And
A division conversion unit that outputs a divided conversion signal; and a recording unit that performs predetermined processing on the division conversion signal and records the divided conversion signal on a recording medium. Image information compression means for compressing information, and performing signal processing in units of macroblocks each including one predetermined pixel block of the two color difference signals and a corresponding m predetermined pixel blocks of the luminance signal; The division and conversion means performs a block set including n predetermined pixel blocks of a luminance signal constituting the image signal of the second definition and one predetermined pixel block of two color difference signals, The macroblock is characterized by adding (mn) predetermined pixel blocks consisting of dummy data.

According to a second aspect of the present invention, in the digital image signal recording apparatus according to the first aspect, the pixels of the luminance signal are thinned by thinning out the pixels of the color difference signal of the second definition still image signal. The ratio between the number of pixels and the number of pixels of each of the two color difference signals is converted to m: 1.
A thinning still image signal having a resolution of? Is divided into t (an integer of 2 or more) to convert the image signal into the first definition image signal and output as a thinning-out divided conversion signal. The division conversion signal or the thinning division conversion signal is recorded on the recording medium.

According to a third aspect of the present invention, in the digital image signal recording apparatus according to the second aspect, the dummy data has the same value at least in the range of the predetermined pixel block. The invention according to claim 4 comprises a luminance signal and two color difference signals, and a ratio between the number of pixels of the luminance signal and the number of pixels of each of the two color difference signals is m: 1 (m is 2 or more). ), A digital image signal recording / reproducing apparatus for recording / reproducing an image signal of the first definition, comprising a luminance signal and two color difference signals, the number of pixels of the luminance signal and the respective pixels of the two color difference signals A still image signal of a second definition higher than the first definition is divided by s (an integer of 2 or more), wherein the ratio of the number to the number is n: 1 (n is an integer of 1 or more where n <m). By performing a predetermined process on the divided conversion signal and recording the processed signal on a recording medium; and Playback of the signal recorded in the And a reproduction conversion means for converting the reproduction output signal into the second definition still image signal and outputting the same, and the recording means performs orthogonal transformation for each predetermined pixel block. Image information compressing means for compressing image information by performing a macroblock composed of one predetermined pixel block of each of the two color difference signals and a corresponding m predetermined pixel block of the luminance signal as a unit And the division conversion means includes n predetermined pixel blocks of a luminance signal constituting the image signal of the second definition and one predetermined pixel block of two color difference signals. The macroblock is characterized by adding (mn) predetermined pixel blocks composed of dummy data to a block set.

According to a fifth aspect of the present invention, the luminance signal and the second
Chrominance signals, and the number of pixels of the luminance signal and the two
In a digital image signal recording apparatus for recording an image signal of the first definition, the ratio of each of the color difference signals to the number of pixels is m: 1 (m is an integer of 2 or more). And the ratio of the number of pixels of one signal to the number of pixels of each of the other two signals is n: 1 (n is n <n
m), the still image signal of the second definition higher than the first definition is converted into the image signal of the first definition by dividing it into s (an integer of 2 or more). A division conversion unit that outputs a divided conversion signal, and a recording unit that performs predetermined processing on the division conversion signal and records the divided conversion signal on a recording medium, wherein the recording unit performs orthogonal transformation for each predetermined pixel block. Image information compression means for compressing image information, wherein a macroblock consisting of one predetermined pixel block of each of the other two signals and a corresponding m predetermined pixel block of the one signal is used as a unit Performing signal processing, wherein the dividing and converting means comprises n predetermined pixel blocks of the one signal constituting the image signal of the second definition, and one predetermined pixel block of the other two signals. Block consisting of Set to consist of dummy data (m-
The macroblock is constituted by adding n) predetermined pixel blocks.

According to the first aspect of the present invention, a block composed of n predetermined pixel blocks of the luminance signal of the second definition image signal and one predetermined pixel block of two color difference signals. A division conversion is performed so as to form a macroblock by adding (mn) predetermined pixel blocks composed of dummy data to the set, and a predetermined process is performed on the signal after the division conversion, and the recording medium Will be recorded.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing the configuration of a digital image signal recording / reproducing apparatus according to an embodiment of the present invention.
And an image signal recording / reproducing unit 2.

The image signal switching processor 1 has an input terminal 11 to which a digitized SD signal is input, and an input to which a digitized high-definition still image signal (hereinafter referred to as "HDS signal") is input. Terminal 12 and the reproduced HDS
An output terminal 19 for outputting a signal, an output terminal 20 for outputting a reproduced SD signal, and first and second switch circuits 13 and 1 for switching between the SD signal and the HDS signal.
4, first and second HD frame memories 15 and 16 for storing HDS signals in frame units, a recording processing circuit 17 for inserting dummy data and the like, and a reproduction processing circuit 18 for removing dummy data and the like. An address control circuit 10 for controlling read / write addresses of the first and second HD frame memories 15 and 16 is a main component.

As shown in FIG. 2A, the recording processing circuit 17 includes a dummy data adding circuit 1 for adding dummy data.
7a, a color difference signal horizontal thinning circuit 17b for thinning out pixels in the horizontal direction of the color difference signal, and a switch circuit 17c. As shown in FIG. 2B, the reproduction processing circuit 18 includes a dummy data removal circuit 18a for removing dummy data added at the time of recording, and a chrominance signal for interpolating pixels in the horizontal direction of the chrominance signal thinned at the time of recording. Horizontal interpolation circuit 1
8b and a switch circuit 18c.

The recording processing circuit 17 converts one HD frame into 8
A first mode for dividing (a mode in which the switch circuit 17c is in the illustrated switching position) and one HD frame divided into four parts,
It is configured to be switchable to a second mode (a mode in which the switch circuit 17c is at a switching position opposite to that shown in the drawing) in which the processing for thinning out pixels in the horizontal direction of the color difference signal is performed, and the reproduction processing circuit 18 also corresponds to this. The first mode (the mode in which the switch circuit 18c is in the illustrated switching position) and the second mode in which the processing for interpolating the horizontal pixels of the color-difference signal (the switching circuit 18c is in the opposite switching position). ), And each switch circuit is switched by a control signal from a control unit (not shown).

In this embodiment, the Y signal of the HDS signal is
The number of effective pixels in the horizontal direction is 1280, and the number of effective lines in the vertical direction is frame (hereinafter, the HDS signal frame is referred to as “HD
A frame of the SD signal is referred to as “SD frame”), and the number of Cr and Cb signals is 1024.
The number of pixels in the horizontal direction is 640 (the number of pixels obtained by thinning out the pixels of the Y signal to １ ／), and the number of pixels in the vertical direction is 1024, which is the same as the Y signal.

The input HDS signal is supplied to a first HD frame memory 15 and an address control circuit 10,
HDS signals for HD frames are stored in the first HD frame memory 15. The address control circuit 10 controls the read address of the HD frame memory 15 as described later, rearranges the pixels of the HDS signal, and outputs the HDS signal read from the HD frame memory 15 via the recording processing circuit 17. And supplied to the first switch circuit 13. The first switch circuit 13 switches between the SD signal and the HDS signal in which the pixels are rearranged, and supplies the signal to the blocking circuit 21 of the image signal recording / reproducing unit 2.

In the present embodiment, the image signal recording / reproducing unit 2 is constituted by a VCR of the DVC standard, and is hereinafter referred to as "VTR unit 2". The image signal recording system of the VTR unit 2 includes a blocking circuit 21 that performs blocking for DCT operation,
A DCT circuit 22 for performing a CT operation, a quantization circuit 23 for performing a quantization, and a VLC (Variable Len) for performing a variable length encoding.
gth Coding) circuit 24, an auxiliary information writing circuit 25 for writing information to subcode sectors, adding video AUX data, and the like; an error correction encoding circuit 26 for adding parity bits for error correction; A sync block synthesis recording and modulation circuit 27 for performing modulation for recording on a magnetic tape while synthesizing blocks and a magnetic head 28 for recording on a magnetic tape 41 are main components. A magnetic head 28 for reproducing from the magnetic tape 41, a SYNC detection / reproduction / demodulation circuit 29 for detecting and demodulating a sync block, an error correction decoding circuit 30 for performing error correction based on parity bit information, Sector data, video A
Auxiliary information reading circuit 3 for reading UX data etc.
1 and VLD (Variable Length Decode) for performing variable length decoding.
coding) circuit 32 and an inverse quantization circuit 33 for performing inverse quantization
And an inverse DCT circuit 34 for performing an inverse DCT operation and a pixel rearranging circuit 35 for rearranging pixels as main components.

The output signal of the pixel rearranging circuit 35 of the VTR unit 2 is input to the second switch 14 of the image signal switching processing unit 1. The second switch circuit 14 outputs the reproduced signal to the SD signal output terminal 20 when the signal is an SD signal, and outputs the signal to the second HD frame memory 16 via the reproduction processing circuit 18 when the signal is an HDS signal. Is done. HD
When reproducing the S signal, the address control circuit 10 controls the write address of the HD frame memory 16 so that the arrangement of the pixels rearranged at the time of recording is restored, and also controls the write address of one HD frame in the order inputted at the time of recording. The read address is controlled so that the data is output.

Next, a method of dividing an HD frame and rearranging pixels at the time of recording an HDS signal will be described. The input HDS signal is stored in the HD frame memory 15, is divided into eight in the screen area, and is converted so that the image signal in the divided area corresponds to one frame (one SD frame) of the SD signal. , VTR unit 2.

FIG. 3 is a diagram for explaining a method of dividing the Y signal into eight in the processing in the first mode (mode in which one HD frame is divided into eight). One HD frame is divided into four parts in the horizontal direction and two parts in the vertical direction. The divided areas A, B, C, D, E, F, G, and H are each horizontally divided into 320 frames.
It is composed of pixels × 512 vertical pixels. Since one SD frame is composed of 720 horizontal pixels × 480 vertical pixels, each area A to A
Since H does not correspond to one SD frame as it is, the following dummy data insertion and pixel movement are performed.

First, as shown in FIG. 3B, in the eight divided areas (320 horizontal pixels × 512 vertical pixels), eight dummy data pixels (eight horizontal pixels × 512 vertical pixels) are provided every eight pixels in the horizontal direction. It is inserted to make horizontal 640 pixels × vertical 512 pixels. At this time, the values of the dummy data are all “16”
And In FIG. 3B, the width of eight pixels in the horizontal direction is enlarged for easy viewing.

Next, as shown in FIG.
The left end and the lower end of the pixel × vertical 512 pixel area are made to correspond to the left end and the lower end of the SD frame, respectively. Then, the pixels of the upper protruding region R1 (horizontal 64
0 pixels × 32 pixels vertically) is moved to the right peripheral region R2 (80 horizontal pixels × 256 vertical pixels) of the SD frame.
At this time, the minimum unit is 8 horizontal pixels × 8 vertical pixels,
Move as much as possible in that unit. Further, as for the Y signal, as shown in FIG. 4, since a macroblock is composed of 32 horizontal pixels × 8 vertical pixels, the Y signal is moved in this unit as much as possible. Here, of the four DCT blocks of the Y signal, two blocks with hatching are blocks of dummy data.

Further, data having a value of "16" is stored as dummy data in a region R3 (horizontal 80 pixels × direct 224 pixels) in the SD frame which is hatched upward and to the right. By the above processing, the Y signal of one SD frame is formed. The Cr and Cb signals are also divided into eight similarly to the Y signal, and each region is set to 160 horizontal pixels × 512 vertical pixels. Then, similarly to FIG. 3C, the left end and the lower end of each of the divided areas are 1SD of the color difference signal.
Correspond to match the left end and lower end of the frame (180 horizontal pixels x 480 vertical pixels). Further, the horizontal 160 pixels × vertical 32 pixels of the region corresponding to the region R1 are replaced with the region R1.
2 right peripheral area (20 horizontal pixels × 256 vertical pixels)
(Pixels), and data having a value of “128” is stored as dummy data in an area (20 horizontal pixels × 224 vertical pixels) corresponding to the area R3. At this time, the horizontal unit is moved as much as possible with the minimum unit of 8 horizontal pixels × 8 vertical pixels.

As described above, the pixel data of the Y signal, Cr and Cb signals for 1/8 frame of the HDS signal is
One frame of the D signal is sequentially converted into pixel data of Y signal, Cr and Cb signals, and an image signal corresponding to one HD frame is converted into an image signal of 8SD frame and input to the VTR unit 2.

In the recording system of the VTR section 2, special processing for the HDS signal described below is performed together with signal processing such as DCT operation, quantization, and variable length coding according to the DVC standard as described above. Image information is recorded on the magnetic tape. Here, according to the DVC standard, image data of one SD frame is divided into ten tracks and recorded, and thus these ten tracks are referred to as one track frame.

In the first mode, 8 SD frames corresponding to 1 HD frame are recorded over 8 track frames (80 tracks). Also, in the subcode sector, which is an auxiliary information recording area of each track frame, information indicating that a certain part of the eight divided HD frames has been recorded in the track frame, and which part is recorded. And information indicating the number of pixels of the Y signal and the color difference signal, and information indicating the aspect ratio and the like. This processing is performed by the auxiliary information writing circuit 25.

Next, processing in the reproduction system of the VTR unit 2 will be described. The data recorded on the magnetic tape is reproduced and demodulated to form a digital data string. From this data string
The YNC word (see FIG. 11) is detected, and data of one sync block is obtained. Error detection / correction processing using inner parity is performed on the reproduced data thus obtained in the sync block, and error detection / correction processing using outer parity is further performed on video data and the like. . Thereafter, reading of auxiliary information, variable-length decoding (reverse processing of variable-length encoding), inverse quantization, and inverse DCT operation are sequentially performed, and the pixels are rearranged in the original pixel arrangement, and image signal switching is performed. The second of the processing unit 1
Is output to the switch circuit 14.

The above is the processing common to the SD signal and the HDS signal. Further, at the time of reproducing the HDS signal, the auxiliary information reading circuit 31 reads the data of the subcode sector, and obtains necessary information such as information indicating which part of the 1HD frame is recorded in the track frame. Then, information on the HDS signal is supplied to the image signal switching processing unit 1.

Reproduction processing circuit 18 of image signal switching processing section 1
Then, the dummy data added at the time of recording is removed. The address control circuit 10 performs address control when storing the reproduction data in the second HD frame memory 16 based on the information on the HDS signal supplied from the VTR unit 2.

Similarly, the data of all the eight divided areas is stored in the HD frame memory 16 and simultaneously stored in the 1 HD.
The data is read from the HD frame memory 16 as frame data. The aspect ratio and the like of the read image are determined with reference to the information recorded in the subcode sector. Thus, a reproduced HDS signal is obtained.

Next, the processing in the second mode (mode in which the processing of thinning out the pixels in the horizontal direction of the color difference signal) is described. The second mode is a mode in which the HDS signal is recorded in a 4-track frame. In the second mode, the Y signal is divided into four in the screen area as shown in FIG. That is,
Horizontal 1280 pixels × vertical 1024 pixels are divided into two in the horizontal direction and the vertical direction, respectively, and divided into four. Each of the divided areas A to D is composed of 640 horizontal pixels × 512 vertical pixels, and is converted into pixel data of a Y signal of one SD frame in the same manner as in the first mode. Also in the second mode, dummy data whose values are all "16" are inserted into an area corresponding to the area R3 in FIG.

On the other hand, the Cr and Cb signals are 1 /
It is decimated to 2 to make 320 horizontal pixels × 1024 vertical pixels, and is further divided into two in the horizontal and vertical directions like the Y signal to be divided into four. The number of pixels in the divided area is 16 horizontal.
0 pixels × 512 vertical pixels. This is converted into pixel data of Cr and Cb signals of one SD frame in the same manner as in the first mode.

Thus, in the second mode, 1HD
The frame is divided into four parts, converted into 4SD frame image data, supplied to the VTR unit 2, and recorded on a magnetic tape. In the second mode, 4 SD frames corresponding to 1 HD frame are 4 track frames (40 tracks).
Is recorded.

In a subcode sector, which is an auxiliary information recording area of each track frame, information indicating that a certain portion of a 1 HD frame divided into four is recorded in the track frame, and which portion is recorded. Is recorded, information indicating the number of pixels of the Y signal and the color difference signal, and information indicating the aspect ratio and the like are recorded.

In the present embodiment, the first switch circuit 13 in FIG. 1 is switched by the user selecting the recording of the SD signal or the recording of the HDS signal. Also,
The switch circuit 17c of the recording processing circuit is also switched when the user selects the first or second mode.
The information indicating whether the signal recording is the SD signal recording or the HDS signal recording and the information indicating the first mode or the second mode are supplied to a control unit (not shown). I do. At the time of reproduction, the control unit determines from the auxiliary information read by the auxiliary information read circuit 31 whether the signal is the SD signal, the HDS signal, or the first or second mode, and switches the switch circuits 14 and 18c. Is performed.

As described above, in the first mode of the present embodiment, the ratio of the number of pixels of the Y signal to the number of pixels of the Cr signal or Cb signal (YC pixel number ratio) is 2: 1. Is divided into eight, and dummy data of eight pixels is inserted every eight pixels in the horizontal direction of the Y signal, so that the YC pixel number ratio is 4:
Since the conversion into one SD signal is performed, it is possible to provide an image signal recording apparatus capable of recording HDS signals having different YC pixel number ratios.

A macro block, which is a processing unit in the VTR unit 2, includes two dummy data blocks of the Y signal as shown in FIG. 4, and a DCT block composed of data of the same value is a DCT block. By performing the operation, all the AC coefficients become “0”, so that other DCT
The number of bits can be assigned to each block, and recording and reproduction can be performed while maintaining the image quality of the HDS signal at high quality.

In the second mode of this embodiment, the pixels of the color difference signal are thinned out to convert an HDS signal having a YC pixel ratio of 2: 1 into an SD signal having a YC pixel ratio of 4: 1 and record the converted signal. Since the reproduction is performed, the quality of the image signal is slightly deteriorated and the number of photographed (recorded) images can be increased.

The number of pixels of the HDS signal is not limited to 1280 horizontal pixels × 1024 vertical pixels in the Y signal, and may be, for example, 1920 horizontal pixels × 1036 vertical pixels. Further, it is not always necessary to divide one HD frame equally into eight or four parts. For example, 1920 horizontal pixels × 1036 vertical pixels may be divided into 12 or 6 parts.

The value of the dummy data stored in the margin of one SD frame is not limited to "16" or "128", but is a value of a DCT block (8 horizontal pixels × 8 vertical pixels) as a unit for performing the DCT operation. Data having the same value in the range may be used. Further, the division does not necessarily have to be performed in the screen area. For example, the division in the vertical direction may be performed so that different SD frames are formed in units of 8 pixels.

The image signal (HDS signal) does not need to be composed of the Y signal, the Cr signal and the Cb signal, but is composed of, for example, a G (green) signal, an R (red) signal, and a B (blue) signal. It may be.

(Second Embodiment) This embodiment uses a VTR unit 2 conforming to the DVC standard for HD signals,
Still image signal with a higher definition than the
S signal) is recorded and reproduced. The configuration of the image signal recording / reproducing apparatus of this embodiment is basically the same as that of the first embodiment shown in FIG.
The signal input and the SD signal output become the HD signal input and the HD signal output, respectively.
The still image signal output is a UHD still image signal input and a UHD still image signal output, respectively, and the HD frame memory is a UHD frame memory. The input UHDS signal in this embodiment is composed of a G (green) signal, an R (red) signal, and a B (blue) signal, and the number of effective pixels in the horizontal direction of the G signal is 2016 pixels, and the number of effective lines in the vertical direction is UHD. There are 1024 lines in a frame, and the R and B signals are digital signals of 1008 horizontal pixels × 512 vertical pixels, respectively. In the following description, one frame of the UHDS signal is called one UHD frame, and one frame of the HD signal is called one HD frame.

In this embodiment, one UHD frame is divided into three in a screen area and converted into 3HD frame image data. Specifically, as shown in FIG. 6A, the G signal is divided into three in the horizontal direction, and each of the divided areas A to C is
It consists of 672 horizontal pixels × 1024 vertical pixels. Next, as shown in FIG. 6B, dummy data of 8 pixels (horizontal 8 pixels × vertical 1024 pixels) is inserted every 16 pixels in the horizontal direction into each of the three divided areas, and 1008 horizontal × 10 vertical pixels are inserted.
Assume 24 pixels. This pixel data is stored in Y of 1 HD frame.
Treated as signal pixel data. At this time, the values of the dummy data are all “16”. In FIG. 6B, the widths of 16 pixels and 8 pixels in the horizontal direction are enlarged for easy viewing.

Similarly, by dividing the R and B signals into three, an image signal of 336 horizontal pixels × 512 vertical pixels is obtained. Each of these pixel data is 1HD
It is handled as pixel data of the Cr and Cb signals of the frame.
The DVC standard for HD signals is 1125/6 as described above.
In the 0 method, the Y signal is 1008 horizontal pixels × 1024 vertical pixels.
Since the pixels and the color difference signals (Cb and Cr signals) are 336 horizontal pixels × 512 vertical pixels, 1
The pixel data of the G signal, the R signal and the B signal of the UHD frame are converted into the pixel data of the Y signal, Cr and Cb signals of the 3HD frame, and this is supplied to the VTR unit 2 conforming to the DVC standard of the HD signal, Will be recorded.
At this time, as shown in FIG. 7, the macroblock serving as a processing unit is composed of six DCT blocks of Y signals (actually,
Signal) and one DCT block each of Cr and Cb signals (actually, an R signal and a B signal, respectively).
Of the six DCT blocks of the Y signal, two blocks are blocks of dummy data.

At the time of reproduction, a process reverse to that at the time of recording is performed as in the first embodiment, and a reproduced ULDS signal is output.
As described above, according to the present embodiment, it is possible to provide an image signal recording / reproducing apparatus capable of recording and reproducing an HD signal and a still image signal having higher definition than the HD signal.

[0053]

As described above in detail, according to the first aspect of the present invention, n predetermined pixel blocks of a luminance signal of a second definition image signal and one of each of two color difference signals are provided. Is divided and converted into a macro block by adding (mn) predetermined pixel blocks made of dummy data to a block set made up of the predetermined pixel blocks of FIG. Since the image signal is converted into an m: 1 image signal and recorded on a recording medium, it is possible to provide an image signal recording apparatus capable of recording a high-precision still image signal having a different YC pixel ratio.

According to the second aspect of the present invention, the second
By thinning out the pixels of the chrominance signal of the still image signal of the definition, the ratio between the number of pixels of the luminance signal and the number of pixels of each of the two chrominance signals is converted to m: 1. Since the still image signal of high definition is converted into a thinned-out divided conversion signal by dividing by t (an integer of 2 or more) and recorded on the recording medium, the number of recordable still images can be increased.

According to the third aspect of the present invention, since the inserted dummy data has the same value at least in the range of the predetermined pixel block, the data amount at the time of encoding is minimized, and It is possible to increase the amount of recording data in the area, and to improve the reproduction image quality.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a digital image signal recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a part of the apparatus of FIG. 1 in detail.

FIG. 3 is a diagram for explaining a method of converting a high-definition still image signal into a normal-resolution image signal.

FIG. 4 is a diagram for explaining a configuration of a macroblock of an image signal obtained by conversion.

FIG. 5 is a diagram for explaining a method of converting a high-definition still image signal into a normal-resolution image signal.

FIG. 6 is a higher definition still image signal (UHDS signal).
FIG. 4 is a diagram for explaining a method of converting the image signal into a high-definition image signal (HD signal).

FIG. 7 is a diagram illustrating a configuration of a macro block of an HD signal obtained by conversion.

FIG. 8 is a diagram showing a configuration of a macroblock of the DVC standard (SD signal).

FIG. 9 is a diagram for explaining a super block of the DVC standard.

FIG. 10 is a diagram showing a data structure after formatting according to the DVC standard.

FIG. 11 is a diagram showing a sync block according to the DVC standard.

FIG. 12 is a diagram showing a data structure on a magnetic tape conforming to the DVC standard.

FIG. 13 is a diagram illustrating a configuration of a macroblock of the DVC standard (HD signal).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image signal switching processing part 2 Image signal recording / reproduction part 10 Address control circuit 15, 16 HD frame memory 17 Recording processing circuit 18 Reproduction processing 21 Blocking circuit 22 DCT operation circuit 23 Quantization circuit 24 Variable length encoding circuit 25 Auxiliary information Write circuit 26 Error correction coding circuit 27 Sync block synthesis recording modulation circuit

Claims (5)

[Claims] 1. A method comprising: a luminance signal and two color difference signals;
The ratio between the number of pixels of the luminance signal and the number of pixels of each of the two color difference signals is m: 1 (m is an integer of 2 or more),
A digital image signal recording apparatus for recording an image signal of a first definition, comprising a luminance signal and two color difference signals, wherein a ratio between the number of pixels of the luminance signal and the number of pixels of each of the two color difference signals is n. : 1 (n is an integer of 1 or more where n <m), and the first image is divided into s (an integer of 2 or more) by dividing the still image signal of the second definition higher than the first definition. And a recording unit that performs predetermined processing on the divided conversion signal and records the processed signal on a recording medium, wherein the recording unit includes a predetermined pixel. An image information compression unit that compresses image information by performing orthogonal transformation for each block, and each one predetermined pixel block of the two color difference signals and a corresponding predetermined pixel block of the m luminance signals; Macro consisting of The signal processing is performed in units of locks. The division conversion unit includes: n predetermined pixel blocks of a luminance signal constituting the image signal of the second definition; and one predetermined pixel block of two color difference signals. A digital image signal recording apparatus, comprising adding (mn) predetermined pixel blocks composed of dummy data to a block set composed of: 2. A method according to claim 1, wherein the ratio of the number of pixels of the luminance signal to the number of pixels of each of the two color difference signals is m:
1 and further dividing the still image signal of the second definition into t (integer of 2 or more) to convert it into the image signal of the first definition and outputting it as a thinned division conversion signal. 2. The digital image signal recording apparatus according to claim 1, further comprising a conversion unit, wherein the recording unit records the divided conversion signal or the thinned-out divided conversion signal on the recording medium. 3. The digital image signal recording apparatus according to claim 1, wherein the dummy data has the same value at least in a range of the predetermined pixel block. 4. It comprises a luminance signal and two color difference signals,
The ratio between the number of pixels of the luminance signal and the number of pixels of each of the two color difference signals is m: 1 (m is an integer of 2 or more),
A digital image signal recording / reproducing apparatus for recording / reproducing a first definition image signal, comprising: a luminance signal and two color difference signals, wherein a ratio of the number of pixels of the luminance signal to the number of pixels of each of the two color difference signals Is n: 1 (n is an integer of 1 or more where n <m), and the still image signal of the second definition higher than the first definition is divided into s (an integer of 2 or more) by the above-mentioned division. A division conversion unit that converts the image into a first definition image signal and outputs the image signal as a division conversion signal; a recording unit that performs predetermined processing on the division conversion signal and records the divided conversion signal on a recording medium; A reproducing unit that reproduces a signal, performs predetermined reproduction processing, and outputs the reproduced output signal; and a reproduction conversion unit that converts the reproduced output signal into the second definition still image signal and outputs the signal. , Orthogonal for each predetermined pixel block Macroblock comprising image information compression means for compressing image information by performing the conversion, and comprising one predetermined pixel block of each of the two color difference signals and corresponding m predetermined pixel blocks of the luminance signal The signal processing unit performs the signal processing. The division conversion unit includes: n predetermined pixel blocks of a luminance signal forming the image signal of the second definition; and one predetermined pixel block of two color difference signals. A digital image signal recording / reproducing apparatus characterized in that the macroblock is constructed by adding (mn) predetermined pixel blocks composed of dummy data to a block set composed of: 5. A system comprising a luminance signal and two color difference signals,
The ratio between the number of pixels of the luminance signal and the number of pixels of each of the two color difference signals is m: 1 (m is an integer of 2 or more),
A digital image signal recording apparatus for recording an image signal of a first definition, comprising three independent signals, wherein the ratio of the number of pixels of one signal to the number of pixels of each of the other two signals is n: 1. (N is an integer of 1 or more where n <m), and the first definition is obtained by dividing a still image signal of a second definition higher than the first definition by s (an integer of 2 or more). And a recording unit that performs predetermined processing on the divided conversion signal and records the processed signal on a recording medium, wherein the recording unit is provided for each predetermined pixel block. Image information compressing means for compressing image information by performing orthogonal transformation on each of the other two signals, one predetermined pixel block of the other two signals, and m corresponding predetermined pixel blocks of the one signal. Macro block consisting of The division and conversion means comprises: n predetermined pixel blocks of the one signal forming the second definition image signal; and one predetermined pixel of the other two signals. A digital image signal recording apparatus characterized in that the macroblock is constructed by adding (mn) predetermined pixel blocks composed of dummy data to a block set composed of blocks.