JPH1056023A - Semiconductor device - Google Patents

Abstract

(57) Abstract: A compound semiconductor heterojunction bipolar transistor having a high maximum oscillation frequency while maintaining a low base resistance of an external base layer and a low collector capacitance. After forming a compound semiconductor mixed crystal containing Al in a parasitic collector region, a single crystal external base layer is epitaxially grown and an oxide is formed by selective oxidation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an ultrahigh-speed compound semiconductor heterojunction bipolar transistor.

[0002]

2. Description of the Related Art A III-V compound semiconductor heterojunction bipolar transistor in which an insulating film is buried in a parasitic collector region below a base electrode to reduce the collector capacitance is disclosed in Solid State Electronics, Vol. 38 (1995), No. 1619. Page to page 1622 (Solid
State Electronics Vol. 38 (1995) pp. 1619
-1622), and its longitudinal sectional structure is shown in FIG.

[0003]

In the above prior art, after the insulating film 32 of SiO ₂ or the like is buried in the parasitic collector region, crystal growth of the layers 8 to 11 serving as the base and the emitter is performed. As a result, the external base layer on the film 32 becomes the polycrystalline semiconductor 33 and the base resistance is increased. As a result, there is a problem that the maximum oscillation frequency cannot be improved.

[0004]

According to the present invention, in order to solve the above-mentioned problems of the prior art, after forming a compound semiconductor mixed crystal containing Al in a parasitic collector region, crystal growth of a base layer and an emitter layer is performed. Thus, the external base layer is also made of a single crystal semiconductor, and after the mesa etching of the emitter and the base is performed, an oxide containing Al is formed in the parasitic collector region by selective oxidation.

According to the present invention, since the external base layer is a single crystal semiconductor, the base resistance is low, and the oxide containing Al has a low relative dielectric constant, so that the collector capacitance can be kept small. As a result, a compound semiconductor heterojunction bipolar transistor having a high maximum oscillation frequency and a semiconductor device having the same can be manufactured.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION

<Embodiment 1> An npn-type In according to a first embodiment of the present invention.
A GaP / GaAs heterojunction bipolar transistor and a method of manufacturing the same will be described with reference to FIGS.

As shown in the longitudinal sectional view of FIG. 1, an AlGaAs oxide 14 is buried in a parasitic collector region, and the collector capacitance is equivalent to that of the prior art. On the other hand, since the external base layer is made of the same single crystal p-type GaAs as the intrinsic base layer immediately below the emitter electrode, the external base resistance is about 1/10 of the conventional technique and the total base resistance is about 1/3 of the conventional technique. The maximum oscillation frequency was reduced to a value exceeding 100 GHz, which is about 1.7 times that of the prior art.

Hereinafter, a method of manufacturing the InGaP / GaAs heterojunction bipolar transistor shown in FIG. 1 will be described. First, a highly doped n-type GaAs layer (Si concentration: 5 × 10 ¹⁸ cm- ³ , film thickness: 1 μm) 2 was grown on a semi-insulating GaAs (100) substrate 1 at 580 ° C. by molecular beam epitaxy. Thereafter, the SiO _{2 is} formed by a chemical vapor deposition method.
A film (thickness: 0.5 μm) 3 was deposited, and the SiO ₂ film 3 was left only in the intrinsic region of the transistor by photolithography and anisotropic dry etching. After removing the photoresist, the highly doped n-type GaAs layer 2 is formed by dry etching.
Was etched by 0.4 μm, and the highly doped n-type GaAs layer 2 was etched by 0.1 μm by wet etching (see FIG. 2).

Thereafter, the sample was re-introduced into the molecular beam epitaxy apparatus, and the natural oxide film on the surface of the highly doped n-type GaAs layer 2 was removed at 600 ° C. Subsequently, highly doped n-type Ga
An undoped AlGaAs layer (AlAs) is formed on the surface of the As layer 2.
Molar ratio 0.5, film thickness 0.35 μm) 4 and undoped G
An aAs layer (thickness: 0.05 μm) 5 was grown at 500 ° C. by molecular beam epitaxy. The undoped GaAs layer 5 is a cap layer for preventing surface oxidation of the undoped AlGaAs layer 4. When growing the layers 4 and 5, the SiO ₂ film 3
A polycrystalline AlGaAs layer (AlAs molar ratio: 0.5, film thickness: about 0.35 μm) 6 and a polycrystalline GaAs layer (film thickness: about 0.05 μm) 7 were deposited thereon (see FIG. 3). Here, the reason why the film thickness is affixed is that the polycrystalline grain size is about 0.05 μm. When this sample is ultrasonically cleaned in a hydrofluoric acid aqueous solution, the SiO ₂ film 3, the polycrystalline AlGaAs layer 6, and the polycrystalline G
The aAs layer 7 was lifted off.

The sample was again introduced into the molecular beam epitaxy apparatus, and the native oxide film on the surface of the undoped GaAs layer 5 and the highly doped n-type GaAs layer 2 was removed at 600 ° C. Then, as shown in FIG. 4, a highly doped n-type GaAs layer (Si concentration 5 × 10 ¹⁸ cm ³ , thickness 0.05 μm) 8, n
Type GaAs layer (Si concentration 5 × 10 ¹⁶ cm- ³ , thickness 0.15)
μm) 9, highly doped p-type GaAs layer (Be concentration 4 × 10 ¹⁹
cm ~ ³ , thickness 0.05 μm) 10, n-type InGaP layer (In
P molar ratio 0.5, Si concentration 3 × 10 ¹⁷ cm- ³ , film thickness 0.05
μm) 11 and a highly doped n-type InGaAs layer (In
As molar ratio 0.6, Si concentration 4 × 10 ¹⁹ cm- ³ , film thickness 0.1
μm) 12 was epitaxially grown at 450 ° C. Here, the heavily doped n-type GaAs layer 8 is inserted for the purpose of reducing the regrowth interface resistance between the heavily doped n-type GaAs layer 2 and the n-type GaAs layer 9. The film thickness and impurity concentration were designed so that the region below the base layer was depleted.

Then, a WSi film (thickness 3) is formed on the entire surface of the sample.
00 nm) 13 was deposited by a sputtering method, and the WSi emitter electrode 13 was processed by photolithography and dry etching. Using the emitter electrode 13 as a mask, wet etching of the highly doped n-type InGaAs layer 12 is performed using a mixed solution of phosphoric acid, hydrogen peroxide and pure water, and the layers 11, 10, 9, 8, 5, and 4 are etched. Photolithography and wet etching (layer 11 is hydrochloric acid,
A mixture of pure water, layers 10, 9, 8, 5, and 4 are processed with a mixture of phosphoric acid, hydrogen peroxide, and pure water to form a highly doped n-type G
The etched surface of the aAs layer 2 was exposed. Further, a highly doped n-type GaAs layer 2 and a semi-insulating GaAs substrate 1
Was removed by photolithography and wet etching using a mixed solution of phosphoric acid, hydrogen peroxide and pure water (see FIG. 5).

As a result of heating the sample in the state of FIG. 5 at 350 ° C. for 5 hours in a nitrogen atmosphere containing 20% of oxygen, the undoped AlGaAs layer 4 becomes AlGaAs as shown in FIG.
It changed from the oxide layer 14 and the relative dielectric constant was also reduced from about 12 to about 3. At this time, it was confirmed by evaluation of the electrical characteristics and the optical characteristics that no change occurred in the other layers not containing Al.

Finally, as shown in FIG.
5 (Au (200 nm) / Pt (50 nm) / Ti (50 n
m) / Pt (30 nm)) and the collector electrode 17 (Au (2
00 nm) / AuGe (20 nm)) by a lift-off method, and annealing at 350 ° C. for 30 minutes to form a Pt alloy region 16 and an AuGe alloy region (not shown). Here, the base electrode 15 is made of n-type InGaP
The reason for the formation via the layer 11 is to suppress a reduction in current amplification factor due to surface recombination of the base layer 10.

According to the present invention, since the external base layer is a single-crystal semiconductor, the base resistance is as low as about 1/3 of the prior art, and the AlGaAs oxide layer 14 is formed of the conventional Si.
As in the case of the insulating film 32 of O ₂ or the like (see FIG. 13), the relative dielectric constant is low, so that the collector capacitance can be kept small. There is an effect that a semiconductor device including the semiconductor device can be manufactured. In this embodiment, only the molecular beam epitaxy is shown as a method for growing a semiconductor layer. Of course, a metal organic vapor phase epitaxy using an organic metal gas as a group III raw material or a gas such as arsine or phosphine as a group V raw material is used. Gas source molecular beam epitaxy may be used.

<Embodiment 2> An npn-type InP / InGaAs heterojunction bipolar transistor according to a second embodiment of the present invention and a method of manufacturing the same will be described with reference to FIGS.

As shown in the vertical sectional structural view of FIG. 7, an InAlAs oxide 29 is buried in the parasitic collector region, and the collector capacitance is equivalent to that of the prior art. On the other hand, since the external base layer is made of the same single crystal p-type InGaAs as the intrinsic base layer immediately below the emitter electrode, the external base resistance is about 1/10 of the prior art and the total base resistance is about 1/3 of the conventional art. The maximum oscillation frequency was reduced to a value exceeding 100 GHz, which is about 1.7 times that of the prior art.

A method of manufacturing the InP / InGaAs heterojunction bipolar transistor shown in FIG. 7 will be described below. First, on a semi-insulating InP (100) substrate 18, a highly doped n-type InGaAs layer (InAs molar ratio 0.5, S
An i concentration of 2 × 10 ¹⁹ cm to ³ and a film thickness of 1 μm) 19 was grown at 500 ° C. by a molecular beam epitaxy method. Thereafter, a SiO ₂ film (0.5 μm thick) 3 was deposited by a chemical vapor deposition method, and the SiO ₂ film 3 was left only in the intrinsic region of the transistor by photolithography and anisotropic dry etching. After removing the photoresist, the highly doped n-type GaAs layer 19 is etched by 0.4 μm by dry etching, and further highly doped n-type In
The GaAs layer 19 was etched by 0.1 μm (see FIG. 8).

Thereafter, the sample is re-introduced into the molecular beam epitaxy apparatus, and the highly doped n-type InGaAs layer 1 is formed at 550 ° C.
Nine natural oxide films on the surface were removed. Subsequently, highly doped n
Undoped InAlAs on the surface of the p-type InGaAs layer 19
A layer (AlAs molar ratio 0.5, thickness 0.35 μm) 20 and an undoped InGaAs layer (InAs molar ratio 0.5, thickness 0.05 μm) 21 were grown by molecular beam epitaxy at 500 ° C. The undoped InGaAs layer 21 is a cap layer for preventing surface oxidation of the undoped InAlAs layer 20. When the layers 20 and 21 are grown, the SiO ₂ film 3
A polycrystalline InAlAs layer (AlAs molar ratio 0.5,
A polycrystalline InGaAs layer (approximately 0.05 μm thick) 23 was deposited (see FIG. 9). Here, the term “approximately” added to the film thickness means that the polycrystalline particle size was 0.05 μm.
Because there is a degree. When this sample is subjected to ultrasonic cleaning in a hydrofluoric acid aqueous solution, the SiO ₂ film 3, the polycrystalline InAlAs layer 2
2, and the polycrystalline InGaAs layer 23 was lifted off.

The sample was introduced again into the molecular beam epitaxy apparatus, and the natural oxide film on the surface of the undoped InGaAs layer 21 and the highly doped n-type InGaAs layer 19 was removed at 550 ° C. Then, as shown in FIG.
Type InGaAs layer (InAs molar ratio 0.5, Si concentration 2 ×
10 ¹⁸ cm- ³ , thickness 0.05 μm) 24, n-type InGaAs
Layer (InAs molar ratio 0.5, Si concentration 1 × 10 ¹⁶ cm- ³ , thickness 0.15 μm) 25, highly doped p-type InGaAs layer (I
nAs molar ratio 0.5, Be concentration 4 × 10 ¹⁹ cm- ³ , film thickness 0.5.
05 μm) 26, n-type InP layer (Si concentration 3 × 10 ¹⁷ cm)
^-3 , thickness 0.1 μm) 27, and highly doped n-type InGa
As layer (InAs molar ratio 0.5, Si concentration 2 × 10 ¹⁹ cm)
³ and a film thickness of 0.1 μm) 28 were sequentially epitaxially grown at 450 ° C.

Here, the highly doped n-type GaAs layer 24 is inserted for the purpose of reducing the regrowth interface resistance between the highly doped n-type GaAs layer 21 and the n-type GaAs layer 25. The film thickness and impurity concentration of 24 were designed so that the region below the external base layer was depleted.

Thereafter, a WSi film (thickness 3) is formed on the entire surface of the sample.
00 nm) 13 was deposited by a sputtering method, and the WSi emitter electrode 13 was processed by photolithography and dry etching. Using the emitter electrode 13 as a mask, the highly doped n-type InGaAs layer 28 is wet-etched using a mixed solution of phosphoric acid, hydrogen peroxide and pure water, and the layers 27, 26, 25, 24, 21, 20 are etched. Photolithography and wet etching (layer 27
Is a mixture of hydrochloric acid and pure water, layers 26, 25, 24, 21,
0 is a mixed solution of phosphoric acid, hydrogen peroxide and pure water) to expose the etched surface of the highly doped n-type InGaAs layer 19. Further, the highly doped n-type InGaAs layer 19
A part of the semi-insulating InP substrate 18 was removed by photolithography and wet etching using a mixed solution of phosphoric acid, hydrogen peroxide and pure water (see FIG. 11).

The sample in the state shown in FIG. 11 was heated at 350 ° C. for 5 hours in a nitrogen atmosphere containing 20% of oxygen. As a result, the undoped InAlAs layer 20 was formed as shown in FIG.
lAs oxide layer 29 and the relative dielectric constant is about 12 to 3
Reduced to a degree. At this time, it was confirmed by evaluation of the electrical characteristics and the optical characteristics that no change occurred in the other layers not containing Al.

Finally, as shown in FIG.
0 (Au (200 nm) / Pt (50 nm) / Ti (50
nm)) and the collector electrode 31 (Au (200 nm)
/ Pt (50 nm) / Ti (50 nm)) by a lift-off method.

According to the present invention, since the external base layer is a single crystal semiconductor, the base resistance is as low as about 1/3 of the prior art, and the InAlAs oxide layer 29 is made of S
Since the relative dielectric constant is low as in the case of the insulating film 32 such as SiO ₂ (see FIG. 13), the collector capacitance can be kept small. As a result, there is an effect that a compound semiconductor heterojunction bipolar transistor having a maximum oscillation frequency as high as 1.7 times that of the related art and a semiconductor device including the same can be manufactured.

[0025]

According to the present invention, since the external base layer is a single crystal semiconductor, the base resistance is lower than that of the prior art, and
Since the oxide containing l has a low relative dielectric constant, the collector capacitance can be kept small. As a result, a compound semiconductor heterojunction bipolar transistor having a high maximum oscillation frequency and a semiconductor device including the same can be manufactured.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of an InGaP / GaAs heterojunction bipolar transistor according to the present invention.

FIG. 2 is a longitudinal sectional view showing a method for manufacturing an InGaP / GaAs heterojunction bipolar transistor according to the present invention.

FIG. 3 is a longitudinal sectional view showing a step following FIG. 2 in the method of manufacturing the InGaP / GaAs heterojunction bipolar transistor according to the present invention;

FIG. 4 is a longitudinal sectional view showing a step following FIG. 3 in the method of manufacturing the InGaP / GaAs heterojunction bipolar transistor according to the present invention;

FIG. 5 is a longitudinal sectional view showing a step following FIG. 4 in the method of manufacturing the InGaP / GaAs heterojunction bipolar transistor according to the present invention;

FIG. 6 is a longitudinal sectional view showing a step following FIG. 5 in the method of manufacturing the InGaP / GaAs heterojunction bipolar transistor according to the present invention;

FIG. 7 is a longitudinal sectional view of an InP / InGaAs heterojunction bipolar transistor according to the present invention.

FIG. 8 is a longitudinal sectional view showing a method for manufacturing an InP / InGaAs heterojunction bipolar transistor according to the present invention.

FIG. 9 is a longitudinal sectional view showing a step following FIG. 8 in the method of manufacturing the InP / InGaAs heterojunction bipolar transistor according to the present invention;

FIG. 10 is a longitudinal sectional view showing a step following FIG. 9 in the method of manufacturing the InP / InGaAs heterojunction bipolar transistor according to the present invention;

FIG. 11 is a longitudinal sectional view showing a step following FIG. 10 in the method of manufacturing the InP / InGaAs heterojunction bipolar transistor according to the present invention;

FIG. 12 is a longitudinal sectional view showing a step following FIG. 11 in the method of manufacturing the InP / InGaAs heterojunction bipolar transistor according to the present invention;

FIG. 13 is a longitudinal sectional view of a conventional InGaP / GaAs heterojunction bipolar transistor.

[Explanation of symbols]

1: Semi-insulating GaAs substrate, 2, 8: Highly doped n-type Ga
As, 3 ... SiO ₂ , 4 ... undoped AlGaAs, 5
... undoped GaAs, 6 ... polycrystalline AlGaAs, 7 ... polycrystalline GaAs, 9 ... n-type GaAs, 10 ... highly doped p-type GaAs, 11 ... n-type InGaP, 12, 19, 24,
28 ... heavily doped n-type InGaAs, 13 ... WSi electrode,
14 ... AlGaAs oxide, 15 ... Au / Pt / Ti /
Pt electrode, 16: Pt alloy region, 17: AuGe electrode, 18: semi-insulating InP substrate, 20: undoped In
AlAs, 21: Undoped InGaAs, 22: Polycrystalline InAlAs, 23: Polycrystalline InGaAs, 25 ... n
Type InGaAs, 26... Highly doped p-type InGaAs, 2
7 ... n-type InP, 29 ... InAlAs oxide, 30,3
1: Au / Pt / Ti electrode.

Claims (4)

[Claims] 1. A single crystal semiconductor substrate, a first layer formed on the substrate and having a desired shape and made of a first conductivity type compound single crystal semiconductor, and formed on the first layer, A second layer of a first conductivity type compound single crystal semiconductor having a desired shape; an insulating film formed on the first layer and surrounding the periphery of the second layer; A third layer formed of a compound single crystal semiconductor having a second conductivity type opposite to the first conductivity type and formed on the second layer; and a third layer formed on the insulating film and electrically connected to the third layer. A fourth layer formed of a compound single crystal semiconductor having the second conductivity type connected to the semiconductor layer and a compound single crystal semiconductor formed on the third layer and forming the third film, having a different forbidden band width. A fifth layer made of a compound single crystal semiconductor having the first conductivity type, the first layer, the fourth layer, and the like. Fine said fifth first electrode is connected to a layer of a semiconductor device characterized by comprising a heterojunction bipolar transistor having a second electrode and the third electrode. 2. The semiconductor device according to claim 1, wherein said fourth layer is an oxide containing Al. 3. The semiconductor device according to claim 2, wherein said third layer and said fifth layer are made of GaAs and InGaP, respectively. 4. The semiconductor device according to claim 2, wherein said third and fifth layers are made of InGaAs and InP, respectively.