JPH1075146A - Noise filter - Google Patents
Noise filterInfo
- Publication number
- JPH1075146A JPH1075146A JP24903396A JP24903396A JPH1075146A JP H1075146 A JPH1075146 A JP H1075146A JP 24903396 A JP24903396 A JP 24903396A JP 24903396 A JP24903396 A JP 24903396A JP H1075146 A JPH1075146 A JP H1075146A
- Authority
- JP
- Japan
- Prior art keywords
- pad
- layer
- noise
- noise filter
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000004020 conductor Substances 0.000 claims description 14
- 239000003990 capacitor Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Coils Or Transformers For Communication (AREA)
- Filters And Equalizers (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体基板上に形
成されたパッド等がノイズの影響を受けないようにする
ノイズフィルタに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise filter for preventing a pad or the like formed on a semiconductor substrate from being affected by noise.
【０００２】[0002]
【従来の技術および発明が解決しようとする課題】ＣＰ
Ｕなどの各種ＬＳＩは機能が複雑化する傾向にあり、そ
れに伴って、トランジスタ等の多数の回路素子を１チッ
プ内に実装する高密度実装技術と、実装された各素子を
高速に動作させる高周波技術について様々な研究開発が
行われてきた。2. Prior Art and Problems to be Solved by the Invention CP
Various LSIs such as U tend to have complicated functions. Accordingly, high-density mounting technology for mounting a large number of circuit elements such as transistors in one chip, and high-frequency mounting technology for operating each mounted element at high speed. Various research and developments have been conducted on technology.
【０００３】しかしながら、ＬＳＩの動作速度が速くな
ると、高周波ノイズが発生するおそれがあり、特に、半
導体基板上の実装密度が高いほどノイズの影響を受けや
すくなる。このため、従来は、半導体基板に形成された
パッドの近くにノイズフィルタを形成したり、ノイズの
影響を特に受けやすい回路素子を他の素子と離して形成
するなどの対策を行っていた。ところが、このようなノ
イズ対策は、半導体基板上の実装領域の一部を利用して
行うため、高密度実装を妨げる要因になっていた。However, when the operating speed of the LSI increases, high-frequency noise may be generated. In particular, the higher the mounting density on the semiconductor substrate, the more easily the noise is affected. For this reason, conventionally, measures such as forming a noise filter near a pad formed on a semiconductor substrate or forming a circuit element which is particularly susceptible to noise at a distance from other elements have been taken. However, since such a noise countermeasure is performed using a part of the mounting area on the semiconductor substrate, it has been a factor that hinders high-density mounting.
【０００４】本発明は、このような点に鑑みて創作され
たものであり、その目的は高密度実装を妨げることなく
確実にノイズを低減できるノイズフィルタを提供するこ
とにある。[0004] The present invention has been made in view of the above points, and an object of the present invention is to provide a noise filter which can surely reduce noise without hindering high-density mounting.
【０００５】[0005]
【課題を解決するための手段】上述した課題を解決する
ために、請求項１および２のノイズフィルタは、パッド
とパッド対向層の少なくとも一部を絶縁層を挟んで対向
配置する。これにより、パッドに印加される電圧に含ま
れるノイズ成分はパッド対向層を介して接地領域に導か
れる。In order to solve the above-mentioned problems, in the noise filter of the first and second aspects, at least a part of the pad and the pad facing layer are opposed to each other with an insulating layer interposed therebetween. Thus, a noise component included in the voltage applied to the pad is guided to the ground region via the pad facing layer.
【０００６】請求項３のノイズフィルタは、インダクタ
導体とパッド対向層とを絶縁層を介して対向配置する。
これにより、インダクタ導体がノイズの影響を受けなく
なる。According to a third aspect of the present invention, there is provided a noise filter in which an inductor conductor and a pad facing layer are opposed to each other via an insulating layer.
As a result, the inductor conductor is no longer affected by noise.
【０００７】[0007]
【発明の実施の形態】以下、本発明を適用したノイズフ
ィルタについて、図面を参照しながら具体的に説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a noise filter to which the present invention is applied will be specifically described with reference to the drawings.
【０００８】〔第１の実施形態〕図１は半導体基板１上
に形成された第１の実施形態のノイズフィルタの概略を
示す平面図、図２は図１のＡ−Ａ線の拡大断面図であ
る。これらの図に示すように、半導体基板１の表面に
は、ボンディングワイヤや配線パターンを接続するため
の矩形状のパッド２が形成され、このパッド２の下面側
には、絶縁層３を介してパッド対向層４が形成されてい
る。パッド２とパッド対向層４は対向配置されており、
また、パッド対向層４は、半導体基板１上に形成された
グラウンド層５と導通しており、パッド対向層４の下面
側には絶縁層６が形成されている。図１では、実線で示
すパッド２と点線で示すパッド対向層４をずらして図示
しているが、実際にはパッド２とパッド対向層４は絶縁
層３を挟んで上下に重なるように形成されている。[First Embodiment] FIG. 1 is a plan view schematically showing a noise filter of a first embodiment formed on a semiconductor substrate 1, and FIG. 2 is an enlarged cross-sectional view taken along line AA of FIG. It is. As shown in these figures, a rectangular pad 2 for connecting a bonding wire or a wiring pattern is formed on the surface of a semiconductor substrate 1, and on the lower surface side of the pad 2 via an insulating layer 3. A pad facing layer 4 is formed. The pad 2 and the pad facing layer 4 are arranged facing each other,
The pad opposing layer 4 is electrically connected to a ground layer 5 formed on the semiconductor substrate 1, and an insulating layer 6 is formed on the lower surface side of the pad opposing layer 4. In FIG. 1, the pad 2 indicated by a solid line and the pad opposing layer 4 indicated by a dotted line are shifted from each other. However, in practice, the pad 2 and the pad opposing layer 4 are formed so as to vertically overlap with the insulating layer 3 interposed therebetween. ing.
【０００９】なお、パッド２とパッド対向層４は必ずし
も同一形状である必要はなく、パッド２の一部の形状が
パッド対向層４と一致していればよい。The pad 2 and the pad opposing layer 4 do not necessarily have to have the same shape, and it is only necessary that a part of the pad 2 has the same shape as the pad opposing layer 4.
【００１０】半導体基板１には、例えばｎ型シリコン基
板（ｎ−Ｓｉ基板）やその他の半導体基板（例えばゲル
マニウムやアモルファスシリコン等の非晶質材料）が用
いられ、パッド２はアルミニウムや金等の金属薄膜で形
成される。As the semiconductor substrate 1, for example, an n-type silicon substrate (n-Si substrate) or another semiconductor substrate (for example, an amorphous material such as germanium or amorphous silicon) is used. It is formed of a metal thin film.
【００１１】なお、半導体基板１上には、パッド２の他
に、トランジスタ・ダイオード等の能動素子や、抵抗・
コンデンサ等の受動素子が実装されるが、図１では説明
を簡単にするためにパッド２のみを示している。また、
半導体基板１上には複数のパッドが形成されており、す
べてのパッドを図１のような構造にしてもよく、あるい
は一部のパッドのみを図１のような構造にしてもよい。On the semiconductor substrate 1, in addition to the pad 2, an active element such as a transistor or a diode,
Although passive elements such as capacitors are mounted, FIG. 1 shows only the pad 2 for simplicity of description. Also,
A plurality of pads are formed on the semiconductor substrate 1, and all the pads may have a structure as shown in FIG. 1, or only some of the pads may have a structure as shown in FIG.
【００１２】図３は、図１に示すノイズフィルタの等価
回路図である。図１に示すパッド２とパッド対向層４は
図３に示すコンデンサ７と等価であり、また図３に示す
抵抗８はパッド２に接続されるパターン２ａの抵抗分を
示している。このように、パッド２に対向させてパッド
対向層４を形成して、このパッド対向層４を接地するこ
とにより、図３に示すようなローパスフィルターを構成
でき、パッド２に印加される電圧に含まれる高周波ノイ
ズ成分、例えばスパイク成分を確実に除去することがで
きる。FIG. 3 is an equivalent circuit diagram of the noise filter shown in FIG. The pad 2 and the pad facing layer 4 shown in FIG. 1 are equivalent to the capacitor 7 shown in FIG. 3, and the resistor 8 shown in FIG. 3 represents the resistance of the pattern 2a connected to the pad 2. As described above, by forming the pad facing layer 4 so as to face the pad 2 and grounding the pad facing layer 4, a low-pass filter as shown in FIG. High frequency noise components, such as spike components, can be reliably removed.
【００１３】例えば、信号入力用のパッド２にノイズ成
分を含む電圧が印加された場合、ノイズ成分はパッド対
向層４を介してグラウンド層５に導かれるため、パッド
２自体はノイズの影響を受けなくなる。For example, when a voltage including a noise component is applied to the signal input pad 2, the noise component is guided to the ground layer 5 via the pad facing layer 4, and the pad 2 itself is affected by the noise. Disappears.
【００１４】また、信号出力用のパッド２の場合、その
パッド２に接続される前段の回路の出力がノイズ成分を
含んでいても、そのノイズ成分はパッド対向層４を介し
てグラウンド層５に導かれるため、パッド２に接続され
る後段の回路はノイズの影響を受けなくなる。In the case of the signal output pad 2, even if the output of the circuit at the preceding stage connected to the pad 2 includes a noise component, the noise component is transmitted to the ground layer 5 via the pad facing layer 4. Therefore, the subsequent circuit connected to the pad 2 is not affected by noise.
【００１５】また、図１に示すノイズフィルタは、パッ
ド２とほぼ同形状のパッド対向層４を半導体基板１の内
部に形成するだけの簡易な構造であるため、半導体基板
１上の実装領域をほとんど占有しなくて済み、高密度実
装が可能となる。Further, the noise filter shown in FIG. 1 has a simple structure in which the pad facing layer 4 having substantially the same shape as the pad 2 is formed inside the semiconductor substrate 1, so that the mounting area on the semiconductor substrate 1 is reduced. Almost no occupancy, and high-density mounting is possible.
【００１６】〔第２の実施形態〕半導体基板１上に薄膜
形成技術を利用して渦巻き形状のインダクタ導体を形成
し、このインダクタ導体をインダクタ素子として利用す
る半導体回路が知られており、この種のインダクタ素子
に一体にノイズフィルタを形成することも可能である。[Second Embodiment] There is known a semiconductor circuit in which a spiral inductor conductor is formed on a semiconductor substrate 1 by using a thin film forming technique and the inductor conductor is used as an inductor element. It is also possible to form a noise filter integrally with the inductor element.
【００１７】図４は第２の実施形態のノイズフィルタの
概略を示す平面図、図５は図４のＢ−Ｂ線の拡大断面図
である。これらの図に示すように、半導体基板１の表面
には、パッド２を中心として渦巻き状にインダクタ導体
１１が形成され、このインダクタ導体１１の下面側に
は、絶縁層３を介して渦巻き状のパッド対向層４′が形
成されている。このパッド対向層４′は、半導体基板１
に形成されたグラウンド層５と導通している。インダク
タ導体１１は、アルミニウムや金等の金属薄膜、あるい
はポリシリコン等の半導体材料で形成され、パッド２と
パッド対向層４′はアルミニウムや金等の金属薄膜で形
成されている。FIG. 4 is a plan view schematically showing a noise filter according to a second embodiment, and FIG. 5 is an enlarged sectional view taken along line BB of FIG. As shown in these figures, a spiral inductor conductor 11 is formed on the surface of the semiconductor substrate 1 with the pad 2 as a center. On the lower surface side of the inductor conductor 11, a spiral inductor A pad facing layer 4 'is formed. This pad facing layer 4 ′ is
Is electrically connected to the ground layer 5 formed at the same time. The inductor conductor 11 is formed of a metal thin film such as aluminum or gold or a semiconductor material such as polysilicon, and the pad 2 and the pad facing layer 4 'are formed of a metal thin film such as aluminum or gold.
【００１８】なお、図４では、実線で示すインダクタ導
体１１と点線で示すパッド対向層４′をずらして図示し
ているが、実際にはインダクタ導体１１とパッド対向層
４′は絶縁層３を挟んで上下に重なるように形成されて
いる。In FIG. 4, the inductor conductor 11 shown by a solid line and the pad facing layer 4 'shown by a dotted line are shifted from each other. It is formed so as to be sandwiched vertically.
【００１９】また、図４では、インダクタ導体１１とパ
ッド対向層４′の双方の形状がほぼ同一である例を示し
ているが、インダクタ導体１１の一部の形状がパッド対
向層４′の形状と一致していればよい。FIG. 4 shows an example in which both the shape of the inductor conductor 11 and the shape of the pad facing layer 4 'are substantially the same, but the shape of a part of the inductor conductor 11 is the same as the shape of the pad facing layer 4'. It only needs to match.
【００２０】図６は、図４に示すノイズフィルタの等価
回路図である。図４に示すインダクタ導体１１とパッド
対向層４′により図６に示すインダクタ１２が形成さ
れ、インダクタ導体１１とパッド対向層４′の全長にわ
たって複数のコンデンサ１３が形成される。これによ
り、分布定数型のＬＣ素子が得られる。図６に示すよう
なＬＣ素子は、Ｌ成分とＣ成分とが分布定数的に存在し
ているものであり、広帯域にわたって良好な減衰特性が
得られるため、半導体基板１上のノイズを確実に除去す
ることができる。FIG. 6 is an equivalent circuit diagram of the noise filter shown in FIG. The inductor 12 shown in FIG. 6 is formed by the inductor conductor 11 and the pad facing layer 4 'shown in FIG. 4, and a plurality of capacitors 13 are formed over the entire length of the inductor conductor 11 and the pad facing layer 4'. Thus, a distributed constant type LC element is obtained. In the LC element as shown in FIG. 6, the L component and the C component are present in the form of a distributed constant, and good attenuation characteristics can be obtained over a wide band, so that noise on the semiconductor substrate 1 is reliably removed. can do.
【００２１】また、図４に示すノイズフィルタは、半導
体基板１上に形成された渦巻き形状のインダクタ素子に
一体に形成することができるため、半導体基板１上に個
別にノイズフィルタを形成する必要がなくなり、高密度
実装が可能になる。Further, since the noise filter shown in FIG. 4 can be formed integrally with the spiral inductor element formed on the semiconductor substrate 1, it is necessary to separately form the noise filter on the semiconductor substrate 1. And high-density mounting becomes possible.
【００２２】[0022]
【発明の効果】以上詳細に説明したように、本発明によ
れば、パッドと対向させてパッド対向層を形成し、この
パッド対向層を接地領域と導通させるため、パッドに印
加される電圧がノイズ成分を含んでいても、このノイズ
成分をパッド対向層を介して接地領域に導くことがで
き、パッドに印加される電圧がノイズの影響を受けなく
なる。また、パッドの下面側にパッドと同形状のパッド
対向層を形成するだけでノイズフィルタを構成できるた
め、半導体基板上の実装領域をほとんど占有しなくて済
み、高密度実装が可能となる。As described above in detail, according to the present invention, a pad facing layer is formed so as to face a pad, and the pad facing layer is electrically connected to a ground region. Even if a noise component is included, the noise component can be guided to the ground region via the pad facing layer, and the voltage applied to the pad is not affected by the noise. In addition, since the noise filter can be configured only by forming the pad facing layer having the same shape as the pad on the lower surface side of the pad, the mounting area on the semiconductor substrate is hardly occupied, and high-density mounting is possible.
【図１】半導体基板上に形成された第１の実施形態のノ
イズフィルタの概略を示す平面図である。FIG. 1 is a plan view schematically showing a noise filter according to a first embodiment formed on a semiconductor substrate.
【図２】図１のＡ−Ａ線の拡大断面図である。FIG. 2 is an enlarged cross-sectional view taken along line AA of FIG.
【図３】図１に示すノイズフィルタの等価回路図であ
る。FIG. 3 is an equivalent circuit diagram of the noise filter shown in FIG.
【図４】第２の実施形態のノイズフィルタの概略を示す
平面図である。FIG. 4 is a plan view schematically illustrating a noise filter according to a second embodiment.
【図５】図４のＢ−Ｂ線の拡大断面図である。FIG. 5 is an enlarged sectional view taken along line BB of FIG. 4;
【図６】図４に示すノイズフィルタの等価回路図であ
る。6 is an equivalent circuit diagram of the noise filter shown in FIG.
１ 半導体基板 ２ パッド ３、６ 絶縁層 ４ パッド対向層 ５ グラウンド層 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Pad 3, 6 Insulating layer 4 Pad facing layer 5 Ground layer
Claims (3)
向配置され、前記半導体基板に形成された接地領域と導
通するパッド対向層とを備えることを特徴とするノイズ
フィルタ。A pad formed on a semiconductor substrate, an insulating layer formed on a lower surface of the pad, and at least a portion of the pad interposed with the insulating layer interposed therebetween, and formed on the semiconductor substrate. A noise filter comprising: a pad facing layer that is electrically connected to a ground region.
記パッド対向層を介して前記接地領域に導かれるよう
に、前記パッド対向層の位置および形状を設定すること
を特徴とするノイズフィルタ。2. The position and the shape of the pad opposing layer according to claim 1, wherein a noise component included in a voltage applied to the pad is guided to the ground region via the pad opposing layer. A noise filter, characterized in that:
ンダクタ導体を備え、前記パッド対向層の少なくとも一
部分は前記インダクタ導体に対向配置されることを特徴
とするノイズフィルタ。3. The device according to claim 1, further comprising a spirally formed inductor conductor including at least a part of the pad, wherein at least a part of the pad facing layer is arranged to face the inductor conductor. Noise filter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24903396A JP3742692B2 (en) | 1996-08-30 | 1996-08-30 | Noise filter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24903396A JP3742692B2 (en) | 1996-08-30 | 1996-08-30 | Noise filter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1075146A true JPH1075146A (en) | 1998-03-17 |
| JP3742692B2 JP3742692B2 (en) | 2006-02-08 |
Family
ID=17187013
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24903396A Expired - Fee Related JP3742692B2 (en) | 1996-08-30 | 1996-08-30 | Noise filter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3742692B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005091499A1 (en) * | 2004-03-18 | 2005-09-29 | Elmec Corporation | Delay line |
| CN114121409A (en) * | 2020-08-26 | 2022-03-01 | 株式会社村田制作所 | Inductor component |
-
1996
- 1996-08-30 JP JP24903396A patent/JP3742692B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005091499A1 (en) * | 2004-03-18 | 2005-09-29 | Elmec Corporation | Delay line |
| CN114121409A (en) * | 2020-08-26 | 2022-03-01 | 株式会社村田制作所 | Inductor component |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3742692B2 (en) | 2006-02-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5523622A (en) | Semiconductor integrated device having parallel signal lines | |
| US6215171B1 (en) | IC module | |
| KR20000071342A (en) | Semiconductor device | |
| US5585664A (en) | Semiconductor integrated circuit device | |
| US4782381A (en) | Chip carrier | |
| US4646126A (en) | Semiconductor device | |
| JP2674553B2 (en) | Semiconductor device | |
| JPH1075146A (en) | Noise filter | |
| JP3234666B2 (en) | Semiconductor integrated circuit device | |
| EP0262493A2 (en) | Electronic package with distributed decoupling capacitors | |
| JP2697547B2 (en) | Semiconductor integrated circuit device | |
| JP2690709B2 (en) | Semiconductor device | |
| JP2004064016A (en) | Semiconductor chip | |
| JP3896838B2 (en) | Semiconductor device | |
| JPH05283611A (en) | Semiconductor device | |
| JPH0590427A (en) | Semiconductor integrated circuit device | |
| JPH05211279A (en) | Hybrid integrated circuit | |
| JPH0653414A (en) | Microwave integrated circuit | |
| JPH0575012A (en) | Semiconductor integrated circuit | |
| JPS63184358A (en) | Semiconductor integrated circuit | |
| JP3283709B2 (en) | Connection method of bypass capacitor | |
| JP3302810B2 (en) | Semiconductor device | |
| JPH05251635A (en) | Semiconductor device | |
| JPH02210858A (en) | Semiconductor device | |
| JPS605055B2 (en) | semiconductor equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040812 |
|
| A131 | Notification of reasons for refusal |
Effective date: 20041102 Free format text: JAPANESE INTERMEDIATE CODE: A131 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20041224 |
|
| A131 | Notification of reasons for refusal |
Effective date: 20050201 Free format text: JAPANESE INTERMEDIATE CODE: A131 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050330 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20050607 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050805 |
|
| A911 | Transfer of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20050810 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Effective date: 20051108 Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Effective date: 20051114 Free format text: JAPANESE INTERMEDIATE CODE: A61 |
|
| R150 | Certificate of patent (=grant) or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 4 Free format text: PAYMENT UNTIL: 20091118 |
|
| LAPS | Cancellation because of no payment of annual fees |