JPH1075181A5 - - Google Patents

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Publication number
JPH1075181A5
JPH1075181A5 JP1997136722A JP13672297A JPH1075181A5 JP H1075181 A5 JPH1075181 A5 JP H1075181A5 JP 1997136722 A JP1997136722 A JP 1997136722A JP 13672297 A JP13672297 A JP 13672297A JP H1075181 A5 JPH1075181 A5 JP H1075181A5
Authority
JP
Japan
Prior art keywords
input data
codeword
register
coefficient
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1997136722A
Other languages
Japanese (ja)
Other versions
JPH1075181A (en
Filing date
Publication date
Priority claimed from US08/666,964 external-priority patent/US5818364A/en
Application filed filed Critical
Publication of JPH1075181A publication Critical patent/JPH1075181A/en
Publication of JPH1075181A5 publication Critical patent/JPH1075181A5/ja
Pending legal-status Critical Current

Links

Claims (3)

最大長「Q」の符号語−係数対を有する符号化データ・ストリームを復号する方法であって、1. A method of decoding an encoded data stream having codeword-coefficient pairs of maximal length "Q", comprising the steps of:
データ容量が少なくともQの2倍であるデータ・レジスタに、係数とハフマン符号語の第1の対を備えるいくつかのビットを有する第1の入力データ・セットを記憶するステップと、storing a first input data set having a number of bits comprising first pairs of coefficients and Huffman code words in a data register having a data capacity at least twice Q;
ストリームの第2の係数−ハフマン符号語対を備える次の逐次入力データ・セットをシフト・レジスタで受け取るステップと、receiving a next sequential input data set comprising a second coefficient-Huffman codeword pair of the stream in a shift register;
前記次の逐次入力データ・セットを前記第1のデータ・セット内のビットの数だけ右シフトするステップとright shifting said next sequential input data set by the number of bits in said first data set;
、前記第1の入力データ・セットと前記次の逐次入力データ・セットの論理和を実行し、結果をデータ・レジスタに入れるステップと、, performing a logical OR of said first input data set and said next sequential input data set and placing the result in a data register;
データ・レジスタの最上位ビットN個を復号済み係数値として抽出し、データ・レジスタの次の上位ビットM個を符号語として抽出するステップとextracting the N most significant bits of the data register as a decoded coefficient value and the M next most significant bits of the data register as a codeword;
を含む方法。A method comprising:
可変長符号化されたビット列符号語−係数対のための入力データ・ストリーム復号器であって、前記入力データ・ストリームは、バイト境界符号と、ヘッダ/マーカ符号とをさらに含み、1. An input data stream decoder for variable length coded bit string codeword-coefficient pairs, the input data stream further comprising byte boundary codes and header/marker codes;
前記符号語−係数対を、逐次、受信して復号する復号手段であって、a decoding means for sequentially receiving and decoding the codeword-coefficient pairs,
少なくとも2つの入力データ・セットを受信する入力シフト手段と、input shifting means for receiving at least two input data sets;
現在の入力データ・セットと、それに続く次の入力データ・セットとの論理和演算を実行する手段と、means for performing a logical OR operation on the current input data set and the next input data set that follows it;
前記現在の入力データ・セットと、それに続く次の入力データ・セットとの論理和演算の結果として得られたビット列を記憶およびシフトする手段と、means for storing and shifting a bit string resulting from the logical OR operation of the current input data set and the subsequent next input data set;
前記符号語−係数対を、符号語と係数とに分離する手段と、means for separating the codeword-coefficient pairs into codewords and coefficients;
前記符号語を検査して、これから復号されたアドレスを抽出する手段と、means for examining said codeword and extracting therefrom a decoded address;
現在の符号語の長さと、符号化された係数の長さとの和だけ、前記記憶およびシフトする手段をシフトさせる手段とmeans for shifting said storing and shifting means by the sum of the length of the current codeword and the length of the coded coefficient;
を有するデコード手段decoding means having
を有する入力データ・ストリーム・デコーダ。An input data stream decoder having:
最大ビット長「Q」のワードを有するJPEG/MPEG圧縮されたデータ・ビット・ストリームを復号する方法であって、1. A method for decoding a JPEG/MPEG compressed data bit stream having words of maximum bit length "Q", comprising:
少なくともQの2倍のビット容量を有する入力レジスタに、復号されようとする連続した入力データ・ワード受信するステップと、receiving successive input data words to be decoded in an input register having a bit capacity of at least twice Q;
連続した入力データ・ワードそれぞれを、前記入力レジスタ内のそれに先行する入力データ・ワードに付加するステップと、appending each successive input data word to the input data word preceding it in said input register;
新たなデータ・ワードそれぞれを、前記レジスタ内で、有効なデータ・ビットの数だけ右シフトするステップであって、前記有効なデータ・ビットの数は、先行する入力ワードのビット数であるステップと、right-shifting each new data word in said register by a number of valid data bits, said number of valid data bits being the number of bits in the previous input word;
2つの連続する入力データ・ワードの論理和演算を実行するステップと、performing a logical OR operation on two consecutive input data words;
動作データ・レジスタ内に、前記論理和演算の結果を記憶するステップと、storing the result of said OR operation in an operational data register;
前記動作データ・レジスタを、先行する符号語−係数対内のビット数に基づいて左シフトし、動作データ・レジスタの最上位ビットN個を、復号された係数の値として、続く最上位ビットM個を、ハフマン符号語として抽出するステップとshifting the operational data register left based on the number of bits in the preceding codeword-coefficient pair, and extracting the N most significant bits of the operational data register as the value of the decoded coefficient and the M most significant bits as the Huffman codeword;
を有する方法。A method having the following.
JP9136722A 1996-06-19 1997-05-27 Huffman decoder Pending JPH1075181A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/666,964 US5818364A (en) 1996-06-19 1996-06-19 High bit-rate huffman decoding
US666,964 1996-06-19

Publications (2)

Publication Number Publication Date
JPH1075181A JPH1075181A (en) 1998-03-17
JPH1075181A5 true JPH1075181A5 (en) 2005-02-17

Family

ID=24676264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9136722A Pending JPH1075181A (en) 1996-06-19 1997-05-27 Huffman decoder

Country Status (6)

Country Link
US (1) US5818364A (en)
EP (1) EP0814614B1 (en)
JP (1) JPH1075181A (en)
DE (1) DE69732271T2 (en)
ES (1) ES2231844T3 (en)
SG (1) SG73441A1 (en)

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