JPH1079491A5 - - Google Patents

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Publication number
JPH1079491A5
JPH1079491A5 JP1997185264A JP18526497A JPH1079491A5 JP H1079491 A5 JPH1079491 A5 JP H1079491A5 JP 1997185264 A JP1997185264 A JP 1997185264A JP 18526497 A JP18526497 A JP 18526497A JP H1079491 A5 JPH1079491 A5 JP H1079491A5
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Prior art keywords
insulating film
semiconductor device
film
forming
bit line
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Pending
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JP1997185264A
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Japanese (ja)
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JPH1079491A (en
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Priority to JP9185264A priority Critical patent/JPH1079491A/en
Priority claimed from JP9185264A external-priority patent/JPH1079491A/en
Publication of JPH1079491A publication Critical patent/JPH1079491A/en
Publication of JPH1079491A5 publication Critical patent/JPH1079491A5/ja
Pending legal-status Critical Current

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Claims (30)

半導体基板上にメモリセル領域と周辺回路領域とを有する半導体装置において、
前記基板中に形成された一対の不純物拡散領域と、該基板表面に形成されたゲート電極とを含む転送トランジスタと、
該ゲート電極の上面および側面を覆う第１の絶縁膜と、
該第１の絶縁膜を覆って前記基板上に形成された第２の絶縁膜と、
該第２の絶縁膜を貫通して、前記一対の不純物拡散領域に達する一対のコンタクトホールと、
該一対のコンタクトホールの一方内に充填され、前記一対の不純物拡散領域の一方に接続された導電プラグと、
前記導電プラグを覆って該第２の絶縁膜上に形成され、前記一対のコンタクトホールの他方の上に第１の開口を有する第３の絶縁膜と、
前記第３の絶縁膜上に形成され、前記第１の開口と前記一対のコンタクトホールの他方を介して前記一対の不純物拡散領域の他方に接続されたビット線と、
該ビット線の上面および側面を覆う第４の絶縁膜と、
前記ビット線の側面を覆う第４の絶縁膜に整合して前記第３の絶縁膜に形成された第２の開口と、
前記第２の開口を介して前記導電プラグと電気的に接続され、前記第３、第４の絶縁膜によって該ビット線から絶縁され、ビット線上方に延在して形成された蓄積電極と、
該蓄積電極表面に形成された誘電体膜と、
該誘電体膜表面に形成された対向電極と、
を有する半導体装置。 In a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate,
a transfer transistor including a pair of impurity diffusion regions formed in the substrate and a gate electrode formed on the surface of the substrate;
a first insulating film covering an upper surface and a side surface of the gate electrode;
a second insulating film formed on the substrate to cover the first insulating film;
a pair of contact holes that penetrate the second insulating film and reach the pair of impurity diffusion regions;
a conductive plug filled in one of the pair of contact holes and connected to one of the pair of impurity diffusion regions;
a third insulating film formed on the second insulating film to cover the conductive plug, the third insulating film having a first opening above the other of the pair of contact holes;
a bit line formed on the third insulating film and connected to the other of the pair of impurity diffusion regions through the first opening and the other of the pair of contact holes;
a fourth insulating film covering an upper surface and a side surface of the bit line;
a second opening formed in the third insulating film in alignment with a fourth insulating film covering a side surface of the bit line;
a storage electrode electrically connected to the conductive plug through the second opening, insulated from the bit line by the third and fourth insulating films, and formed to extend above the bit line;
a dielectric film formed on the surface of the storage electrode;
a counter electrode formed on the surface of the dielectric film;
A semiconductor device having: 前記第２の絶縁膜が、エッチング特性の異なる２層以上の絶縁膜積層からなる下層とその上に形成された上層とを含む請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said second insulating film includes a lower layer made of a laminate of two or more insulating films having different etching characteristics and an upper layer formed thereon. 前記絶縁膜積層が酸化膜とその上に形成された窒化膜とを含む請求項２記載の半導体装置。3. The semiconductor device according to claim 2, wherein said insulating film stack includes an oxide film and a nitride film formed thereon. 前記第２の絶縁膜の上層が、エッチング特性の異なる２層以上の絶縁膜積層を含む請求項２記載の半導体装置。3. The semiconductor device according to claim 2, wherein the upper layer of said second insulating film includes a laminate of two or more insulating film layers having different etching characteristics. 前記上層の絶縁膜積層がＢＰＳＧ層とその上に形成されたコンフォーマルな層を含む請求項４記載の半導体装置。5. The semiconductor device according to claim 4, wherein said upper insulating film stack comprises a BPSG layer and a conformal layer formed thereon. 前記コンフォーマルな層が窒化膜である請求項５記載の半導体装置。6. The semiconductor device according to claim 5, wherein said conformal layer is a nitride film. 前記コンフォーマルな層が高温酸化膜である請求項５記載の半導体装置。6. The semiconductor device of claim 5, wherein said conformal layer is a high temperature oxide film. 前記第１の絶縁膜が、前記ゲート電極の上面を覆う下層と、前記ゲート電極の側面を覆う上層とを含む請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the first insulating film includes a lower layer covering an upper surface of the gate electrode and an upper layer covering a side surface of the gate electrode. 前記第１の絶縁膜の下層が酸化膜と酸化窒化膜との積層であり、前記第１の絶縁膜の上層が酸化膜である請求項８記載の半導体装置。9. The semiconductor device according to claim 8, wherein the lower layer of said first insulating film is a laminate of an oxide film and an oxynitride film, and the upper layer of said first insulating film is an oxide film. 前記第４の絶縁膜が前記ビット線の上面を覆う下層と前記ビット線の側面を覆う上層とを含む請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said fourth insulating film includes a lower layer covering an upper surface of said bit line and an upper layer covering a side surface of said bit line. 前記第４の絶縁膜の下層が酸化膜と酸化窒化膜との積層であり、前記第４の絶縁膜の上層が酸化膜である請求項１０記載の半導体装置。11. The semiconductor device according to claim 10, wherein a lower layer of said fourth insulating film is a laminate of an oxide film and an oxynitride film, and an upper layer of said fourth insulating film is an oxide film. 前記第２の絶縁膜の上面が略平坦である請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the upper surface of said second insulating film is substantially flat. 前記メモリセル領域のコンタクトホールと同様のコンタクトホールが、前記周辺回路領域にも形成されている請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein a contact hole similar to the contact hole in the memory cell region is also formed in the peripheral circuit region. 前記ビット線を複数備え、該ビット線とビット線との間隔が、前記一対のコンタクトホールの一方のホール径よりも狭い請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the bit lines are plural, and the distance between the bit lines is narrower than the diameter of one of the pair of contact holes. 前記ビット線が前記他のコンタクトホール内に充填された他の導電プラグと、前記第３の絶縁膜と他の導電プラグ上に形成された配線層とを含む請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said bit line includes another conductive plug filled in said another contact hole, and a wiring layer formed on said third insulating film and the other conductive plug. 前記ビット線が前記他のコンタクトホール内面を覆い、前記第３の絶縁膜上に延在する導電層を含む請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said bit line includes a conductive layer covering the inner surface of said other contact hole and extending onto said third insulating film. さらに、前記ビット線および第４の絶縁膜を覆って、前記基板上に形成され、ほぼ平坦な表面を有する第５の絶縁膜を有する請求項１記載の半導体装置。2. The semiconductor device according to claim 1, further comprising a fifth insulating film formed on said substrate to cover said bit line and said fourth insulating film, said fifth insulating film having a substantially flat surface. 前記第５の絶縁膜が、エッチング特性が異なる２層以上の絶縁膜積層を有する下層とその上に形成された上層とを含む請求項１７記載の半導体装置。18. The semiconductor device according to claim 17, wherein the fifth insulating film includes a lower layer having a laminate of two or more insulating film layers having different etching characteristics and an upper layer formed thereon. 前記第５の絶縁膜の絶縁膜積層が、コンフォーマルな酸化膜と窒化膜とを含む請求項１８記載の半導体装置。20. The semiconductor device of claim 18, wherein the fifth insulating film stack includes a conformal oxide film and a nitride film. 前記第４の絶縁膜が、前記ビット線上に形成され、エッチング特性の異なる２層以上の絶縁層の積層を有する請求項１８記載の半導体装置。19. The semiconductor device according to claim 18, wherein the fourth insulating film is formed on the bit line and has a laminate of two or more insulating layers having different etching characteristics. 半導体基板上にメモリセル領域と周辺回路領域とを有する半導体装置の製造方法において、
前記基板上に、一対の不純物拡散領域と、ゲート電極とを含む転送トランジスタを形成する工程と、
該ゲート電極の上面および側面を覆う第１の絶縁膜を形成する工程と、
該第１の絶縁膜および前記転送トランジスタを覆う第２の絶縁膜を形成する工程と、
該第２の絶縁膜を貫通して、前記一対の不純物拡散領域の少なくとも一方に達するコンタクトホールを形成する工程と、
該コンタクトホール内に導電層を充填し、蓄積電極の接続用導電プラグを形成する工程と、
前記導電プラグを覆い、該第２の絶縁膜上に第３の絶縁膜を形成する工程と、
前記第３の絶縁膜上にビット線を形成する工程と、
該ビット線の上面および側面を覆う第４の絶縁膜を形成する工程と、
前記第４の絶縁膜に整合させて前記導電プラグ上で前記第３の絶縁膜に開口を形成する工程と、
前記導電プラグと電気的に接続する蓄積電極を形成する工程と、
該蓄積電極表面に誘電体膜を形成する工程と、
該誘電体膜表面に対向電極を形成する工程と、
を有する半導体装置の製造方法。 A method for manufacturing a semiconductor device having a memory cell region and a peripheral circuit region on a semiconductor substrate, comprising:
forming a transfer transistor including a pair of impurity diffusion regions and a gate electrode on the substrate;
forming a first insulating film covering an upper surface and side surfaces of the gate electrode;
forming a second insulating film covering the first insulating film and the transfer transistor;
forming a contact hole that penetrates the second insulating film and reaches at least one of the pair of impurity diffusion regions;
a step of filling the contact hole with a conductive layer to form a conductive plug for connecting the storage electrode;
forming a third insulating film on the second insulating film to cover the conductive plug;
forming a bit line on the third insulating film;
forming a fourth insulating film covering an upper surface and a side surface of the bit line;
forming an opening in the third insulating film over the conductive plug in alignment with the fourth insulating film;
forming a storage electrode electrically connected to the conductive plug;
forming a dielectric film on the surface of the storage electrode;
forming a counter electrode on the surface of the dielectric film;
A method for manufacturing a semiconductor device having the above structure. 前記第２の絶縁膜が前記第１の絶縁膜を覆って基板表面上に形成された下層絶縁膜とその上の上層絶縁膜を含む請求項２１記載の半導体装置の製造方法。22. The method for manufacturing a semiconductor device according to claim 21, wherein the second insulating film includes a lower insulating film formed on the surface of the substrate to cover the first insulating film, and an upper insulating film thereon. 前記下層絶縁膜が窒化シリコン膜を含む請求項２２記載の半導体装置の製造方法。23. The method for manufacturing a semiconductor device according to claim 22, wherein the lower insulating film includes a silicon nitride film. 前記コンタクトホールを形成する工程が前記下層絶縁膜をエッチングストッパとして利用する工程を含む請求項２２記載の半導体装置の製造方法。23. The method for manufacturing a semiconductor device according to claim 22, wherein the step of forming the contact holes includes a step of using the lower insulating film as an etching stopper. 前記第２の絶縁膜を形成する工程が前記上層絶縁膜を平坦化する工程を含む請求項２２記載の半導体装置の製造方法。23. The method for manufacturing a semiconductor device according to claim 22, wherein the step of forming the second insulating film includes the step of planarizing the upper insulating film. 前記下層絶縁膜が窒化シリコン膜を含み、前記上層絶縁膜が不純物添加酸化シリコン膜を含む請求項２５記載の半導体装置の製造方法。26. The method for manufacturing a semiconductor device according to claim 25, wherein the lower insulating film includes a silicon nitride film, and the upper insulating film includes an impurity-doped silicon oxide film. 前記コンタクトホールを形成する工程が、前記メモリセル領域と前記周辺回路領域とに同時にコンタクトホールを形成する請求項２１記載の半導体装置の製造方法。22. The method for manufacturing a semiconductor device according to claim 21, wherein the step of forming contact holes comprises simultaneously forming contact holes in the memory cell region and the peripheral circuit region. 前記第２の絶縁膜の下層絶縁膜を形成後、前記周辺回路領域の該第２の絶縁膜の下層絶縁膜を選択的に除去する工程を有する請求項２２記載の半導体装置の製造方法。23. The method for manufacturing a semiconductor device according to claim 22, further comprising the step of selectively removing the insulating film underlying the second insulating film in the peripheral circuit region after forming the insulating film underlying the second insulating film. 前記転送トランジスタを形成する工程が、導電層上に反射防止膜を形成する工程と、その後に該導電層のパターニングを行う工程と、次いで、該反射防止膜を除去する工程とを有する請求項２１記載の半導体装置の製造方法。22. The method for manufacturing a semiconductor device according to claim 21, wherein the step of forming the transfer transistor comprises the steps of forming an anti-reflective film on a conductive layer, thereafter patterning the conductive layer, and then removing the anti-reflective film. 前記反射防止膜を除去する工程が、周辺回路領域の該反射防止膜を選択的に除去する工程を有する請求項２９記載の半導体装置の製造方法。30. The method for manufacturing a semiconductor device according to claim 29, wherein the step of removing the anti-reflection film comprises the step of selectively removing the anti-reflection film in a peripheral circuit region.
JP9185264A 1996-07-10 1997-07-10 Semiconductor device and manufacturing method thereof Pending JPH1079491A (en)

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JP9185264A JPH1079491A (en) 1996-07-10 1997-07-10 Semiconductor device and manufacturing method thereof

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Application Number Priority Date Filing Date Title
JP18105796 1996-07-10
JP8-181057 1996-10-07
JP9185264A JPH1079491A (en) 1996-07-10 1997-07-10 Semiconductor device and manufacturing method thereof

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JP2005100899A Division JP2005244251A (en) 1996-07-10 2005-03-31 Semiconductor device and manufacturing method thereof
JP2005100900A Division JP2005252283A (en) 1996-07-10 2005-03-31 Semiconductor device and manufacturing method thereof
JP2005100898A Division JP4391438B2 (en) 1996-07-10 2005-03-31 Manufacturing method of semiconductor device

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JPH1079491A JPH1079491A (en) 1998-03-24
JPH1079491A5 true JPH1079491A5 (en) 2005-09-15

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KR100275752B1 (en) * 1998-11-18 2000-12-15 윤종용 Manufacturing method of concave capacitor having adhesion spacers
TW472384B (en) * 1999-06-17 2002-01-11 Fujitsu Ltd Semiconductor device and method of manufacturing the same
KR100334393B1 (en) * 1999-06-30 2002-05-03 박종섭 Fabricating method for semiconductor device
US6458649B1 (en) * 1999-07-22 2002-10-01 Micron Technology, Inc. Methods of forming capacitor-over-bit line memory cells
JP5775018B2 (en) * 1999-10-13 2015-09-09 ソニー株式会社 Semiconductor device
KR100351897B1 (en) * 1999-12-31 2002-09-12 주식회사 하이닉스반도체 Method for fabricating semiconductor device
JP3957945B2 (en) 2000-03-31 2007-08-15 富士通株式会社 Semiconductor device and manufacturing method thereof
KR100402943B1 (en) * 2000-06-19 2003-10-30 주식회사 하이닉스반도체 High dielectric capacitor and a method of manufacturing the same
JP2003152104A (en) * 2001-11-14 2003-05-23 Fujitsu Ltd Semiconductor device and manufacturing method thereof
JP2007258747A (en) * 2002-08-30 2007-10-04 Matsushita Electric Ind Co Ltd Semiconductor device
JP2005260082A (en) * 2004-03-12 2005-09-22 Toshiba Corp Magnetic random access memory
JP5076168B2 (en) * 2009-12-07 2012-11-21 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device

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