JPH1084064A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent peeling of a laminated plating layer at the time of wire bonding to an inner lead having a laminated plating structure. SOLUTION: A semiconductor chip 3 is bonded on a die pad portion 2 of a lead frame 1 having a laminated plating layer of nickel, palladium and gold. Thereafter, a thin metal wire 6 made of a gold wire is pressed on the electrode pad 4 of the semiconductor chip 3 with a load of about 60 (g) via the bonding tool 20 while applying an ultrasonic wave having an output of about 55 (mW). First
A bonding step is performed. Next, the thin metal wire 6 is pressed against the inner lead portion 5 with a load of 150 to 250 (g), and an ultrasonic wave having an output of 0 to 20 (mW) is applied to perform a second bonding step. In the second bonding step, a large pressing load and a small amount of ultrasonic output perform bonding suitable for the characteristics of the laminated plating layer, and strong bonding can be performed in a short time without peeling of the gold plating layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of preventing peeling of a lead plating layer in a laminated plating layer in a wire bonding step and ensuring reliability of connection between wire lead frames, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Recently, copper (C) has been used as a lead frame.
u), a nickel (Ni) plating is applied as a base plating, a palladium (Pd) plating is applied thereon, and then a gold (A) is applied thereon.
u) A plate having a laminated plating layer has been developed.

A conventional semiconductor device using a lead frame plated with a nickel / palladium / gold laminate as described above will be described below.

FIG. 9 is a sectional view showing the structure of a conventional semiconductor device. As shown in FIG. 9, a conventional semiconductor device is:
A lead frame having a die pad portion, an inner lead portion, and an outer lead portion;
A semiconductor chip 3 bonded and mounted on a die pad portion 2 by an adhesive such as silver paste, and the semiconductor chip 3
And a thin metal wire 6 for connecting the electrode 4 to the bonding area 5 a of the inner lead portion 5 of the lead frame 1. The surrounding area of the semiconductor chip 3, that is, the area including the die pad portion 2, the inner lead portion 5, the semiconductor chip 3, and the thin metal wire 6 is sealed with the sealing resin 7, and the outer side from the sealing resin 7. The protruding outer lead portion 8 of the lead frame 1 is formed so as to be suitable for connection to an external device, thereby forming a semiconductor device.

Next, a conventional method for manufacturing a semiconductor device will be described. 10 to 13 are cross-sectional views showing the steps of manufacturing a conventional semiconductor device.

First, as shown in FIG. 10, a semiconductor chip 3 is bonded onto a die pad portion 2 of a lead frame 1 using an adhesive such as a silver paste (die bonding step).

Next, as shown in FIG. 11, the electrodes 4 of the semiconductor chip 3 mounted on the die pad portion 2 and the inner lead portions 5 of the lead frame 1 are electrically connected by thin metal wires 6 (wire bonding step). ). In this step, when a gold wire is used as the thin metal wire, a method called a nail head bonding method is usually used. That is, a wire bonder having a bonding tool 20 called a capillary is used, and as a first bonding step, the metal thin wire 6 having a ball-shaped tip is pressed onto the electrode 4 of the semiconductor chip 3 and connected. Then, successively as a second bonding step, a thin metal wire 6 is formed in the bonding region 5a of the inner lead portion 5.
Press to connect. By these two bonding steps, the electrode 4 of the semiconductor chip 3 and the bonding area 5a of the inner lead portion 5 are electrically connected via the thin metal wire 6.

Here, in the wire bonding step, the first bonding step is to reduce the ultrasonic output to 55
(MW) and a pressing load of 60 (g).
The connection is made under the conditions of 0 (mW) and a pressing load of 100 (g), and the diameter of the thin metal wire 6 is generally about 25 to 35 μm.

Next, as shown in FIG. 12, after the wire bonding step is completed, a region including the die pad portion 2, the inner lead portion 5, the semiconductor chip 3, and the fine metal wires 6 is sealed with a sealing resin 7. . In this step, the lead frame 1 on which the semiconductor chip 3 is mounted is placed in a mold, and is performed by transfer molding.

[0010] Finally, as shown in FIG.
The semiconductor device is completed by molding the outer lead portion 8 of the lead frame 1 protruding outward from the semiconductor device.

[0011]

However, the semiconductor device manufactured by the above-mentioned conventional manufacturing process has the following problems.

FIGS. 14A and 14B are an enlarged sectional view and a perspective view showing the vicinity of the bonding region 5a of the inner lead 5 of the conventional semiconductor device. As shown in FIG. 1, the lead frame 1 is configured such that a nickel plating layer 10, a palladium plating layer 11, and a gold plating layer 12 are formed on a copper body 9. In addition,
The thickness of each of the nickel plating layer 10, the palladium plating layer 11, and the gold plating layer 12 is 0.5 (μm).
m), 0.03 (μm), and 0.002 (μm).

As shown in FIGS. 1A and 1B, a gold plating layer is formed around the tip 6a of the inner lead 5, which is cut by pressing the thin metal wire 6 with the bonding tool 20 in the bonding area 5a. It was observed that the peeled region 13 including 12 was formed in a half ring shape. The peeled area 13 may reach the nickel plating layer 10 or the base body 9 without remaining in the palladium plating layer 11. When the peeled area 13 is formed, not only the nickel plating layer is corroded and the wire connection strength is deteriorated, but also the peeled plated material adheres to the bonding tool 20 of the wire bonder, and the next wire bonding step (the next wire bonding step) is performed. 1 bonding process)
This caused wire bond defects such as deformation of the ball at the tip.

Therefore, as a result of pursuing a mechanism of generating the peeling region 13 in the second bonding step, the second bonding step is performed by applying ultrasonic waves in the same manner as in the first bonding step, and moreover, in comparison with the first bonding step. It was presumed that this was due to the application of high power ultrasonic waves. In other words, in the current wire bonding process, in order to ensure high speed (mass production) and reliability of the connection portion, the application of ultrasonic waves and a load and the heating are performed, and a strong connection is instantaneously performed. Has become indispensable. At present, the thickness of the gold plating layer is made as thin as possible (about 0.002 μm) in order to reduce the manufacturing cost. When applying an ultrasonic wave to a lead frame having such a structure with a wire bonder and connecting the electrode of the semiconductor chip and the inner lead part with a thin metal wire, the vibration of the ultrasonic wave is sufficiently absorbed in the thin gold plating layer It was presumed that cracks were generated at the boundary between the gold plating layer and the palladium plating layer, particularly at the outer peripheral portion of the region pressed by the bonding tool, and the peeling occurred.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems. In the wire bonding step for a lead frame having a laminated plating structure in which the uppermost layer is made of a soft material such as a gold plating layer, the uppermost layer is formed. An object of the present invention is to provide a structure of a semiconductor device capable of firmly connecting a wire and a lead frame with high efficiency without peeling and a method of manufacturing the same.

[0016]

In order to solve the above-mentioned problem of peeling of the plating layer, the inventors of the present invention have proposed that the plating layer is peeled off by the ultrasonic power (mW) of the bonding tool at the time of wire bonding, and in particular, gold or the like is peeled off. We have found that soft plating materials are susceptible.

Therefore, the means taken by the present invention to achieve the above object is to provide a structure in which the plating layer in the bonding area of the inner lead portion can absorb the ultrasonic wave, without using the ultrasonic wave, or without using the ultrasonic wave output. Is made extremely small, and a method of connecting the thin metal wire and the inner lead portion is performed. Specifically, means for a semiconductor device described in claims 1 to 3 and means for a method for manufacturing a semiconductor device described in claims 4 to 14 are provided.

According to the present invention, there is provided a semiconductor device having a semiconductor chip having an electrode pad,
A lead frame having at least an inner lead portion and an outer lead portion, the lead frame including a main body made of metal and a laminated plating layer formed on the main body layer and having an uppermost layer made of a soft material; and an electrode pad of the semiconductor chip. And a fine metal wire connecting the inner lead portion,
The thickness of the uppermost layer of the laminated plating layer in a region of the inner lead portion to which the thin metal wire is connected is greater than the thickness of the uppermost layer in another region.

Accordingly, since the uppermost layer of the laminated plating layer in the region of the inner lead portion to which the fine metal wire is connected is formed thicker, even if an ultrasonic output is applied in the wire bonding step, the uppermost layer vibrates. Is absorbed and the uppermost layer does not peel off.

According to a second aspect of the present invention, in the first aspect, it is preferable that the uppermost layer of the laminated plating layer of the inner lead portion and the fine metal wire are made of the same material.

Thus, since the thin metal wire and the uppermost layer of the laminated plating layer are made of the same soft material, the function of absorbing the vibration of the ultrasonic wave is increased and the structure is easy to bond.

According to a third aspect of the present invention, in the first or second aspect, the main body of the inner lead portion is formed of a copper plate, and the laminated plating layer of the inner lead portion is formed of a nickel plating layer, a palladium plating layer and It is preferable that gold plating layers are sequentially laminated and the fine metal wire is made of a material mainly containing gold.

Thus, a structure in which a peeling region can be prevented from being generated in the inner lead portion having the palladium plating layer having poor corrosion property.

The first method of manufacturing a semiconductor device according to the present invention comprises:
5. A step of preparing a semiconductor chip having an electrode pad and an inner lead portion formed by applying a laminated plating layer whose uppermost layer is made of a soft material on a main body made of metal, as described in claim 4. And a step of preparing a lead frame having an outer lead portion, and a step of joining the thin metal wire and the electrode pad while applying a load and ultrasonic waves in a state where the tip of the thin metal wire is applied to the electrode pad of the semiconductor chip. (1) a second bonding step of connecting the thin metal wire and the inner lead portion by applying a load without applying an ultrasonic wave in a state where another portion of the thin metal wire is applied to the inner lead portion; And a process.

According to this method, in the second bonding step, the two are connected only by the pressing load without applying an ultrasonic wave between the fine metal wire and the inner lead portion. Without giving birth
Strong bonding can be performed in a short time.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor chip having an electrode pad; Preparing a lead frame having an inner lead portion and an outer lead portion formed by applying a laminated plating layer composed of: a load and ultrasonic waves in a state where the tip of a fine metal wire is applied to the electrode pad of the semiconductor chip; A first bonding step of joining the thin metal wire and the electrode pad while applying a pressure, and applying a larger pressing load and a second pressing force than the first bonding step in a state where another portion of the thin metal wire is applied to the inner lead portion. A second bonding step of applying an ultrasonic wave having an output smaller than that of the first bonding step to connect the thin metal wire to the inner lead portion. .

According to this method, since the ultrasonic output in the second bonding step is extremely small, the ultrasonic output having a higher output than in the first bonding step as in the conventional method for manufacturing a semiconductor device is applied. It is possible to prevent peeling in the uppermost layer of the laminated plating layer.

According to a sixth aspect of the present invention, in the fifth aspect, the first bonding step is performed by setting an ultrasonic output to about 55 (mW) and a pressing load to about 60 (g). 2 bonding process, the ultrasonic output is 0 to
The pressure is preferably set to 20 (mW) and the pressing load is set to 150 to 250 (g).

According to a seventh aspect of the present invention, in the fourth or fifth aspect, in the first and second bonding steps, a thin metal wire made of the same material as the uppermost layer of the laminated plating layer is used. Is preferred.

According to an eighth aspect of the present invention, in the fourth or fifth aspect, in the step of preparing the lead frame, a nickel plating layer, a palladium plating layer, and a gold plating layer are sequentially laminated on a main body made of a copper plate. It is preferable to use a thin metal wire composed of a material containing gold as a main component in the first and second bonding steps.

As described in claim 9, in claim 4, 5, 6, 7, or 8, the second bonding step is preferably performed at a temperature of 150 to 300 (° C.).

According to a tenth aspect, in the fourth, fifth, sixth, seventh, eighth or ninth aspects, in the step of preparing the lead frame, the thin metal wire of the inner lead portion is connected. The thickness of the uppermost layer of the laminated plating layer in one region may be larger than the thickness of the uppermost layer in another region.

According to this method, even if an ultrasonic wave is applied to the connection between the inner lead portion and the thin metal wire in the second bonding step, the vibration caused by the ultrasonic wave is absorbed by the uppermost layer of the laminated plating layer, and peeling occurs. Can be prevented.

According to a third method of manufacturing a semiconductor device of the present invention,
As claimed in claim 11, a step of preparing a semiconductor chip having an electrode pad and a step of performing a multilayer plating in which a nickel plating layer, a palladium plating layer and a gold plating layer are sequentially laminated on a metal body. Preparing a lead frame having an inner lead portion and an outer lead portion formed by applying a load to the electrode pad of the semiconductor chip while applying the tip of a thin metal wire made of a material mainly composed of gold to the electrode pad. A first bonding step of bonding the thin metal wire and the electrode pad while applying ultrasonic waves, and a pressing load of 150 to 250 (g) in a state where another portion of the thin metal wire is applied to the inner lead portion. When,
A second bonding step of applying an ultrasonic wave having an output of 0 to 20 (mW) to connect the thin metal wire and the inner lead portion.

According to this method, since the ultrasonic output in the second bonding step is extremely small, the gold plating layer, which is the uppermost layer of the laminated plating layer, is peeled off to expose the corrosive palladium plating layer, and further, the nickel plating layer thereunder is exposed. Wire bonding is performed without exposing the metal constituting the layer or the main body of the lead frame. In addition, by pressing with such a large load, it is possible to perform bonding suitable for the characteristics of the entire laminated plating layer of the nickel plating layer, the palladium plating layer, and the gold plating layer, and to obtain a large bonding strength in a short time. And a highly reliable semiconductor device can be manufactured.

According to a twelfth aspect, in the eleventh aspect, after the first bonding step and the second bonding step, the semiconductor chip, the thin metal wires, and the inner lead portions are sealed with a resin. The method further includes a step.

According to this method, the inner lead portion housed in a resin-sealed package having a low manufacturing cost and easily corroded by moisture contained in the sealing resin has
Corrosion or the like resulting from the generation of a peeled region can be prevented. Therefore, an inexpensive and highly reliable semiconductor device can be obtained.

According to a thirteenth aspect, in the eleventh or twelfth aspect, the second bonding step is preferably performed at a temperature of 150 to 300 (° C.).

According to this method, the second bonding step is performed at a relatively low heating temperature suitable for the characteristics of the entire laminated plating layer including the nickel plating layer, the palladium plating layer, and the gold plating layer. It can be done in time.

According to a fourteenth aspect, in the eleventh or thirteenth aspect, in the second bonding step, the output of the ultrasonic wave can be set to zero.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) First, a first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view illustrating the configuration of the semiconductor device according to the present embodiment.

As shown in FIG. 1, in the semiconductor device of this embodiment, a semiconductor chip 3 is bonded and mounted on a die pad portion 2 of a lead frame 1 with an adhesive such as silver paste.
The electrodes 4 of the semiconductor chip 3 and the inner lead portions 5 of the lead frame 1 are electrically connected by thin metal wires 6. The semiconductor chip 3, the thin metal wires 6, and the inner lead portions 5 of the lead frame 1 are sealed with a sealing resin 7, and the outer lead portions 8 of the lead frame 1 projecting outward from the sealing resin 7 are formed. Thus, a semiconductor device is configured.

Here, the feature of the semiconductor device of the present embodiment is that the thickness of the plating layer in the bonding region 5a of the inner lead portion 5 of the lead frame 1 where the thin metal wire 6 is bonded in the wire bonding step is increased. That is the point. Hereinafter, this characteristic portion will be described.

FIG. 2 is a cross-sectional view showing a connection state between the inner lead portion 5 and the thin metal wire 6 in the vicinity of the bonding region 5a of the inner lead portion 5. As shown in FIG. 1, a lead frame 1 of the present embodiment includes a main body 9 made of a copper plate and a nickel plating layer 1 formed on the main body 9.
0, and each of the palladium plating layer 11 and the gold plating layer 12. Then, the bonding region 5a of the inner lead portion 5 of the lead frame 1
The thickness of the gold plating layer 12 is formed thicker than the other regions. For example, while the thickness in the other region of the gold plating layer 12 is about 0.002 (μm),
The thickness in the bonding region 5a is 0.03 (μm)
It is about. With this configuration, the electrode 4 of the semiconductor chip 3
When the inner lead portion 5 and the inner lead portion 5 are connected to each other by the thin metal wire 6, the outermost gold plating layer 12 is applied to the bonding area 5 a of the inner lead portion 5 even when the ultrasonic power of the bonding tool of the wire bonder is applied. Since it is thick, the vibration of the ultrasonic wave is absorbed to some extent and the gold plating layer 1
2 does not occur, or only the very surface layer of the gold plating layer 12 is removed. Therefore, in the wire bonding step, the lower palladium plating layer 11 and the nickel plating layer 10 are not exposed, so that deterioration of the wire connection strength due to peeling of the outermost layer can be prevented.

In the present embodiment, the thicknesses of the nickel plating layer 10 and the palladium plating layer 11 are 0.5 (μm) and 0.03 (μm), respectively. It is not limited. In the present embodiment, the thickness of the gold plating layer 12 is 0.002 (μm) except for the bonding region 5a, and the thickness of the bonding region 5a is 0.03 (μm). It is not something to be done.

(Second Embodiment) Next, a method of manufacturing a semiconductor device according to a second embodiment will be described. FIG. 3-
FIG. 6 is a cross-sectional view illustrating a manufacturing process of the semiconductor device of the present embodiment.

First, in the step shown in FIG. 3, a lead frame 1 having a die pad portion 2, an inner lead portion 5, and an outer lead portion 8 is prepared. Although the detailed cross-sectional state is not shown, the lead frame 1 has substantially the same structure as that shown in FIG. 2 of the first embodiment, and a nickel plating Each plating layer of a layer, a palladium plating layer, and a gold plating layer is provided. However, in this embodiment, the gold plating layer, which is the uppermost layer, has a substantially uniform thickness over the entire surface, and the gold plating layer in the bonding region 5a is not particularly thickly plated. The thicknesses of the nickel plating layer, palladium plating layer, and gold plating layer are 0.5 (μm), 0.03 (μm),
Then, the semiconductor chip 3 is bonded to the die pad portion 2 of the lead frame 1 having such a configuration using an adhesive such as a silver paste.

Next, in the step shown in FIG. 4, the electrode 4 of the semiconductor chip 3 mounted on the die pad portion 2 and the inner lead portion 5 of the lead frame 1 are connected to a thin metal wire 6 made of a gold wire.
To make electrical connection. This step is performed by a nail head bonding method using a wire bonder (not shown) having a bonding tool 20 called a capillary similarly to the above-described conventional wire bonding step. The diameter of the thin metal wire 6 is about 25 to 35 μm. In general, the bonding step includes a first bonding step of connecting one end of the thin metal wire 6 to the electrode 4 of the semiconductor chip 3 and a second bonding step of connecting the other end of the thin metal wire 6 to the inner lead portion 5 of the lead frame 1. Process.

In the first bonding step, the tip (generally in the form of a ball) of the fine metal wire 6 is applied to the electrode 4 of the semiconductor chip 3 by applying a ultrasonic wave by the bonding tool 20 to a load of 60 (g). ) Is pressed with a load of about) to join the thin metal wire 6 and the semiconductor chip 3.

In the second bonding step, a part of the thin metal wire 6 whose tip is connected to the electrode 4 of the semiconductor chip 3 is pressed by the bonding tool 20 onto the bonding area 5 a of the inner lead portion 5. At this time, the load is set to about 200 (g) and a load larger than the load in the first bonding step is applied while the ultrasonic wave is not applied or the output is suppressed to a small output of 20 (mW) or less even if it is applied. This is a feature of the semiconductor device manufacturing method according to the present embodiment. Then, by the pressing force and the heating, the thin metal wire 6 is joined to the inner lead portion 5 and the thin metal wire 6 is cut at the edge of the bonding tool 20.

Next, in the step shown in FIG. 5, after each of the above wire bonding steps is completed, the semiconductor chip 3
Then, the thin metal wire 6 and the die pad portion 2 and the inner lead portion 5 of the lead frame 1 are sealed with the sealing resin 7. In this step, the lead frame 1 on which the semiconductor chip 3 is mounted is placed in a mold, and is performed by transfer molding. Thereafter, a portion of the lead frame 1 outside the sealing resin 7 is cut, and the outer lead portion 8 is cut.
Disconnect from

Finally, in the step shown in FIG. 6, an outer lead portion 8 projecting outward from the sealing resin 7 is formed, thereby completing the semiconductor device.

As described above, in the manufacturing process of the semiconductor device of this embodiment, the ultrasonic output is set to 55 (mW) and the pressing load is set to 60 (g) in the first bonding step, and the ultrasonic output is set to 60 (g) in the second bonding step. The wire bonding process is performed under the condition that the sound wave output is 0 to 20 (mW) and the pressing load is about 200 (g), which is significantly different from the conventional wire bonding condition, thereby preventing the plating layer on the lead frame 1 from peeling off. can do. In particular, when the thin metal wire 6 and the outermost plating layer of the lead frame 1 are made of the same material and a soft material, the bonding strength between the thin metal wire and the inner lead portion is further increased.

FIGS. 7A and 7B are diagrams showing a comparison between the ultrasonic output and the load of the bonding tool during wire bonding between the conventional and this embodiment. FIG. 7 (a)
7 shows conditions in the conventional method, and FIG. 7B shows conditions in the present embodiment.

As described above, in the first bonding step, that is, in the step of bonding the semiconductor chip and the thin metal wire, the conditions in the present embodiment are the same as those in the conventional method, but the second bonding step, that is, in the step of bonding the lead frame. In the step of bonding with a thin metal wire, the ultrasonic output is set to be not more than one fifth of the conventional one, and the load is set to about twice. The ultrasonic power in the second bonding step may not be 0 (mW). For example, 10
Even if it is about (mW) or very close to 0 (mW), if it is 20 (mW) or less, bonding can be performed without peeling off the uppermost gold plating layer.

Here, the second bonding between the fine metal wire 6 and the inner lead portion 5 can be performed by the method of the present embodiment without forming the peeled region 13 shown in FIGS. Consider why the process can be performed. When performing wire bonding, the ultrasonic power causes an action of sliding the thin metal wire against the connected object, and the load and heating generate an action of thermocompression bonding the thin metal wire and the connected object. Normal heating temperature is 200
(° C.). By performing the bonding process under such a combination of conditions, the time required for one bonding is 5 (msec), and the time required for completing the entire bonding process is about 15 (msec), and the high-speed bonding is performed. The steps can be performed. However, the reason why the second bonding step of this embodiment can perform strong bonding in a short time of 15 (msec) without causing peeling of the uppermost layer of the laminated plating layer, has not been sufficiently clarified. However, the present invention reveals that the empirical fact that such a large load and relatively low-temperature heating conditions are well compatible with the characteristics of the entire nickel / palladium / gold laminated plating layer is well understood. I have. The following empirical facts have been confirmed as incidental items.

For example, when the ultrasonic power in the second bonding step is set to 0 (mW) and the temperature is set to about 250 (° C.), the pressing load can be made smaller than the above 200 (g). When the ultrasonic power is set to 20 (mW) and the temperature is set to about 180 (° C.), it is preferable to increase the pressing load to 200 (g) or more. The higher the temperature, the shorter the bonding time.

Here, a summary of the bonding conditions obtained by experiments performed in the course of the present invention is as follows. It is preferable that the ultrasonic power is not applied or even if it is applied, the power is 0 to 20 (mW), and the pressing load is The heating temperature is preferably in the range of 150 to 250 (g), and the heating temperature is preferably in the range of 150 to 300 ° C. However, a gold wire having a diameter of about 25 to 35 μm is used for the thin metal wire, and the laminated plating layer is composed of three layers of nickel / palladium / gold having the above-described thickness.

FIGS. 8A and 8B show a second bonding step in which the ultrasonic power is set to 0 (mW) and the load is set to 200.
It is sectional drawing and perspective view in the vicinity of the bonding area 5a of the inner lead when wire bonding is performed as (g). As shown in FIG. 14, around the bonding area 5a bonded by the method of this embodiment, FIG.
There is no ring-shaped peeling region 13 as shown in (a) and (b). That is, the distal end portion 6a of the thin metal wire 6 is connected without the outermost gold plating layer 12 of the inner lead portion 5 of the lead frame 1 coming off.
Of course, there is no exposure of copper constituting the main body 9 and no exposure or peeling of the nickel plating layer 10 and the palladium plating layer 11. Thereby, since the plating layer does not peel off, the wire connection strength can be stabilized. Further, since the plating layer is not peeled off, there is no adhesion of the material constituting the plating layer to the bonding tool, and the abnormality of the shape of the ball formed at the tip of the fine metal wire in the next bonding step, ie, the first bonding step, occurs. Nor.

Although illustration of the embodiment is omitted, the second embodiment
In the method of manufacturing the semiconductor device according to the embodiment, the thickness of the gold plating layer 12 of the lead frame 1 in the bonding region 5a of the inner lead portion 5 is made larger than other regions, and the second in the wire bonding process is performed.
By setting the ultrasonic output of the bonding step (bonding of the fine metal wire on the inner lead portion) to 0 to 20 (mW), the wire is prevented while exposing the lower plating layer due to peeling of the gold plating layer 12. Bonding can be performed, and an effect of stabilizing connection strength can be exhibited.

The uppermost layer of the laminated plating layer is made of a soft material, particularly the same material as the thin metal wire, even if the structure of the laminated plating layer is not necessarily composed of three layers of nickel / palladium / gold as in this embodiment. If it is constituted by the above, the effect of the present invention can be exhibited. In that case, even if the value of the ultrasonic power of the bonding tool of the wire bonder is extremely small, the thin metal wire and the softener constituting the uppermost layer of the plating layer are joined in a very short time by the pressing load, and the uppermost layer Structure is not destroyed. Therefore, highly reliable wire bonding can be performed while preventing peeling of the lead frame having the laminated plating structure in the wire bonding step.

[0062]

According to the present invention, there is provided a semiconductor device in which electrodes of a semiconductor chip and inner lead portions of a lead frame having a laminated plating layer are connected by thin metal wires. Since the thickness of the outermost layer of the laminated plating layer in the bonding area for connection with the fine wire is made thicker than the other areas, even when ultrasonic waves are applied to the connection part via a bonding tool at the time of wire bonding, The lower layer and the main body of the laminated plating layer are not exposed, and the deterioration of the wire connection strength due to the peeling of the outermost layer of the laminated plating layer can be prevented.

Claim 4 and Claims 7 to 1 cited therefor
According to No. 0, in a semiconductor device in which an electrode of a semiconductor chip and an inner lead portion of a lead frame having a laminated plating layer are connected by a thin metal wire, in a second bonding step of connecting the thin metal wire and the inner lead portion. Since the metal wiring is connected to the inner lead part only by pressing load without applying ultrasonic waves, it is possible to reliably prevent peeling of the uppermost layer of the laminated plating layer of the inner lead part due to application of ultrasonic waves. In addition, the connection strength between the thin metal wires and the inner lead portions can be increased, and the reliability of the manufactured semiconductor device can be improved.

Claim 5 and Claims 6 to 1 cited therefor
According to No. 0, in a semiconductor device in which an electrode of a semiconductor chip and an inner lead portion of a lead frame having a laminated plating layer are connected by a thin metal wire, in a second bonding step of connecting the thin metal wire and the inner lead portion, Since an ultrasonic wave having a lower output than that of the first bonding step is applied, it is possible to prevent the occurrence of a peeling region in the uppermost layer of the laminated plating layer, which occurred when applying an ultrasonic wave larger than that of the first bonding step. However, the connection strength between the thin metal wire and the inner lead portion can be increased, and the reliability of the manufactured semiconductor device can be improved.

According to the present invention, the electrode of the semiconductor chip is connected to the inner lead portion of the lead frame having a laminated plating layer formed by sequentially laminating nickel, palladium and gold by a thin metal wire. In the semiconductor device, in the second bonding step for connecting the thin metal wire and the inner lead portion, the semiconductor device is pressed with a load of 150 to 250 (g) and applies an ultrasonic wave having an output of 0 to 20 (mW). Therefore, it is possible to perform bonding that is extremely suitable for the characteristics of the laminated plating layer of palladium and gold, and to perform strong and highly reliable wire bonding without peeling off at the uppermost layer of the laminated plating layer. .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to a first embodiment.

FIG. 2 is an enlarged cross-sectional view showing the vicinity of a bonding region of an inner lead portion in the semiconductor device according to the first embodiment.

FIG. 3 is a cross-sectional view illustrating a die bonding step in the manufacturing steps of the semiconductor device according to the second embodiment.

FIG. 4 is a cross-sectional view showing a wire bonding step in the manufacturing steps of the semiconductor device according to the second embodiment.

FIG. 5 is a cross-sectional view showing a resin sealing step in the manufacturing steps of the semiconductor device according to the second embodiment.

FIG. 6 is a cross-sectional view showing an outer lead forming step in the manufacturing steps of the semiconductor device according to the second embodiment.

FIG. 7 is a diagram showing wire bonding conditions in a manufacturing process of a semiconductor device according to a second embodiment in comparison with conventional wire bonding conditions.

FIGS. 8A and 8B are an enlarged cross-sectional view and a perspective view illustrating a vicinity of a bonding region of an inner lead formed by a manufacturing process of a semiconductor device according to a second embodiment.

FIG. 9 is a cross-sectional view illustrating a structure of a conventional semiconductor device.

FIG. 10 is a cross-sectional view showing a die bonding step in a conventional semiconductor device manufacturing process.

FIG. 11 is a cross-sectional view showing a wire bonding step in a conventional semiconductor device manufacturing process.

FIG. 12 is a cross-sectional view showing a resin sealing step in a conventional semiconductor device manufacturing process.

FIG. 13 is a cross-sectional view showing an outer lead forming step in a conventional semiconductor device manufacturing process.

14A and 14B are an enlarged cross-sectional view and a perspective view showing the vicinity of a bonding region of an inner lead formed by a conventional semiconductor device manufacturing process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Lead frame 2 Die pad part 3 Semiconductor chip 4 Electrode 5 Inner lead part 5a Bonding area 6 Thin metal wire 6a Tip part 7 Sealing resin 8 Outer lead part 9 Main body 10 Nickel plating layer 11 Palladium plating layer 12 Gold plating layer 13 Peeling area 20 Bonding tool

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Kouei Maruyama 1-1, Komachi, Takatsuki City, Osaka Prefecture Matsushita Electronics Corporation

Claims (14)

[Claims] 1. A semiconductor chip having electrode pads, a main body made of metal, and a laminated plating layer formed on the main body layer and having an uppermost layer made of a soft material, and at least an inner lead portion and an outer lead. A lead frame having a portion, a thin metal wire connecting the electrode pad of the semiconductor chip and the lead frame, and an uppermost layer of the laminated plating layer in a region of the inner lead portion to which the thin metal wire is connected. A semiconductor device having a thickness greater than a thickness of an uppermost layer in another region. 2. The semiconductor device according to claim 1, wherein the uppermost layer of the laminated plating layer of the inner lead portion and the thin metal wire are made of the same material. 13. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the main body of the inner lead portion is made of a copper plate, and the laminated plating layer of the inner lead portion is a nickel plating layer, a palladium plating layer, A semiconductor device, comprising: a gold plating layer sequentially laminated; and wherein the thin metal wire is composed of a material containing gold as a main component. 4. A step of preparing a semiconductor chip having an electrode pad; and having an inner lead portion and an outer lead portion formed by applying a laminated plating layer whose uppermost layer is made of a soft material on a main body made of metal. A step of preparing a lead frame; a first bonding step of joining the thin metal wire and the electrode pad while applying a load and an ultrasonic wave with the tip of the thin metal wire applied to the electrode pad of the semiconductor chip; A second bonding step of applying a load without applying ultrasonic waves to connect the thin metal wire and the inner lead portion with another portion of the thin metal wire applied to the inner lead portion. A method for manufacturing a semiconductor device. 5. A step of preparing a semiconductor chip having an electrode pad, and a lead frame having an inner lead portion and an outer lead portion formed by applying a laminated plating layer having a top layer made of a soft material on a main body made of metal. A first bonding step of joining the thin metal wire and the electrode pad while applying a load and an ultrasonic wave with the tip of the thin metal wire applied to the electrode pad of the semiconductor chip; and the inner lead In a state where the other portion of the thin metal wire is applied to the portion, a pressing load larger than the first bonding step and an ultrasonic wave having a smaller output than the first bonding step are applied to the thin metal wire and the inner wire. A method of manufacturing a semiconductor device, comprising: a second bonding step of connecting a lead portion. 6. The method of manufacturing a semiconductor device according to claim 5, wherein in the first bonding step, the ultrasonic output is set to about 55 (m).
W), and the pressing load is set to about 60 (g). In the second bonding step, the ultrasonic output is set to 0 to 20.
(MW) and a pressing load of 150 to 250 (g). 7. The method for manufacturing a semiconductor device according to claim 4, wherein in the first and second bonding steps, a thin metal wire made of a material having the same quality as the uppermost layer of the laminated plating layer is used. A method for manufacturing a semiconductor device, comprising: 8. The method for manufacturing a semiconductor device according to claim 4, wherein in the step of preparing the lead frame, a nickel plating layer, a palladium plating layer, and a gold plating layer are sequentially laminated on a main body made of a copper plate. A method of manufacturing a semiconductor device, comprising: forming a laminated plating layer by using a metal thin wire composed of a material containing gold as a main component in the first and second bonding steps. 9. The method of manufacturing a semiconductor device according to claim 4, wherein the second bonding step is performed at a temperature of 150 to 300 (° C.). A method for manufacturing a semiconductor device. 10. The method for manufacturing a semiconductor device according to claim 4, wherein in the step of preparing the lead frame, the thin metal wire of the inner lead portion is connected. A method of manufacturing a semiconductor device, comprising: making a thickness of an uppermost layer of a laminated plating layer in a region larger than a thickness of an uppermost layer in another region. 11. A step of preparing a semiconductor chip having an electrode pad, and performing an inner lead portion formed by applying a laminated plating in which a nickel plating layer, a palladium plating layer, and a gold plating layer are sequentially laminated on a metal main body. A step of preparing a lead frame having an outer lead portion, while applying a load and ultrasonic waves in a state in which a tip of a thin metal wire made of a material mainly containing gold is applied to the electrode pads of the semiconductor chip. A first bonding step of joining the thin metal wire and the electrode pad; and a pressing load of 150 to 250 (g) and an output of 0 to 20 in a state where another portion of the thin metal wire is applied to the inner lead portion. A second bonding step of applying an ultrasonic wave of (mW) to connect the fine metal wire and the inner lead portion. A method for manufacturing a conductor device. 12. The method for manufacturing a semiconductor device according to claim 11, wherein after the first bonding step and the second bonding step, the semiconductor chip, the thin metal wires, and the inner lead portions are sealed with a resin. A method for manufacturing a semiconductor device, further comprising: 13. The method of manufacturing a semiconductor device according to claim 11, wherein the second bonding step is performed at a temperature of 150 to 300 (° C.). 14. The method of manufacturing a semiconductor device according to claim 11, wherein in the second bonding step, an output of an ultrasonic wave is set to 0.