JPH1092964A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1092964A JPH1092964A JP8239621A JP23962196A JPH1092964A JP H1092964 A JPH1092964 A JP H1092964A JP 8239621 A JP8239621 A JP 8239621A JP 23962196 A JP23962196 A JP 23962196A JP H1092964 A JPH1092964 A JP H1092964A
- Authority
- JP
- Japan
- Prior art keywords
- solder resist
- wiring pattern
- semiconductor device
- semiconductor element
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
Landscapes
- Wire Bonding (AREA)
- Chemically Coating (AREA)
Abstract
(57)【要約】
【課題】 ソルダーレジストと樹脂部材との接着部の接
着を十分にし、半導体装置のワイヤーの切断を防止する
ことができる半導体装置を提供する。
【解決手段】 プリント基板２０を有し、その表面には
配線パターン２１が形成され、電気的接続が不要な部分
をソルダーレジスト２２で覆い、Ｎｉ，Ａｕメッキが施
されている。プリント基板２０上には半導体素子２３が
搭載され、エポキシ樹脂等の接着剤２４等によりプリン
ト基板２０と固着されている。半導体素子２３の電極部
はワイヤー２５によって、配線パターン２１の接続部と
接続されている。半導体素子２３、ワイヤー２５、及び
ワイヤー２５と配線パターン２１との接続部は、樹脂部
材２６で覆われ樹脂封止されている。この時、プリント
基板２０上のソルダーレジスト２２の表面に凹凸２２ａ
が施されている。
(57) [Problem] To provide a semiconductor device capable of sufficiently bonding an adhesive portion between a solder resist and a resin member and preventing a wire of the semiconductor device from being cut. SOLUTION: A printed circuit board 20 is provided, and a wiring pattern 21 is formed on a surface of the printed circuit board. A portion which does not need to be electrically connected is covered with a solder resist 22, and plated with Ni or Au. A semiconductor element 23 is mounted on the printed board 20, and is fixed to the printed board 20 by an adhesive 24 such as an epoxy resin. The electrode part of the semiconductor element 23 is connected to the connection part of the wiring pattern 21 by a wire 25. The semiconductor element 23, the wire 25, and the connection between the wire 25 and the wiring pattern 21 are covered with a resin member 26 and sealed with a resin. At this time, the surface of the solder resist 22 on the printed circuit board 20 has irregularities 22a.
Is given.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子等を搭
載する、有機性基板を用いた半導体装置に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device on which an organic substrate is mounted, on which a semiconductor element and the like are mounted.
【０００２】[0002]
【従来の技術】従来、このような分野の技術としては、
以下に示すようなものがあった。図３はかかる従来の半
導体装置の断面図である。この図に示すように、この半
導体装置は、例えば硝子エポキシ基板や、ベークライト
基板等の有機性基板からなる、印刷配線基板（以下プリ
ント基板と言う）１を有し、そのプリント基板１の表面
には導電性の配線パターン２が銅箔パターンで形成され
ている。2. Description of the Related Art Conventionally, techniques in such a field include:
There were the following. FIG. 3 is a sectional view of such a conventional semiconductor device. As shown in this figure, this semiconductor device has a printed wiring board (hereinafter referred to as a printed board) 1 made of an organic substrate such as a glass epoxy board or a bakelite board. Has a conductive wiring pattern 2 formed of a copper foil pattern.
【０００３】その配線パターン２にＮｉ、Ａｕメッキを
行い銅箔の酸化等を防止する。その時、Ｎｉ、Ａｕメッ
キエリアを少なくし、コストダウンを図るため、ソルダ
ーレジスト３で、部品搭載部等、電気的接続を必要とし
ない配線パターンを覆っている。このソルダーレジスト
３には、熱硬化型と、感光性の二種類がある。プリント
基板１上には、半導体素子４が搭載され、エポキシ樹脂
等の接着剤５で固着されている。半導体素子４の電極部
はワイヤー６（Ａｕ線、Ａｌ線等）によって配線パター
ン２と接続されている。そして、半導体素子４と配線パ
ターン２の接続箇所とが樹脂部材７（エポキシ樹脂等）
で樹脂封止されている。The wiring pattern 2 is plated with Ni or Au to prevent oxidation of the copper foil. At this time, in order to reduce the Ni and Au plating area and reduce the cost, the solder resist 3 covers a wiring pattern that does not require electrical connection, such as a component mounting portion. The solder resist 3 has two types, a thermosetting type and a photosensitive type. A semiconductor element 4 is mounted on the printed circuit board 1 and fixed with an adhesive 5 such as an epoxy resin. The electrode portion of the semiconductor element 4 is connected to the wiring pattern 2 by a wire 6 (Au line, Al line, etc.). The connection between the semiconductor element 4 and the wiring pattern 2 is made of a resin member 7 (epoxy resin or the like).
Resin sealing.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記し
た従来の半導体装置では、ソルダーレジスト表面汚れ及
び樹脂部材７との接着強度が小さい等の問題により、ソ
ルダーレジスト３と樹脂部材７との接着部に剥離が入
り、半導体装置のワイヤー６を切断するという問題があ
る。However, in the above-described conventional semiconductor device, due to problems such as contamination of the surface of the solder resist and a low adhesive strength with the resin member 7, the adhesion between the solder resist 3 and the resin member 7 is reduced. There is a problem that separation occurs and the wire 6 of the semiconductor device is cut.
【０００５】本発明は、上記問題点を除去し、ソルダー
レジストと樹脂部材との接着部の接着を十分にし、半導
体装置のワイヤーの切断を防止することができる半導体
装置を提供することを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device which eliminates the above-mentioned problems, sufficiently bonds an adhesive portion between a solder resist and a resin member, and can prevent a wire of the semiconductor device from being cut. I do.
【０００６】[0006]
【課題を解決するための手段】本発明は、上記目的を達
成するために、 （１）基板上に配線パターンを形成し、ソルダーレジス
トで電気的接続を必要としない配線パターンを覆い、樹
脂封止を行う半導体装置において、前記ソルダーレジス
ト上に機械加工により凹凸を施すようにしたものであ
る。According to the present invention, in order to achieve the above object, (1) a wiring pattern is formed on a substrate, and a wiring pattern which does not require electrical connection is covered with a solder resist, and a resin seal is formed. In the semiconductor device for stopping, the solder resist is provided with irregularities by machining.
【０００７】このように、ソルダーレジスト塗布後に機
械加工により凹凸を付けるようにしたので、樹脂部材と
の密着面積が増大し、接着強度が向上し、信頼性の高い
半導体素子を得ることができる。 （２）基板上に配線パターンを形成し、ソルダーレジス
トで電気的接続を必要としない配線パターンを覆い、樹
脂封止を行う半導体装置において、前記ソルダーレジス
ト上に化学処理により凹凸を施すようにしたものであ
る。As described above, since the unevenness is formed by machining after the application of the solder resist, the contact area with the resin member is increased, the adhesive strength is improved, and a highly reliable semiconductor element can be obtained. (2) In a semiconductor device that forms a wiring pattern on a substrate, covers a wiring pattern that does not require electrical connection with a solder resist, and performs resin sealing, the solder resist is provided with irregularities by a chemical treatment. Things.
【０００８】このように、ソルダーレジスト塗布後に化
学加工により凹凸を付けるようにしたので、樹脂部材と
の密着面積が増大し、接着強度が向上し、信頼性の高い
半導体素子を得ることができる。 （３）基板上に配線パターンを形成し、ソルダーレジス
トで電気的接続を必要としない配線パターンを覆い、樹
脂封止を行う半導体装置において、前記ソルダーレジス
ト上に無電解Ｃｕメッキを施すようにしたものである。As described above, since the unevenness is formed by the chemical processing after the solder resist is applied, the contact area with the resin member is increased, the bonding strength is improved, and a highly reliable semiconductor element can be obtained. (3) In a semiconductor device that forms a wiring pattern on a substrate, covers a wiring pattern that does not require electrical connection with a solder resist, and performs resin sealing, electroless Cu plating is performed on the solder resist. Things.
【０００９】このように、ソルダーレジスト塗布後に無
電解Ｃｕメッキを施すだけの簡単な工程により、樹脂部
材との密着面積が増大し、接着強度が向上し、信頼性の
高い半導体素子を得ることができる。As described above, by a simple process of merely applying electroless Cu plating after solder resist coating, it is possible to obtain a highly reliable semiconductor element having an increased adhesion area with a resin member, improved adhesive strength. it can.
【００１０】[0010]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して詳細に説明する。図１は本発明の第１
実施例を示す半導体装置の断面図である。この半導体装
置は、チップ・オン・ボード（ｃｈｉｐ ｏｎ ｂｏａ
ｒｄ）と称されるタイプのものである。例えば、エポキ
シ基板やベークライト基板等の有機性基板からなる絶縁
性のプリント基板２０を有し、そのプリント基板２０の
表面には銅箔等からなる導電性の配線パターン２１が形
成され、電気的接続が不要な部分をソルダーレジスト２
２で覆い、Ｎｉ，Ａｕメッキが施されている。Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows the first embodiment of the present invention.
FIG. 4 is a cross-sectional view of a semiconductor device according to an example. This semiconductor device is a chip on board (chip on board)
rd). For example, it has an insulating printed board 20 made of an organic board such as an epoxy board or a bakelite board, and a conductive wiring pattern 21 made of a copper foil or the like is formed on the surface of the printed board 20 so that electrical connection is made. Unnecessary parts are solder resist 2
2 and plated with Ni and Au.
【００１１】また、プリント基板２０上には半導体素子
２３が搭載され、エポキシ樹脂等の接着剤２４やＡｕ−
Ｓｉ（金、シリコン）共晶合金方法等により、プリント
基板２０に固着されている。半導体素子２３の電極部
は、Ａｌ（アルミニウム）、Ａｕ（金）等のワイヤー２
５によって、配線パターン２１の接続部と接続されてい
る。A semiconductor element 23 is mounted on the printed circuit board 20, and an adhesive 24 such as epoxy resin or Au-
It is fixed to the printed circuit board 20 by a Si (gold, silicon) eutectic alloy method or the like. The electrode portion of the semiconductor element 23 is made of a wire 2 of Al (aluminum), Au (gold) or the like.
5 is connected to the connection portion of the wiring pattern 21.
【００１２】更に、半導体素子２３、ワイヤー２５、及
びワイヤー２５と配線パターン２１との接続部は、エポ
キシ、シリコン、ポリイミド樹脂等からなる樹脂部材２
６で覆われ樹脂封止されている。この時、プリント基板
２０上のソルダーレジスト２２の表面に凹凸２２ａが施
されている。Further, the semiconductor element 23, the wire 25, and the connection between the wire 25 and the wiring pattern 21 are made of a resin member 2 made of epoxy, silicon, polyimide resin or the like.
6 and sealed with resin. At this time, irregularities 22a are formed on the surface of the solder resist 22 on the printed circuit board 20.
【００１３】図２は、上記したプリント基板、配線パタ
ーン及びソルダーレジストの製造工程図である。なお、
ここでは両面プリント基板として示されている。 （１）まず、図２（ａ）に示すように、プリント基板２
０を用意する。 （２）次に、図２（ｂ）に示すように、プリント基板２
０に対し、穴空け加工を行い、スルーホール２０ａを形
成する。FIG. 2 is a manufacturing process diagram of the above-mentioned printed circuit board, wiring pattern and solder resist. In addition,
Here, it is shown as a double-sided printed circuit board. (1) First, as shown in FIG.
Prepare 0. (2) Next, as shown in FIG.
Drilling is performed on 0 to form a through hole 20a.
【００１４】（３）次に、図２（ｃ）に示すように、ス
ルーホール２０ａ内に無電解Ｃｕメッキ２１ａにより銅
の薄膜を形成し、全面を電解Ｃｕメッキ２１ｂによりス
ルーホール２０ａの壁の銅メッキ厚を厚くする。その
後、有機レジストにより回路形成を行い、不要の銅パタ
ーンをエッチングし、除去することにより、プリント基
板２０上に配線パターンを複数形成する。(3) Next, as shown in FIG. 2 (c), a copper thin film is formed in the through hole 20a by electroless Cu plating 21a, and the entire surface is covered with electrolytic Cu plating 21b to form a wall of the through hole 20a. Increase the copper plating thickness. Thereafter, a circuit is formed with an organic resist, unnecessary copper patterns are etched and removed, and a plurality of wiring patterns are formed on the printed circuit board 20.
【００１５】（４）その後、図２（ｄ）に示すように、
電気的接続部をマスキングし、ソルダーレジスト２２を
非電気的接続部に塗布する。この後、パターニングされ
たソルダーレジスト表面にバフ研磨等の機械加工を加え
て、ソルダーレジスト表面に凹凸２２ａを付ける。 （５）次に、マスキング材を取り去り、図２（ｅ）に示
すように、配線パターン２１のソルダーレジスト２２で
覆われた以外の配線パターン部に、Ｎｉ、Ａｕメッキ２
１ｃを行う。(4) Thereafter, as shown in FIG.
The electrical connection is masked and a solder resist 22 is applied to the non-electric connection. Thereafter, mechanical processing such as buffing is performed on the patterned solder resist surface to form irregularities 22a on the solder resist surface. (5) Next, the masking material is removed, and as shown in FIG. 2E, Ni and Au plating 2 are applied to the wiring pattern portions of the wiring pattern 21 other than those covered with the solder resist 22.
Perform 1c.
【００１６】このように、製造されたプリント基板２０
上に半導体素子２３を搭載し、その電極部をワイヤー２
５で配線パターン２１の接続部と接続し、その後、樹脂
部材２６で覆うことにより、図１に示したような半導体
装置が得られる。上記のように、ソルダーレジスト塗布
後に機械加工により、凹凸を付けたことにより、樹脂部
材との密着面積が増大し、接着強度が向上し、信頼性の
高い半導体素子を得ることができる。The printed circuit board 20 thus manufactured is
The semiconductor element 23 is mounted thereon, and its electrode portion is connected to the wire 2.
The semiconductor device as shown in FIG. 1 is obtained by connecting with the connection part of the wiring pattern 21 at 5 and then covering with the resin member 26. As described above, by providing the unevenness by machining after the application of the solder resist, the area of adhesion to the resin member is increased, the adhesive strength is improved, and a highly reliable semiconductor element can be obtained.
【００１７】なお、上記実施例ではソルダーレジスト上
の凹凸の作製を機械加工によって施したが、化学的処理
により凹凸を設けることにより、機械加工時のようにプ
リント基板毎に機械加工するのではなく、複数枚のプリ
ント基板を一括で処理することにより、作業性の向上及
び低コストでの加工が行えるようになる。次に、本発明
の第２実施例について説明する。In the above embodiment, the irregularities on the solder resist are formed by machining. However, by providing the irregularities by chemical treatment, the machining is not performed for each printed circuit board as in the case of machining. By processing a plurality of printed circuit boards collectively, workability can be improved and processing can be performed at low cost. Next, a second embodiment of the present invention will be described.
【００１８】図４は本発明の第２実施例を示す半導体装
置の断面図である。この図において、上記第１実施例と
同じ部分については同じ符号を付し、それらの説明にい
ては重複するので省略する。図４に示すように、この実
施例については、ソルダーレジスト２２上に無電解Ｃｕ
メッキ２７を施すようにしている。FIG. 4 is a sectional view of a semiconductor device according to a second embodiment of the present invention. In this figure, the same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted because they are duplicated. As shown in FIG. 4, for this embodiment, electroless Cu
The plating 27 is applied.
【００１９】これにより、無電解Ｃｕメッキ２７のＣｕ
表面の酸化により、樹脂部材との接着強度を向上させる
ことができる。なお、本発明は上記実施例に限定される
ものではなく、本発明の趣旨に基づいて種々の変形が可
能であり、これらを本発明の範囲から排除するものでは
ない。Thus, the Cu of the electroless Cu plating 27
Oxidation of the surface can improve the adhesive strength with the resin member. It should be noted that the present invention is not limited to the above embodiment, and various modifications can be made based on the gist of the present invention, and these are not excluded from the scope of the present invention.
【００２０】[0020]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、以下のような効果を奏することができる。 （１）請求項１記載の発明によれば、ソルダーレジスト
塗布後に機械加工により凹凸を付けたことにより、樹脂
部材との密着面積が増大し、接着強度が向上し、信頼性
の高い半導体素子を得ることができる。As described above, according to the present invention, the following effects can be obtained. (1) According to the first aspect of the present invention, since the unevenness is formed by machining after the application of the solder resist, the contact area with the resin member is increased, the adhesive strength is improved, and a highly reliable semiconductor element is provided. Obtainable.
【００２１】（２）請求項２記載の発明によれば、ソル
ダーレジスト塗布後に化学加工により凹凸を付けたこと
により、樹脂部材との密着面積が増大し、接着強度が向
上し、信頼性の高い半導体素子を得ることができる。 （３）請求項３記載の発明によれば、ソルダーレジスト
塗布後に無電解Ｃｕメッキを施すだけの簡単な工程によ
り、樹脂部材との密着面積が増大し、接着強度が向上
し、信頼性の高い半導体素子を得ることができる。(2) According to the second aspect of the present invention, since the unevenness is formed by chemical processing after the application of the solder resist, the contact area with the resin member is increased, the adhesive strength is improved, and the reliability is high. A semiconductor element can be obtained. (3) According to the third aspect of the present invention, the area of adhesion to the resin member is increased, the adhesion strength is improved, and the reliability is high by a simple process of only performing electroless Cu plating after applying the solder resist. A semiconductor element can be obtained.
【図１】本発明の第１実施例を示す半導体装置の断面図
である。FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第１実施例を示すプリント基板、配線
パターン及びソルダーレジストの製造工程図である。FIG. 2 is a manufacturing process diagram of a printed circuit board, a wiring pattern, and a solder resist according to the first embodiment of the present invention.
【図３】従来の半導体装置の断面図である。FIG. 3 is a cross-sectional view of a conventional semiconductor device.
【図４】本発明の第２実施例を示す半導体装置の断面図
である。FIG. 4 is a sectional view of a semiconductor device according to a second embodiment of the present invention.
２０ プリント基板 ２０ａ スルーホール ２１ 配線パターン ２２ ソルダーレジスト ２２ａ 凹凸 ２３ 半導体素子 ２４ 接着剤 ２５ ワイヤー ２６ 樹脂部材 Reference Signs List 20 printed circuit board 20a through hole 21 wiring pattern 22 solder resist 22a unevenness 23 semiconductor element 24 adhesive 25 wire 26 resin member
Claims (3)
ーレジストで電気的接続を必要としない配線パターンを
覆い、樹脂封止を行う半導体装置において、 前記ソルダーレジスト上に機械加工により凹凸を施すよ
うにしたことを特徴とする半導体装置。1. A semiconductor device in which a wiring pattern is formed on a substrate, a wiring pattern that does not require electrical connection is covered with a solder resist, and resin sealing is performed. A semiconductor device, characterized in that:
ーレジストで電気的接続を必要としない配線パターンを
覆い、樹脂封止を行う半導体装置において、 前記ソルダーレジスト上に化学処理により凹凸を施すよ
うにしたことを特徴とする半導体装置。2. A semiconductor device in which a wiring pattern is formed on a substrate, a wiring pattern not requiring electrical connection is covered with a solder resist, and resin sealing is performed. A semiconductor device, characterized in that:
ーレジストで電気的接続を必要としない配線パターンを
覆い、樹脂封止を行う半導体装置において、 前記ソルダーレジスト上に無電解Ｃｕメッキを施すよう
にしたことを特徴とする半導体装置。3. A semiconductor device which forms a wiring pattern on a substrate, covers a wiring pattern which does not require electrical connection with a solder resist, and performs resin sealing, wherein an electroless Cu plating is performed on the solder resist. A semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8239621A JPH1092964A (en) | 1996-09-11 | 1996-09-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8239621A JPH1092964A (en) | 1996-09-11 | 1996-09-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1092964A true JPH1092964A (en) | 1998-04-10 |
Family
ID=17047462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8239621A Withdrawn JPH1092964A (en) | 1996-09-11 | 1996-09-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1092964A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105451466A (en) * | 2014-09-23 | 2016-03-30 | 罗伯特·博世有限公司 | Electronic module and manufacturing method thereof |
| DE102017208476A1 (en) * | 2017-05-19 | 2018-11-22 | Conti Temic Microelectronic Gmbh | Method for producing an electronic component and electronic component |
| CN110677992A (en) * | 2019-09-26 | 2020-01-10 | 维沃移动通信有限公司 | A circuit board assembly, a method for making the circuit board assembly, and a terminal device |
-
1996
- 1996-09-11 JP JP8239621A patent/JPH1092964A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105451466A (en) * | 2014-09-23 | 2016-03-30 | 罗伯特·博世有限公司 | Electronic module and manufacturing method thereof |
| CN105451466B (en) * | 2014-09-23 | 2019-07-09 | 罗伯特·博世有限公司 | Electronic module and affiliated manufacturing method |
| DE102017208476A1 (en) * | 2017-05-19 | 2018-11-22 | Conti Temic Microelectronic Gmbh | Method for producing an electronic component and electronic component |
| CN110677992A (en) * | 2019-09-26 | 2020-01-10 | 维沃移动通信有限公司 | A circuit board assembly, a method for making the circuit board assembly, and a terminal device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20031202 |