JPH1093024A - Semiconductor integrated circuit device - Google Patents

Abstract

[PROBLEMS] To increase the speed and integration of a semiconductor integrated circuit device having a plurality of MISFETs. A semiconductor integrated circuit device having a plurality of MISFETs Qn, wherein each of the plurality of MISFETs Qn is provided on a surface of a buried insulating film 1B of a semiconductor substrate 1 by a source region (n-type semiconductor region 8) and a drain region ( Each of the plurality of MISFETs Qn has a structure in which the bottoms of the n-type semiconductor regions 8) are in contact with each other.
(p-type well region 4A) and a second conductivity type well region 4B that is electrically connected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, in particular, a plurality of MISFET (M etal I nsulat
when applied to a semiconductor integrated circuit device having a or S emicondutor F ield E ffect T ransistor) a technique effectively.

[0002]

2. Description of the Related Art There is a MISFET as an active element mounted on a semiconductor integrated circuit device. Since this MISFET has a smaller occupation area than a bipolar transistor, high integration of a semiconductor integrated circuit device can be achieved.

When the MISFET is of an n-channel conductivity type, for example, a p-type well region formed on the main surface of the semiconductor substrate is used as a channel forming region, and a pair of n-type wells formed on the main surface of the p-type well region are used. Since the semiconductor region is configured to have a source region and a drain region, a pn junction capacitance formed by the p-type well region and the n-type semiconductor region
(Parasitic capacitance) is added to the source region and the drain region. This pn junction capacitance lowers the switching speed of the MISFET and hinders the speeding up of the semiconductor integrated circuit device.

Therefore, a so-called SOI in which a buried insulating film is provided between a supporting substrate and a thin semiconductor layer made of single crystal silicon.
(S ilicon O n I nsulator) using semiconductor substrate construction, MISFET bottom contacting the structure of the source and drain regions on the surface of the buried insulating film of the semiconductor substrate
Is an international electron device meeting technical digest published in 1993 [IE
DM93, Technical Digest], pages 727 to 73
It is disclosed on page 0. This MISFET can reduce the pn junction capacitance added to the source region and the drain region by an amount corresponding to the area of the bottom of the source region and the drain region. The speed of the integrated circuit device can be increased. The MISFET is formed on the surface of a buried insulating film of a semiconductor substrate, and its periphery is defined by a field insulating film in contact with the surface, and is electrically isolated from other MISFETs.

[0005]

In a MISFET mounted on a semiconductor integrated circuit device, a channel forming region is fixed in potential in order to stabilize a threshold voltage (Vth). For example, the range of the operating potential of the MISFET is 0 [V] to +5
In the case of [V], the channel formation region of the p-channel conductivity type MISFET is fixed at a positive potential of +5 [V] or more,
The channel formation region of the n-channel MISFET is 0
The potential is fixed to a negative potential of [V] or less. Normally, the potential of the channel formation region of the MISFET is fixed via a power supply contact region formed on the main surface of the well region. The power supply contact region is formed of a semiconductor region having the same conductivity type as the well region, and is electrically connected to each channel forming region of the plurality of MISFETs formed on the main surface of the well region.

However, when the MISFET is configured to have a structure in which the bottoms of the source region and the drain region are in contact with the surface of the buried insulating film of the semiconductor substrate having the SOI structure, the MISFET has the surface of the buried insulating film of the semiconductor substrate. The periphery is defined by a field insulating film formed on and in contact with the surface, and is electrically insulated and separated from other MISFETs. Therefore, a power supply contact region must be provided for each MISFET. The occupied area of the MISFET increases, and the degree of integration of the semiconductor integrated circuit device decreases correspondingly.

An object of the present invention is to provide a technique capable of increasing the speed and the degree of integration of a semiconductor integrated circuit device having a plurality of MISFETs.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A semiconductor integrated circuit device having a plurality of first conductivity type MISFETs, wherein the plurality of first conductivity type MISFETs are provided.
Each of the SFETs has a structure in which the bottoms of the source region and the drain region are in contact with the surface of the buried insulating film of the semiconductor substrate, and each of the plurality of first conductivity type MISFETs is electrically connected to the channel formation region and In the well region of the second conductivity type, which is electrically connected.

When the MISFET is to be separated by the above-described method when the semiconductor substrate having the SOI structure is not used, a region required for the separation is increased. This is for setting the impurity concentration of the well region to a low concentration in order to set the threshold voltage to an appropriate value.

On the other hand, when a semiconductor substrate having an SOI structure is used, especially in a structure in which the bottoms of the source and drain regions of the MISFET are in contact with the surface of the buried insulating film, the threshold voltage is set to an appropriate value. Therefore, the impurity concentration in the well region is set to be higher than that in the case where the SOI structure semiconductor substrate is not used, so that the element can be separated in the well region. This can be explained as follows.

[0013] In general, MOSFET (M etal O xide S e
micondutor FET ) and threshold electrode (Threshold Vllta)
When a voltage equivalent to that of ge) is externally applied to the gate electrode, an inversion layer is formed on the silicon surface immediately below the gate electrode, and the amount of charge induced immediately below the gate electrode and the externally applied voltage are balanced. .

Here, M using an SOI semiconductor substrate
In case of OSFET, MOS using single crystal silicon substrate
The volume of silicon immediately below the gate electrode is smaller than that of the FET. As a result, the amount of charges induced immediately below the gate electrode is reduced, so that an inversion layer is formed with a practically smaller externally applied voltage. That is, the threshold voltage decreases. In order to prevent the threshold voltage from lowering, it is necessary to increase the amount of charge induced immediately below the gate electrode. To increase the amount of charge induced immediately below the gate electrode, the amount of silicon in the silicon immediately below the gate electrode must be increased. This is realized by setting the charge amount, that is, the impurity concentration in the well region to be high.

These are described in I.I.E., Electron Device Letters, No. E, issued in April 1986.
DL-7 Volume 4 (IEEE ELECTRON DEV)
ICE LETTERS, VOL. EDL-7. NO
4, APRIL 1986), page 244, @Subthresh
The old Slope of Thin-Flim SOI MOSFETs is shown in Figure 3. Also, published in 1993, International Electron Device Meeting Technical Digest (IEDM93 Technical Digest)
〃 @ SYMMETRIC CMOS IN on page 727
FULLY-DEPLETED SILICON-ON
-INSULATOR USING P + POLYCR
YSTALLINE Si-Ge GATE ELEC
This is shown in FIG. 1 and FIG.

According to the above-described means, the pn junction capacitance (parasitic capacitance) added to the source region and the drain region can be reduced by an amount corresponding to the area of the bottom of the source region and the drain region. The switching speed can be increased. Further, by fixing the potential of the second conductivity type well region, the potential of the channel forming region of the MISFET electrically connected to the second conductivity type well region can be fixed.
There is no need to provide a power supply contact area for each FET,
The occupied area of each MISFET can be reduced. As a result, a high speed and high integration of a semiconductor integrated circuit device having a plurality of MISFETs can be achieved.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

An SRAM ( S tat) according to an embodiment of the present invention.
The schematic structure of the ic R andom A ccess M emory) shown in FIG. 1 (chip layout diagram).

As shown in FIG. 1, the SRAM of this embodiment
The (semiconductor integrated circuit device) includes four memory cell units 50 and peripheral circuit units 51A, 51B, 51C,
51D.

A plurality of Y decoder circuits and a plurality of driver circuits are arranged in the peripheral circuit section 51B, and a plurality of X decoder circuits and a plurality of driver circuits are arranged in the peripheral circuit section 51C. Are provided with a plurality of input / output circuits.

Each of the four memory cell sections 50 has:
As shown in FIG. 2 (main part block diagram), a plurality of memory cells M for storing 1-bit information are arranged in a matrix.
The peripheral circuit section 51A includes a column selection circuit CA.
And a sense circuit SE. A plurality of column selection circuits CA and sense circuits SE are arranged.

FIG. 3 (equivalent circuit diagram)
MISFETs Qp1, Qp2 and MISFET
It comprises FETs Qn1, Qp2, Qp3, Qp4. Each of the MISFETs Qp1 and Qp2 is of a p-channel conductivity type, and the MISFETs Qn1, Qn2 and Qn3
Are of the n-channel conductivity type.

One semiconductor region of the MISFET Qp1 is electrically connected to an operating potential terminal Vcc to which an operating potential (for example, +5 [V]) is applied, and the other semiconductor region is electrically connected to one semiconductor region of the MISFET Qn1. And its gate electrode is electrically connected to the gate electrode of the MISFET Qp2. One semiconductor region of MISFET Q2 is electrically connected to operating potential terminal Vcc, and the other semiconductor region is electrically connected to one semiconductor region of MISFET Qn2.

The other semiconductor region of the MISFET Qn1 is electrically connected to one semiconductor region of each of the MISFETs Qn3 and Qn4, and its gate electrode is electrically connected to the signal input terminal In1. The MISFET
The other semiconductor region of Qn2 is MISFET Qn3, Qn
4 is electrically connected to one of the semiconductor regions, and its gate electrode is electrically connected to the signal input terminal In2.

The other semiconductor region of the MISFET Qn3 is electrically connected to a reference potential terminal Vss to which a reference potential (for example, 0 [V]) is applied, and its gate electrode is connected to a terminal SEL to which a sense circuit selection signal is applied. It is electrically connected. The other semiconductor region of the MISFET Qn4 is electrically connected to the reference potential terminal Vss, and its gate electrode is electrically connected to the terminal SEL.

The gate electrodes of the MISFETs Qp1 and Qp2 are electrically connected to the other semiconductor region of the MISFET Qp1 and one semiconductor region of the MISFET Qn1, respectively.
One semiconductor region of the ISFET Qn2 is a signal output terminal O
ut.

The respective channel forming regions of the MISFETs Qp1 and Qp2 are fixed at a potential of, for example, +5 [V] in order to stabilize their threshold voltage (Vth). Further, the MISFETs Qn1, Qn2, Qn3,
The respective channel forming regions of Qn4 are fixed at a potential of, for example, 0 [V] in order to stabilize their threshold voltage (Vth).

As shown in FIG. 4 (equivalent circuit diagram), the memory cell M includes a flip-flop circuit composed of two inverter circuits and MISFETs Qn5 and Qn6. One of the inverter circuits is composed of a MISFET Qp3 and a MISFET Qn7, and the other inverter circuit is composed of a MISFET Qp4 and a MISFET Qn8. Each of the MISFETs Qp3 and Qp4 is of a p-channel conductivity type, and the MISFETs Qn5 and Qn
Each of 6, Qn7, and Qn8 is of an n-channel conductivity type. Each of the MISFETs Qp3 and Qp4 is configured as a load element, and the MISFETs Qn7, Qn
8 are each configured as a driving element, and the MISFET Q
Each of n5 and Qn6 is configured as a transfer element.

One of the semiconductor regions of the MISFET (for transfer) Qn5 is a MISFET (for load) Qp3, MISFE.
T (for driving) Qn7 is electrically connected to one semiconductor region, the other semiconductor region is electrically connected to data line DL1, and its gate electrode is electrically connected to word line WL. I have.

One semiconductor region of the MISFET (for transfer) Qn6 is a MISFET (for load) Qp4, MISFE.
T (for driving) Qn8 is electrically connected to one semiconductor region, the other semiconductor region is electrically connected to data line DL2, and its gate electrode is electrically connected to word line WL. I have.

The other semiconductor region of the MISFET Qp3 is electrically connected to an operating potential terminal Vcc to which an operating potential (for example, +5 [V]) is applied, and its gate electrode is set to MI.
It is electrically connected to the gate electrode of SFET Qn7. The other semiconductor region of the MISFET Qp4 is electrically connected to an operating potential terminal Vcc, and its gate electrode is
It is electrically connected to the gate electrode of ISFET Qn8.

The other semiconductor region of each of the MISFETs Qn7 and Qn8 is electrically connected to a reference potential terminal Vss to which a reference potential (for example, 0 [V]) is applied.

The MISFET Qp3, MISFET Q
The respective gate electrodes of n7 are MISFETs Qp4, MI
Each of the MISFETs Qp4 and Qn8 is electrically connected to one of the semiconductor regions of the SFET Qn8.
Qn7 is electrically connected to one of the semiconductor regions.

The channel forming regions of the MISFETs Qp3 and Qp4 are fixed at a potential of, for example, +5 [V] in order to stabilize their threshold voltage (Vth). Further, the respective channel forming regions of the MISFETs Qn7 and Qn8 are fixed at a potential of, for example, 0 [V] in order to stabilize their threshold voltage (Vth).
Further, the respective channel forming regions of the MISFETs Qn5 and Qn6 are fixed at a potential of, for example, 0 [V] in order to stabilize their threshold voltages.

Next, a specific configuration of the sense circuit SE will be described with reference to FIGS. FIG. 5 is a plan view of a main part of the peripheral circuit unit 51A, and FIG.
FIG. 7 is a cross-sectional view taken along line A-A, FIG. 7 is a cross-sectional view taken along line BB shown in FIG. 5, and FIG. 8 is a plan view showing a layout of each semiconductor region in FIG. is there. Note that in FIGS. 5 to 7, the second
The illustration of the layer above the wiring of the layer is omitted.

As shown in FIG. 5 and FIG.
Each of ETQp1 and Qp2 is formed on the main surface of the semiconductor substrate 1. Each of the MISFETs Qp1 and Qp2 mainly includes an n-type well region 3 serving as a channel forming region.
A, a gate insulating film 5, a gate electrode 6, and a pair of p-type semiconductor regions 7 serving as a source region and a drain region. The gate insulating film 5 is formed of, for example, a thermal silicon oxide film. Gate electrode 6 is formed of, for example, a polycrystalline silicon film into which impurities are introduced.

The semiconductor substrate 1 has a buried insulating film 1 between a supporting substrate 1A and a thin semiconductor layer 1C made of single crystal silicon.
B is provided in a so-called SOI structure. The support substrate 1A is formed of, for example, a p-type semiconductor substrate made of single crystal silicon, and the embedded insulating film 1B is formed of a thermal silicon oxide film. That is, the SRAM of the present embodiment has a structure mainly including the semiconductor substrate 1 having the SOI structure.

In each of the MISFETs Qp1 and Qp2, the bottom of each of a pair of p-type semiconductor regions 7 serving as a source region and a drain region is formed by burying an insulating film 1B of the semiconductor substrate 1.
It is configured with a structure that comes into contact with the surface. This MIS
Each of the FETs Qp1 and Qp2 is formed on the surface of the buried insulating film 1B, and its periphery is defined by the field insulating film 2 in contact with the surface.
It is electrically separated from T.

A wiring 10 A is electrically connected to one of the p-type semiconductor regions 7 of the MISFETs Qp 1 and Qp 2 through a connection hole formed in the interlayer insulating film 9.
The wiring 10B is electrically connected to the other p-type semiconductor region 7 of the MISFET Qp1 through a connection hole formed in the interlayer insulating film 9, and is formed in the interlayer insulating film 9 to the other p-type semiconductor region 7 of the MISFET Qp2. The wiring 10C is electrically connected through the connection hole. Wiring 10A, 10
Each of B and 10C is formed in the first wiring layer, and is formed of, for example, an aluminum film or an aluminum alloy film.

As shown in FIG. 5 and FIG.
Each of ETQn1 and Qn4 is configured on the main surface of the semiconductor substrate 1. Each of the MISFETs Qn1 and Qn4 mainly has a p-type well region 4 serving as a channel forming region.
A, a gate insulating film 5, a gate electrode 6, and a pair of n-type semiconductor regions 8, which are a source region and a drain region.

In each of the MISFETs Qn1 and Qn4, the bottom of each of a pair of n-type semiconductor regions 8 serving as a source region and a drain region is buried in the buried insulating film 1B of the semiconductor substrate 1.
It is configured with a structure that comes into contact with the surface. This MIS
The periphery of each of the FETs Qn1 and Qn4 is defined by the field insulating film 2, and is electrically isolated from the MISFET of another sense circuit.

A wiring 10B is electrically connected to one n-type semiconductor region 8 of the MISFET Qn1 through a connection hole formed in the interlayer insulating film 9, and the other n-type semiconductor region 8 is connected to an interlayer insulating film. The wiring 10D formed in the first wiring layer is electrically connected through the connection hole formed in the wiring layer 9.

A wiring 10D is electrically connected to one n-type semiconductor region 8 of the MISFET Qn4 through a connection hole formed in an interlayer insulating film 9, and the other n-type semiconductor region 8 is connected to an interlayer insulating film. The wiring 10F formed in the first wiring layer is electrically connected through the connection hole formed in the wiring 9.

Each of the MISFETs Qn2 and Qn3 is formed on the main surface of the semiconductor substrate 1, although not shown in detail. Each of the MISFETs Qn2 and Qn3 mainly has a p-type well region 4 serving as a channel forming region, similarly to the above-described MISFETs Qn1 and Qn4.
A, a gate insulating film 5, a gate electrode 6, and a pair of n-type semiconductor regions 8, which are a source region and a drain region.

In each of the MISFETs Qn2 and Qn3, the bottom of each of a pair of n-type semiconductor regions 8 serving as a source region and a drain region is buried in the buried insulating film 1B of the semiconductor substrate 1.
It is configured with a structure that comes into contact with the surface. This MIS
The periphery of each of the FETs Qn2 and Qn3 is defined by the field insulating film 2, and is electrically separated from the MISFETs of other sense circuits.

A wiring 10C is electrically connected to one semiconductor region 8 of the MISFET Qn2, and a wiring 10D is electrically connected to the other semiconductor region 8.
The wiring 10D is electrically connected to one n-type semiconductor region 8 of the MISFET Qn3, and the wiring 10E formed in the first wiring layer is electrically connected to the other semiconductor region 8. .

As shown in FIG. 5, the wiring 10A has
The wiring 12A formed in the second wiring layer is electrically connected. Since an operating potential (for example, +5 [V]) Vcc is applied to the wiring 12A, the MISFET Q
One of the p-type semiconductor regions 7 of p1 and Qp2 is fixed at the operating potential Vcc. The wiring 10B has a second
The wiring 12B formed in the wiring layer of the layer is electrically connected. This wiring 12B is a p-channel conductive type MISF
It is electrically connected to each gate electrode 6 of ETQp1 and ETQp2. The wiring 12C formed in the second wiring layer is electrically connected to the wiring 10C. Each of the wirings 12A, 12B, and 12C is formed of, for example, an aluminum film or an aluminum alloy film.

Each of the wirings 10E and 10F has a second
The wiring 12G formed in the wiring layer of the layer is electrically connected. A reference potential (for example, 0
[V]) Since Vss is applied, the MISFET Qn
3, the other n-type semiconductor region 8 of Qn4 is fixed to the reference potential Vss.

The wiring 12D formed in the second wiring layer is electrically connected to the gate electrode 6 of the MISFET Qn1, and the wiring 12D formed in the second wiring layer is connected to the gate electrode 6 of the MISFET Qn2. The wiring 12E is electrically connected, and the respective gate electrodes 6 of the MISFETs Qn3 and Qn4 have wirings 12F formed in a second wiring layer.
Are electrically connected.

The field insulating film 2 is formed outside one of the p-type semiconductor regions 7 of the MISFTs Qp1 and Qp2.
An n-type well region 3B whose periphery is defined by is defined. Since the wiring 10A is electrically connected to the n-type well region 3B, the operating potential V
The potential is fixed to cc.

The MISFETs Qn1, Qn2, Qn
3 and Qn4 are electrically isolated from each other by a p-type well region 4B as shown in FIGS. The wiring 10E formed in the first wiring layer is electrically connected to the p-type well region 4B.
Since the wiring 12G is electrically connected to E, the p-type well region 4B is fixed at the reference potential Vss.

As shown in FIG. 8, the n-type well region 4B is electrically connected to the p-type well region 4A which is a channel forming region of the MISFET Qn1, and the p-type well region 4A is a channel forming region of the n-channel conductive MISFET Qn2. The type well region 4A is electrically connected to the MISFET Qn
The p-type well region 4A, which is the channel formation region of No. 3, is electrically connected to the p-type well region 4A, which is the channel formation region of the MISFET Qn4.
That is, n-channel conductivity type MISFETs Qn1, Qn2,
Each of Qn3 and Qn4 is electrically separated by an n-type well region 3B electrically connected to these channel forming regions.

The p-type well region 4B has a reference potential Vss.
MISFETs Qn1, Qn2,
Each of the channel forming regions of Qn3 and Qn4 has a reference potential V
The potential is fixed to ss. That is, by fixing the potential of the p-type well region 4B, the potential of the channel forming region of each MISFET Qn electrically connected to the p-type well region 4B can be fixed.

Next, a specific configuration of the memory cell M will be described with reference to FIGS. 9 is a plan view of a main part of the memory cell unit 50, FIG. 10 is an enlarged plan view of a main part of FIG. 9, and FIG. 11 is a cross-sectional view taken along a line CC shown in FIG. FIG. 12 is a sectional view taken along line DD
FIG. 13 is a cross-sectional view taken along a line, and FIG. 13 is a plan view showing a layout of each semiconductor region in FIG. In FIGS. 9 to 12, the layers above the second-layer wiring are not shown for easy viewing.

As shown in FIGS. 10 and 11, the MI
Each of the SFETs (for driving) Qn7 and Qn8 is formed on the main surface of the semiconductor substrate 1. This MISFET Qn7,
Each of Qn8 mainly includes a p-type well region 4A as a channel forming region, a gate insulating film 5, a gate electrode 6, and a pair of n-type semiconductor regions 8 as a source region and a drain region.

In each of the MISFETs Qn7 and Qn8, the bottom of each of a pair of n-type semiconductor regions 8 serving as a source region and a drain region is buried in the buried insulating film 1B of the semiconductor substrate 1.
It is configured with a structure that comes into contact with the surface.

A wiring 10J formed in the first wiring layer is electrically connected to one n-type semiconductor region 8 of the MISFET Qn7 through a connection hole formed in the interlayer insulating film 9, and is connected to the other n-type semiconductor region 8. The wiring 10H formed in the first wiring layer is electrically connected to the n-type semiconductor region 8 through a connection hole formed in the interlayer insulating film 9.

The wiring 10K formed in the first wiring layer is electrically connected to one n-type semiconductor region 8 of the MISFET Qn8 through a connection hole formed in the interlayer insulating film 9, and The wiring 10I formed in the first wiring layer is electrically connected to the n-type semiconductor region 8 through a connection hole formed in the interlayer insulating film 9.

As shown in FIG. 10 and FIG.
Each of the SFETs (for load) Qp3 and Qp4 is formed on the main surface of the semiconductor substrate 1. This MISFET Qp3,
Each of Qp4 mainly includes an n-type well region 3A as a channel formation region, a gate insulating film 5, a gate electrode 6, and a pair of p-type semiconductor regions 7 as source and drain regions.

In each of the MISFETs Qp3 and Qp4, the bottom of each of a pair of p-type semiconductor regions 7 serving as a source region and a drain region is formed by a buried insulating film 1B of the semiconductor substrate 1.
It is configured with a structure that comes into contact with the surface.

A wiring 10 J is electrically connected to one p-type semiconductor region 7 of the MISFET Qp 3, and the other p-type semiconductor region 7 is connected to the first p-type semiconductor region 7 through a connection hole formed in the interlayer insulating film 9. Wiring 1 formed in the wiring layer of the first layer
0L is electrically connected. The MISFET Qp
4 is electrically connected to one p-type semiconductor region 7, and the other p-type semiconductor region 7 is connected to a first layer wiring through a connection hole formed in the interlayer insulating film 9. The wiring 10M formed in the layer is electrically connected.

The MISFETs (for transfer) Qn5, Qn6
Are formed on the main surface of the semiconductor substrate 1, although not shown in detail. The MISFETs Qn5 and Qn6
Are mainly a p-type well region 4A which is a channel forming region, a gate insulating film 5, a gate electrode 6, and a pair of n-type semiconductors which are a source region and a drain region, similarly to the above-described MISFETs Qn7 and Qn8. The region 8 is configured.

In each of the MISFETs Qn5 and Qn6, the bottom of each of a pair of n-type semiconductor regions 8 which are a source region and a drain region is buried in the buried insulating film 1B of the semiconductor substrate 1.
It is configured with a structure that comes into contact with the surface.

As shown in FIG. 10, the respective gate electrodes 6 of the MISFETs Qn8 and Qp4 are electrically connected to the wiring 10J via a wiring 12H formed in the second wiring layer. . The wiring 10
The gate electrode 6 of each of the MISFET Qn7 and the MISFET Qp3 is electrically connected to K via a wiring 12I formed in the second wiring layer.

Each of the wirings 10H and 10I has a wiring 1
2G is electrically connected, and a wiring 12A is electrically connected to each of the wirings 10L and 10M. That is, M
The other n-type semiconductor region 8 of each of the SIFETs Qn7 and Qn8 is fixed to a reference potential Vss, and the MISFET Q
The other p-type semiconductor region 7 of each of p3 and Qp4 is fixed at the operating potential Vcc.

A wiring 10J is electrically connected to one n-type semiconductor region 8 of the MISFET Qn5, and a data line (D) (not shown) is connected to the other n-type semiconductor region 8.
L1) are electrically connected, and the word line WL is integrated with the gate electrode 6 thereof. The MISFET Qn6
A wiring 10K is electrically connected to one of the n-type semiconductor regions 8, and a data line (DL2) (not shown) is electrically connected to the other n-type semiconductor region 8. Is integrated with a word line WL.

As shown in FIGS. 10 and 11, the MI
Each of the SFETs Qn5, Qn6, Qn7, Qn8 is electrically separated from each other by a p-type well region 4B. Although not shown in this p-type well region 4B,
Since the wiring 12G is electrically connected, the p-type well region 4B is fixed at the reference potential Vss.

As shown in FIG. 13, a p-type well region 4A, which is a channel forming region of MISFET Qn5, is electrically connected to the p-type well region 4B.
P-type well region 4A which is a channel forming region of TQn7
Are electrically connected, and the p-type well region 4A, which is a channel forming region of the MISFET Qn6, is electrically connected;
The p-type well region 4A, which is a channel forming region of the MISFET Qn8, is electrically connected. That is, MISF
Each of ETQn5, Qn6, Qn7, Qn8 is electrically isolated by a p-type well region 4B electrically connected to these channel forming regions.

The p-type well region 4B has a reference potential Vss.
MISFETs Qn5, Qn6,
Each of the channel forming regions of Qn7 and Qn8 has a reference potential V
The potential is fixed to ss. That is, by fixing the potential of the p-type well region 4B, the potential of the channel forming region of each MISFET Qn electrically connected to the p-type well region 4B can be fixed.

As shown in FIGS. 10 and 12, the MI
Each of the SFETs Qp3 and Qp4 is an n-type well region 3B
Are electrically separated from each other. Although not shown, since the wiring 12A is electrically connected to the n-type well region 3B, the n-type well region 3B is fixed at the operating potential Vcc.

As shown in FIG. 13, the n-type well region 3B is electrically connected to the n-type well region 3A, which is a channel forming region of the MISFET Qp3, and is connected to the channel forming region of the p-channel conductive type MISFET Qp4. A certain n-type well region 3A is electrically connected. That is, each of the MISFETs Qp3 and Qn4 is an n-type well region 3 electrically connected to these channel forming regions.
B electrically separates.

The n-type well region 3B has an operating potential Vcc.
, The respective channel forming regions of the MISFETs Qp3 and Qp4 are fixed at the operating potential Vcc. That is, by fixing the potential of the n-type well region 3B, the potential of the channel forming region of each MISFET Qp electrically connected to the n-type well region 3B can be fixed.

As shown in FIG. 10 and FIG.
Each of the SFETs Qn7 and Qn8 is a field insulating film 2
MISFETs Qp3 and Qp4 are electrically separated from each other. The MISFETs Qn7 and Qn7
The p-type well region 4B between n8 and n8 is electrically isolated from the n-type well region 3B by the field insulating film 2.

As shown in FIG. 13, each of the MISFETs Qn5, Qn6, Qn7, and Qn8 of the memory cell M is electrically connected to each of the MISFETs Qn5, Qn6, Qn7, and Qn8 of the other memory cell M by the p-type well region 4A. MISFET Q of the memory cell M
Each of p3 and Qp4 is formed by the n-type well region 3A.
It is electrically separated from each of the MISFETs Qp3 and Qp4 of the other memory cell M. That is, in the memory cell section 50, each MISFET Qn of one memory cell M and each MISFET Qn of the other memory cell M are connected to the p-type well region 4 electrically connected to these channel forming regions.
B, each MIS of one memory cell M is electrically separated.
FET Qp and each MISFET Qp of the other memory cell M
Is n electrically connected to these channel forming regions.
It is electrically isolated at the mold well region.

As described above, according to the present embodiment, the following operational effects can be obtained.

(1) Multiple MISFEs of n-channel conductivity type
An SRAM having a TQn (or a p-channel conductivity type MISFET Qp), wherein the plurality of n-channel conductivity types M
Each of the ISFETs Qn is embedded in the buried insulating film 1 of the semiconductor substrate 1.
A plurality of n-channel conductive MISFETs each having a structure in which a bottom of a source region (n-type semiconductor region 8) and a bottom of a drain region (n-type semiconductor region 8) are in contact with the surface of B;
Each of Qn is separated by a p-type well region 4B electrically connected to these channel forming regions (p-type well region 4A).

According to this structure, the pn junction capacitance (parasitic capacitance) added to the source region and the drain region can be reduced by an amount corresponding to the area of the bottom of the source region and the drain region. MISFETQ
The switching speed of n can be increased. Further, by fixing the potential of the p-type well region 4B,
Since the channel forming region of the n-channel conductivity type MISFET Qn electrically connected to the p-type well region 4B can be fixed in potential, each n-channel conductivity type MISFET QSF
There is no need to provide a power supply contact region for each ETQn, and the area occupied by each n-channel conductivity type MISFET Qn can be reduced. As a result, it is possible to achieve high speed and high integration of the SRAM having the plurality of n-channel conductivity type MISFETs Qn.

Further, since the space between adjacent elements is narrowed,
Characteristic differences between adjacent n-channel conductivity type MISFETs Qn can be reduced.

(2) Multiple n-channel conductivity type MISFE
An SRAM having a TQn and a plurality of p-channel conductive MISFETs Qp, wherein each of the plurality of n-channel conductive MISFETs Qn is embedded in a buried insulating film 1 of a semiconductor substrate 1.
B has a structure in which the bottom of the source region (n-type semiconductor region 8) and the bottom of the drain region (n-type semiconductor region 8) are in contact with each other, and each of the plurality of p-channel conductive MISFETs Qp is The buried insulating film 1B has a structure in which the bottoms of a source region (p-type semiconductor region 7) and a drain region (p-type semiconductor region 7) are in contact with the surface of the buried insulating film 1B. Separated by an n-type well region 4B electrically connected to these channel formation regions (n-type well regions 4A), each of the plurality of p-channel conductivity type MISFETs Qp is separated from these channel formation regions (p-type well regions 4A). 3A) and are separated by a p-type well region 3B which is electrically connected.

With this configuration, each n-channel conductivity type MI
SFET Qn and each p-channel conductivity type MISFET Qp
And the occupation area of each n-channel conductivity type MISFET Qn and each p-channel conductivity type MISFET Qp can be reduced.
Higher speed and higher integration of the SRAM having n and a plurality of p-channel conductivity type MISFETs Qp can be further achieved.

(3) The p-type well region 4B and the n-type well region 3B are separated by the field insulating film 2 formed on the surface of the buried insulating film 1B of the semiconductor substrate 1. With this configuration, p-type well region 4B and n-type well region 3
Since the pn junction with B can be eliminated, it is possible to prevent a leak current generated between the p-type well region 4B and the n-type well region 3B.

(4) MISFET Qn of n-channel conductivity type
Cell part 5 in which a plurality of memory cells M having
0 and a peripheral circuit section 51 in which a plurality of sense circuits (peripheral circuits) SE having n channel conductivity type MISFETs Qn are arranged.
A and the memory cell unit 50
In the peripheral circuit section 51A, an n-channel conductivity type MISFET Qn is formed on the surface of the buried insulating film 1B of the semiconductor substrate 1 by a source region (n-type semiconductor region 8) and a drain region.
(n-type semiconductor region 8) with a structure in which the bottoms are in contact with each other;
Between the memory cells M of the memory cell portion 50, the n-channel conductivity type MISFET Qn of one memory cell M and the n-channel conductivity type MISFET Qn of the other memory cell M
n and the channel forming region (p-type well region 4).
A) is separated by a p-type well region 4B which is electrically connected to the n-channel conductivity type MISF of one of the sense circuits SE between the sense circuits SE of the peripheral circuit portion 51A.
ETQn and n-channel conductivity type M of the other sense circuit SE
ISFET Qn and embedded insulating film 1 of semiconductor substrate 1
B is separated by the field insulating film 2 formed on the surface of B.

According to this configuration, in the sense circuit SE, the side surfaces of the source region and the drain region of the n-channel conductivity type MISFET Qn can be brought into contact with the field insulating film 2, which corresponds to the area of the side surfaces of the source region and the drain region. Accordingly, the pn junction capacitance (parasitic capacitance) added to the source region and the drain region can be reduced. As a result, the switching speed of the n-channel conductivity type MISFET Qn of the sense circuit SE can be further increased.

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

[0086]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

The speed and integration of a semiconductor integrated circuit device having a plurality of MISFETs can be increased.

[Brief description of the drawings]

FIG. 1 is a chip layout diagram showing a schematic configuration of an SRAM according to an embodiment of the present invention.

FIG. 2 is a main block diagram of the SRAM.

FIG. 3 is an equivalent circuit diagram of a sense circuit mounted in a peripheral circuit section of the SRAM.

FIG. 4 is an equivalent circuit diagram of a memory cell mounted on a memory unit of the SRAM.

FIG. 5 is a plan view of a main part of a peripheral circuit section of the SRAM.

6 is a sectional view taken along the line AA shown in FIG.

FIG. 7 is a sectional view taken along the line BB shown in FIG. 5;

FIG. 8 is a plan view showing a layout of each semiconductor region in FIG. 5;

FIG. 9 is a plan view of a main part of a memory unit of the SRAM.

FIG. 10 is an enlarged plan view of a main part of FIG. 9;

11 is a cross-sectional view taken along the line CC shown in FIG.

12 is a sectional view taken along the line DD shown in FIG.

FIG. 13 is a plan view showing a layout of each semiconductor region in FIG. 9;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor base, 1B ... buried insulating film, 2 ... field insulating film, 3A ... n-type well region, 3B ... n-type well region,
4A: p-type well region, 4B: p-type well region, 5: gate insulating film, 6: gate electrode, 7: p-type semiconductor region, 8
... n-type semiconductor region, 9 ... interlayer insulating film, Qn1, Qn2
Qn3, Qn4, Qn5, Qn6, Qn7, Qn8 ... n
Channel conductivity type MISFET, Qp1, Qp2, Qp
3, Qp4... P-channel conductivity type MISFET.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/786 H01L 29/78 621

Claims (4)

[Claims] 1. A semiconductor integrated circuit device having a plurality of first conductivity type MISFETs, wherein said plurality of first conductivity type MISFETs are provided.
Each of the ISFETs has a structure in which the bottoms of the source region and the drain region are in contact with the surface of the buried insulating film of the semiconductor substrate, and each of the plurality of first conductivity type MISFETs is electrically connected to these channel forming regions. A semiconductor integrated circuit device, which is separated by a connected second conductivity type well region. 2. A semiconductor integrated circuit device having a plurality of first conductivity type MISFETs and a plurality of second conductivity type MISFETs, wherein each of the plurality of first conductivity type MISFETs is a surface of a buried insulating film of a semiconductor substrate. A plurality of MISFETs of the second conductivity type each having a bottom portion of a source region and a drain region in contact with a surface of a buried insulating film of a semiconductor substrate. And the plurality of first conductivity type MISFEs
T are separated by a second conductivity type well region electrically connected to these channel forming regions, and the plurality of second conductive regions are separated from each other.
A semiconductor integrated circuit device, wherein each of the conductivity type MISFETs is separated by a first conductivity type well region electrically connected to these channel forming regions. 3. The semiconductor device according to claim 2, wherein the second conductivity type well region and the first conductivity type well region are separated by a field insulating film formed on a surface of a buried insulating film of the semiconductor substrate. The semiconductor integrated circuit device according to claim 2. 4. A memory cell section in which a plurality of memory cells each having a first conductivity type MISFET are arranged, and a first conductivity type MISFET is provided.
1. A semiconductor integrated circuit device comprising: a peripheral circuit section in which a plurality of peripheral circuits having SFETs are arranged; wherein the memory cell section and the peripheral circuit section have a first conductivity type MISF
ET has a structure in which the bottom of a source region and a drain region are in contact with the surface of a buried insulating film of a semiconductor substrate, and between the memory cells of the memory cell portion, the first conductivity type MISFET of one of the memory cells is connected to the other. Of the first memory cell
The conductivity type MISFET is separated by a second conductivity type well region electrically connected to these channel formation regions, and between the peripheral circuits of the peripheral circuit portion, the first conductivity type MISFET of one of the peripheral circuits and the other are formed. A semiconductor integrated circuit device, wherein a first conductivity type MISFET of a peripheral circuit is separated by a field insulating film formed on a surface of a buried insulating film of the semiconductor substrate.