JPH1093406A - Timing generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize a timing signal by providing a sliding resistor on the input side of the smoothing circuit of a phase comparator, detecting the fluctuation of a delay time and adjusting it to a cancelling direction to reduce the variation of the shifting quantity of timing. SOLUTION: An offset adjusting means 15 is provided for the output side of a phase comparator. Then the sliding resistors VR is connected between terminals TA and TB on the inputting side of a smoothing circuit 12c provided for the phase comparator, and its slider is connected to a negative electrode -V. The positive and negative balance point between the terminals TA and TB is adjusted by sliding the position of the slider. Consequently, when an offset error is generated in a phase comparing result, the means 15 is adjusted so as to cancel the offset error. The fluctuation of the delay time of a delay circuit is detected through the use of the phase comparator to adjust in the direction of cancelling the fluctuation so that the shifting quantity of timing does not very much and the timing signal is stabilized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing generator which can be used, for example, in an IC tester.

[0002]

2. Description of the Related Art When testing whether or not an IC operates normally, one of the test items is to shift the timing of a signal applied to an IC under test slightly and measure a range of a timing at which the IC normally operates. is there. In order to perform such a test, the IC test apparatus is provided with a timing generator which can generate the clock generation timing with a slight shift.

FIG. 4 shows a configuration of a conventional timing generator. The timing generator includes a minute delay circuit 10;
A selection circuit 20 for selecting and extracting any one of the pulses slightly delayed by the minute delay circuit 10, a decoder 30 for setting selection conditions for the selection circuit 20, and a clock delay time varying in units of one clock cycle Counting means 40
It is constituted by and.

The minute delay circuit 10 includes a delay circuit 11 in which delay elements DY each formed of a single circuit including a semiconductor active element are cascaded in multiple stages, a pulse input to the delay circuit 11 and a pulse passed through the delay circuit 11. And a control for generating a control voltage for controlling the delay amount of each delay element DY such that the phase comparison result of the phase comparator 12 always converges to a predetermined value (generally 0). It comprises a voltage generator 14 and a filter 13 for determining a frequency characteristic for stably operating a closed loop constituted by the delay circuit 11, the phase comparator 12, and the control voltage generator 14.

The delay circuit 11 is generally an IC having a CMOS structure.
And a single circuit such as a buffer amplifier or an inverter formed in the IC is used as the delay element DY. I
When a circuit such as a buffer amplifier or an inverter formed inside C is used as a delay element, there is a drawback that a delay time fluctuates due to a temperature fluctuation. For this purpose, a phase comparator 12, a filter 13, and a control voltage generator 14 are provided. A closed loop is formed by these circuits, and the delay time is always maintained at a constant value.

That is, as shown in FIG. 5, the delay time .tau.
Is set to a delay time corresponding to one cycle of. Therefore, one of the clocks input to the phase comparator 12 is input with a delay of one cycle, and thus is input to both input terminals with substantially the same phase. If the delay time of the delay circuit 11 is stabilized at a time corresponding to one cycle of the clock CLK, the phase comparison result of the phase comparator 12 is maintained at zero. However, when the temperature changes, the delay time of each delay element DY becomes longer. Change. Since the phase of the two pulses input to the phase comparator 12 is shifted due to the change in the delay time, a phase comparison output corresponding to the phase difference is obtained, and the phase comparison output is supplied to the control voltage generator 14 to generate a voltage. And converts the voltage signal into a delay circuit 11
, The delay time of each delay element DY can be controlled, and the phase difference can always be kept at zero. For example, when the temperature rises and the delay time of the delay circuit 11 changes in the direction of delay, the power supply voltage applied to the delay circuit 11 is changed in the rising direction to control the delay time to be shortened.

As described above, the delay element DY is used as an IC.
The configuration is such that the delay time is stably maintained while using (the delay time changes with temperature fluctuation), and the delay time of the delay pulse extracted from each stage is stably maintained. The selection circuit 20 selects one of the delay pulses extracted from between the stages of the delay circuit 11, and generates a clock with a pitch that minimizes the delay time T of one delay element DY from the input clock CLK. taking out arbitrary time T _n-delayed pulse obtained by dividing one period of CLK in number n of delay elements DY.

The decoder 30 provides gates G _{1 to} G _n constituting the selection circuit 20 by giving a desired delay time.
Is provided for inputting an H logic signal to any one of them and outputting a timing pulse from a gate to which the H logic is applied. As the counting means 40, for example, a down counter can be used. The set value corresponding to the delay time is set in the down counter. When the down counter counts the number of clocks CLK corresponding to the set value, its output becomes H logic. By providing this logical H signal to the gate G ₁ ~G _n, it can give H logic gates G ₁ ~G _n at timing period delay of set clock CLK, by the decoder 30 to the timing after When a delay pulse is supplied to any of the selected gates G _{1 to} G _n , the delay pulse is extracted from that gate, and
The output terminal 21 can output a pulse delayed by an arbitrary time.

[0009]

In the above description, it has been described that the phase comparison result of the phase comparator 12 always converges to a state of zero. However, in practice, some offset is applied to the output side of the phase comparator 12. (Error voltage) occurs. This offset occurs due to, for example, a difference in the length of the wiring on the input side of the phase comparator 12, a difference in the cross-sectional area of the wiring, or a difference in the operation speed of the active element used in the phase comparator. I do.

This will be described with reference to FIG. FIG. 6 schematically shows a specific circuit configuration of the phase comparator 12. The phase comparator 12 has two flip-flops FF
₁ and FF ₂ and switch elements SW ₁ and SW that are turned on and off by the flip-flops FF ₁ and FF _2
2 , a gate 12A for resetting the flip-flops FF ₁ and FF ₂ and a delay element 12B.

[0011] flip-flop FF ₁ and FF ₂ are used is D-type flip-flop, the data input terminal D is given H logic. The respective clock input terminal is connected to the phase comparison input terminal IN ₁ and IN _2, pulses P ₁ and P ₂ to be phase comparison is given. Switching element SW ₁ and SW ₂ are always stands by in a state of ON. When the pulse P _1, P ₂ to the flip-flop FF ₁ and FF ₂ is provided, the flip-flop FF ₁ and FF ₂ are both read logic H, the output terminal Q is inverted to H logic. Switching element SW ₁ and SW ₂ are switched to the OFF state by the H logic signal. Flip-flop FF ₁ and FF ₂ are both H
When the logic is output, the gate 12A detects the state and outputs the flip-flop F through the delay circuit 12B.
Providing a reset signal to F ₁ and FF _2.

In this manner, the input pulse P₁ When
P_Two If one of them rises earlier than the other,
Switch element SW only for difference₁ Or SW_Two Turned off
Time is longer and the output terminal T_AAnd T_BOutput to
Pulse P₁₁Or P_{twenty two}Of the output terminal T
_AAnd T_BPulse P output to₁₁And P_{twenty two}And add
The addition result is smoothed by the smoothing circuit 12C and taken out.
Output terminal T_AAAnd T _BBCan get DC voltage
You.

[0013] The pulse width of the pulse P ₁₁ is the input pulse P ₂ If delayed from the input pulse P ₁ to be output to the output terminal T _AA when the connection relation the polarity of the DC voltage to be shown P
_Since it is longer than _22, the potential on the output terminal T _AA side becomes higher than the potential on the T _BB side, and becomes positive polarity. Input when the pulse P ₂ is the flow advances from the input pulse P ₁ phase when the potential of the output terminal T _BB side becomes higher than the potential of the T _AA side a negative polarity.

As described above, the phase comparator 12 has a flip
Flop FF₁ And FF_Two And switch element SW₁ And S
W_Two Are used, these flip-flops F
F₁And FF_Two And switch element SW₁ And SW_Two Operating speed
If there is a difference in degree (time required for reversal), the operating speed
An offset occurs due to the difference in degrees. For example, Flick
Flop FF_Two FF₁ To flip
If the time is Δφ longer than the required time (lags by Δφ)
In this case, as shown in FIG._BPal to output to
SU_{twenty two}Is the output terminal T_AAPulse P output to₁₁More pal
In this case, a phase error occurs in the direction in which the pulse width becomes narrower by Δφ. This
Is the control voltage V_CDelay time T_DYAgainst
As shown in FIG. 8, the delay time offset error ΔT _Pdage
Appear. In addition, these switch elements, flip-flops
Rop, IN₁, IN_Two Interconnect capacitance is very small
The difference produces a similar error.

When the delay time offset error ΔT _Pd is distributed to one delay element DY constituting the delay circuit 11, the value thereof is extremely small as ΔT _Pd / n. However, if n delay elements DY are connected in series, the sum of the errors becomes n. If the delay time of the delay element DY is increased one by one in the process of gradually shifting the phase of the signal applied to the IC under test, the counting means 4 reaches the maximum serial value.
After returning to the delay time of one delay element DY after carrying the delay time of one pulse to 0, the error value suddenly changes from the maximum value ΔT _Pd to ΔT _Pd / n. .

FIG. 9 is an enlarged view of this state. As shown in FIG. 9, each exceeding the delay time delay setting time for setting the timing generator corresponds to the period of the clock CLK tau, since the error value is suddenly changed from [Delta] T _Pd on [Delta] T _Pd / n,
There is a disadvantage that the error changes in a saw-tooth shape and the linearity deteriorates. Particularly, when testing a high-speed IC, there is an inconvenience that the reliability of the test is reduced due to the deterioration of the linearity.

An object of the present invention is to provide a timing generator capable of setting a delay time offset error to a zero state.

[0018]

According to the present invention, the delay time of a delay circuit is compared by a phase comparator, the variation of the delay time is detected based on the phase comparison result, and the delay is set in a direction to cancel the variation of the delay time. In a timing generator for controlling a time to stabilize a delay time and generate a stable timing signal, an offset adjusting means is provided on an output side of a phase comparator, and the offset error can be set to 0 by the offset adjusting means. It is configured as follows.

According to the configuration of the present invention, by providing the offset adjusting means, the offset error generated in the phase comparator or the like can be set to zero. Therefore, the relationship between the timing setting time and the actual delay time can be aligned on a straight line. That is, the linearity of the change characteristic of the delay time can be improved. As a result, there is an advantage that a test can be performed with high reliability even with a high-speed IC.

[0020]

FIG. 1 shows an embodiment of the present invention.
You. Parts corresponding to those in FIG. 4 are denoted by the same reference numerals. This
According to the invention, an offset adjusting means is provided on the output side of the phase comparator 12.
A step 15 is provided. This offset adjusting means 15 is adjusted.
As a result, the pulse P input to the phase comparator 12 is₁ 
And P_Two If the phase difference of
Force terminal T _AAnd T_BStatus of the phase comparison output to
Can be set to

2 and 3 show a specific embodiment of the offset adjusting means 15. FIG. Input side of the terminal T _A and T of the smoothing circuit 12C provided in the phase comparator in the embodiment shown in FIG. 2
A case is shown in which a slide resistor VR is connected between _B and the slider is connected to a negative power supply -V. It is possible to adjust the positive and negative balance point between the output terminals T _A and T _B by sliding the position of the slider. Therefore, when an offset error occurs in the phase comparison result, the offset adjusting means 15 may be adjusted so as to cancel the offset error.

FIG. 3 shows a case where the offset error can be automatically adjusted to zero by a controller such as a microcomputer. To this end, one of the terminals T _{A and} T _B is connected to a negative voltage source via a fixed resistor R, and the other is connected to a current suction circuit 15A, which is provided along with the current suction circuit 15A. The current value of the current attraction circuit 15A is set by giving the current attraction value to the digital-analog converter DA, and the current value is controlled to adjust the zero balance between the output terminals T _A and T _B. Shows the case where it is configured.

In either case of FIG. 2 or FIG. 3, even if an offset error occurs in the phase comparison result, the offset error can be adjusted to zero.

[0024]

As described above, according to the present invention, the fluctuation of the delay time of the delay circuit is detected using the phase comparator, and the delay time of the delay circuit is controlled in a direction to cancel the fluctuation of the delay time. In the timing generator having a configuration for generating a stable timing signal, the offset adjusting means 15 is provided on the output side of the phase comparator.
Even if an offset error occurs on the output side of No. 2, the offset error can be adjusted to zero by the offset adjusting means 15.

Therefore, even if the timing of the timing signal output from the timing generator is slightly shifted, the inconvenience that the amount of the timing shift greatly changes on the way does not occur. Therefore high-speed IC
Is also advantageous in that a reliability IC test can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention.

FIG. 2 is a connection diagram for explaining a specific embodiment of a main part of the present invention.

FIG. 3 is a connection diagram similar to FIG. 2;

FIG. 4 is a block diagram for explaining a conventional timing generator.

FIG. 5 is a waveform chart for explaining the operation of FIG. 4;

FIG. 6 is a connection diagram for explaining in detail the configuration of a phase comparator used in the timing generator shown in FIG. 4;

FIG. 7 is a waveform chart for explaining inconvenience occurring in the phase comparator shown in FIG. 6;

FIG. 8 is a graph for explaining a delay time offset error generated due to the inconvenience described in FIG. 7;

FIG. 9 is a graph for explaining the linearity of the delay time generated by the delay time offset error shown in FIG. 8;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Micro delay circuit 11 Delay circuit 12 Phase comparator 13 Filter 14 Control voltage generator 15 Offset adjustment means 20 Selection circuit 30 Decoder 40 Counting means

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[Procedure amendment]

[Submission date] October 4, 1996

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] Fig. 9

[Correction method] Change

[Correction contents]

FIG. 9

Claims (3)

[Claims] 1. A. First Embodiment B. a delay circuit configured by cascading delay elements configured by a single circuit including a semiconductor active element; B. a phase comparator for detecting a phase difference between an input clock supplied to the delay circuit and an output pulse output from the delay circuit; A control voltage generator that controls a power supply voltage applied to the delay circuit so that the phase comparison result output from the phase comparator always converges to a predetermined value, and maintains a delay time of the delay circuit at a constant value; E. offset adjusting means for removing an offset component generated on the output side of the phase comparator; And a selector circuit for selecting and extracting any one of the pulses extracted from each stage of the delay element constituting the delay circuit and slightly delayed from the timing of the input clock of the delay circuit. Timing generator. 2. The timing generator according to claim 1, wherein said offset adjusting means is a slide resistor connected between input-side terminals of a smoothing circuit provided in said phase comparator, and a slide terminal of said slide resistor. And a negative power supply for deviating the voltage to a negative potential. 3. The timing generator according to claim 1, wherein said offset adjusting means includes a fixed resistor connected to one of the input-side terminals of a smoothing circuit provided in said phase comparator; A timing generator comprising: a negative power supply for displacing the terminal to a negative potential; a current suction circuit connected to the other terminal; and a digital-analog converter for setting a current value of the current suction circuit. .