JPH1098039A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a method of manufacturing a semiconductor device capable of stably forming embedded wiring by using a high-pressure reflow method. SOLUTION: A connection hole 4 and a wiring groove 5 are provided in an interlayer insulating film 3.
After forming a dual damascene structure, a TiN / Ti film 6 is formed on the entire surface, and an upper Al alloy layer 7 is formed thereon as a wiring material for forming a buried wiring at least three times the width of the wiring groove 5. Then, a bridge shape is formed at the wiring groove 5 and the connection hole 4. Next, high pressure reflow is performed using an inert gas to fill the wiring groove 5 and the connection hole 4 with an Al alloy. Thereafter, polishing is performed by a CMP method or the like until the interlayer insulating film 3 is exposed, thereby forming a buried wiring inside the wiring groove 5. Further, in order to stably form a bridge shape by a wiring material at a connection portion between a wiring groove and a hole for forming a pad at a terminal of an embedded wiring,
A dummy pattern is formed at or near this connection portion, or a plurality of connection holes are formed at the bottom of the pad formation hole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method suitable for application to formation of an embedded wiring using a high-pressure reflow method.

[0002]

2. Description of the Related Art Due to the high integration of LSIs, internal wirings are becoming finer and multilayered, and accordingly, it is important to develop flattening technology when forming wirings, process fine wirings, and secure reliability. It has become. As one of the solutions to these problems, an embedded wiring technique is being studied. Among these embedded wiring technologies, a so-called Dual Damascene method (also referred to as a Double Damascene method), which can reduce the cost, has attracted attention. One example of the dual damascene method is shown in FIGS.

In this dual damascene method, FIG.
As shown in FIG. 4, a lower Al alloy wiring 102 is formed on a substrate 101 on which elements are formed in advance and the surface of which is covered with an interlayer insulating film (both not shown). After the interlayer insulating film 103 is formed, a resist pattern 104 having a predetermined shape is formed on the interlayer insulating film 103 by a lithography process. next,
As shown in FIG. 15, using the resist pattern 104 as a mask, the interlayer insulating film 103 is etched by a reactive ion etching (RIE) method or the like to form a connection hole 105. After that, the resist pattern 104 is removed.

[0006] Next, as shown in FIG.
A resist pattern 106 having a predetermined shape is formed on the substrate 03 by a lithography process. Next, as shown in FIG.
Using the resist pattern 106 as a mask, the interlayer insulating film 103 is etched by RIE or the like, and
7 is formed. Thereafter, as shown in FIG. 18, the resist pattern 106 is removed. Thereby, the connection hole 10
5 and the wiring groove 107 are formed. These connection holes 1
The structure composed of the wiring 05 and the wiring groove 107 is called a dual damascene structure.

As a method of embedding a wiring material in the wiring grooves 107 and the connection holes 105 formed in the interlayer insulating film 103, a reflow method has been conventionally used. The high-pressure reflow method which is excellent in embedding characteristics is being studied.

A method of forming a buried wiring by using this high-pressure reflow method to bury, for example, an Al alloy as a wiring material in the wiring groove 107 and the connection hole 105 of the dual damascene structure will be described.

[0009] First, as shown in FIG. 19, after forming the connection holes 105 and the wiring grooves 107 in the interlayer insulating film 103 as described above, a titanium (Ti) film and a nitride A titanium (TiN) film is sequentially formed, and a TiN / Ti film 108 as a base barrier metal is formed. Subsequently, an upper Al alloy layer 109 is formed on the entire surface in a high vacuum. At this time, the upper Al alloy layer 109 forms the wiring groove 107 and the connection hole 105.
So that the void 110 remains therein (hereinafter, this state is referred to as a bridge shape). The thickness of the upper Al alloy layer 109 is usually selected to be about twice the width of the wiring groove 107.

Next, the entire substrate 101 is heated to near the melting point of the Al alloy in a high-pressure reflow furnace evacuated to a high vacuum to melt or soften the upper Al alloy layer 109. For example, by introducing an inert gas such as argon (Ar) at a high pressure, the upper surface of the upper Al alloy layer 109 is pressurized, and the voids 110 are reduced. In this manner, as shown in FIG.
7 and the inside of the connection hole 105 are completely filled with an Al alloy.

Thereafter, for example, CMP (Chemical Mechani)
cal Polish) method or the like until the interlayer insulating film 103 is exposed until the upper Al alloy layer 109 and the TiN / Ti film 10 are exposed.
8 is polished to remove the upper Al alloy layer 109 and the TiN / Ti film 108 other than the wiring groove 107 and the connection hole 105. As a result, as shown in FIG. 21, a buried wiring 111 as an upper wiring is formed in the wiring groove 107 through the connection hole 105 to form the lower Al alloy wiring 10.
2 is formed.

In the above-described method of forming a buried wiring having a dual damascene structure using a high-pressure reflow method, the formation of the upper wiring, the global flattening of the upper wiring, and the filling of the wiring material into the connection holes are performed simultaneously. This is very advantageous in reducing the cost for forming the multilayer wiring. Furthermore, since the wiring material used for the upper wiring and the material filled in the connection holes are the same, there is an advantage that the reliability is high.

[0011]

However, the above-mentioned conventional method for forming an embedded wiring using the high-pressure reflow method has the following problems.

That is, as is apparent from the above-described principle of embedding by the high-pressure reflow method, in order to fill and embed the wiring material into the wiring grooves 107 and the connection holes 105, a high-pressure reflow furnace is not required. Before introducing the active gas, it is necessary to cover the upper portions of the wiring grooves 107 and the connection holes 105 with a wiring material to form a bridge shape in which the voids 110 are left. However, actually,
As shown in FIG. 22, the wiring material may not be connected at the portion of the connection hole 105, and a bridge shape may not be formed.
In such a case, even if the upper surface of the upper Al alloy layer 109 is pressurized with a high-pressure inert gas, the wiring material cannot be sufficiently filled in the wiring grooves 107 and the connection holes 105. Also, compared to the case where the high-pressure reflow method is applied only to the filling of the connection holes in the normal wiring structure,
In the above-described conventional method of forming a buried interconnect, this problem becomes remarkable because a bridge shape must be formed in the portion of the wide interconnect trench 107.

As described above, when the high-pressure reflow method is applied to the formation of the buried wiring, a technique for stably forming the bridge shape is important for stabilizing the burying.

Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which a bridge shape can be formed stably, so that a buried wiring can be formed stably using a high-pressure reflow method. It is in.

[0015]

According to a first aspect of the present invention, there is provided a method of manufacturing a buried interconnect using a high-pressure reflow method. The wiring material is formed in a film thickness three times or more the width of the wiring.

In the first aspect of the present invention, typically, a wiring material for forming a buried wiring is formed to a thickness of 3 to 4.5 times the wiring width.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a buried wiring is formed by using a high-pressure reflow method. A dummy pattern is formed at a portion connected to the hole or in the vicinity thereof.

In one embodiment of the second aspect of the present invention, the dummy pattern has substantially the same height as the depth of the hole for forming the pad.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which an embedded wiring is formed by using a high-pressure reflow method, wherein a plurality of connection holes are formed at the bottom of the pad forming hole at the end of the embedded wiring. Is formed.

In one embodiment of the third invention of the present invention, a plurality of connection holes are formed at substantially the same depth as the connection holes formed at the bottom of the wiring groove for forming the buried wiring.

In a preferred embodiment of the third invention of the present invention, a plurality of connection holes are formed on the entire bottom surface of the hole for forming the pad.

In the present invention, as a wiring material for forming a buried wiring, for example, aluminum (Al), copper (Cu), silver (Ag), gold (Au) or an alloy thereof is used.

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, the wiring material for forming the buried wiring is formed to a film thickness three times or more the width of the wiring. Accordingly, a bridge shape can be stably formed in the wiring groove portion. Therefore, by performing high-pressure reflow thereafter, the wiring material can be reliably embedded in the wiring groove.

In the method of manufacturing a semiconductor device according to the second or third aspect of the present invention having the above-described structure, a wiring groove for forming a buried wiring and a hole for forming a pad at a terminal of the buried wiring are provided. By forming a dummy pattern at or near the connection portion of the wiring, or by forming a plurality of connection holes at the bottom of the pad formation hole at the end of the embedded wiring, the wiring material for forming the embedded wiring is reduced. When the film is formed, a bridge shape can be stably formed also at a connection portion between a wiring groove for forming a buried wiring and a hole for forming a pad at the end of the buried wiring where the width changes greatly. Therefore, by performing high-pressure reflow after that, the wiring material can be reliably buried also in the connection portion between the wiring groove for forming the buried wiring and the hole for forming the pad at the end of the buried wiring.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 4 show a method for manufacturing a semiconductor device according to a first embodiment of the present invention,
In particular, a method for forming a buried wiring as an upper layer wiring will be described.

In the first embodiment, first, as shown in FIG. 1, an element is formed in advance, and a lower layer Al is formed on a Si substrate 1 whose surface is covered with an interlayer insulating film (both not shown). After forming the alloy wiring 2, an interlayer insulating film 3 such as a silicon oxide (SiO ₂ ) film is formed so as to cover the lower Al alloy wiring 2. Next, a dual damascene structure is formed in the interlayer insulating film 3. That is, after a resist pattern (not shown) having a predetermined shape is formed on the interlayer insulating film 3 by a lithography process, the interlayer insulating film 3 is etched by, for example, RIE using the resist pattern (not shown) as a mask. The connection hole 4 is formed. Thereafter, the resist pattern is removed. Next, after a resist pattern (not shown) having a predetermined shape is formed on the interlayer insulating film 3 by a lithography process, the interlayer insulating film 3 is etched by, for example, the RIE method using the resist pattern as a mask. Form.
Thereafter, the resist pattern is removed. Through the above steps, a dual damascene structure is formed. here,
The diameter of the connection hole 4 is, for example, 0.35 μm, and the depth is, for example, 1.
0 μm. The width of the wiring groove 5 is, for example, 0.4 μm.
m and the depth are, for example, 0.5 μm.

Next, as shown in FIG. 2, for example, in a high vacuum, a Ti film having a thickness of, for example, 20 nm and a TiN film having a thickness of, for example, 50 nm are sequentially formed on the entire surface by magnetron sputtering. A TiN / Ti film 6 is formed as a base barrier metal. As an example of sputtering conditions for forming the Ti film, Ar is used as an atmosphere gas, the flow rate is 100 sccm, the pressure is 0.4 Pa, the DC power is 5 kW, and the substrate heating temperature is 15
0 ° C. As an example of sputtering conditions for forming the TiN film, a mixed gas of Ar and nitrogen (N ₂ ) is used as an atmosphere gas, and the flow rates of these Ar gas and N ₂ gas are 30 sccm and 80 sc, respectively.
cm, pressure 0.4 Pa, DC power 5 kW, substrate heating temperature 150 ° C.

Subsequently, for example, in a high vacuum,
An upper Al alloy layer 7 containing, for example, 0.5% of Cu is formed on the TiN / Ti film 6 by magnetron sputtering. Here, the thickness of the upper Al alloy layer 7 is selected to be at least three times the width of the wiring groove 5. Specifically, for example, assuming that the width of the wiring groove 5 is 0.4 μm, the thickness of the upper Al alloy layer 7 is 1200 nm, which is three times the width. As described later, since the upper Al alloy layer 7 other than the wiring groove 5 and the connection hole 4 is removed in a later step, unlike the case of a normal wiring structure, the upper Al alloy layer 7 There is no limitation on the film thickness, but the film formation time and CM of the next process
From the viewpoint of preventing the time required for P from becoming too long, the thickness of the upper Al alloy layer 7 is preferably selected so as not to exceed 4.5 times the width of the wiring groove 5. As an example of sputtering conditions for forming the upper Al alloy layer 7, Ar is used as an atmosphere gas, and the flow rate is 100 sccm.
The pressure is 0.4 Pa, the DC power is 15 kW, and the substrate heating temperature is 400 ° C.

The upper Al alloy layer 7 formed as described above is connected at the upper part of the wiring groove 5 and the connection hole 4 to form a bridge shape in which the void 8 is left. Here, as described above, when forming the upper Al alloy layer 7, the substrate heating temperature is set to 400 ° C., thereby promoting the migration of Al, which contributes to the formation of the bridge shape.

Next, the entire Si substrate 1 is heated to near the melting point of the Al alloy in a high-pressure reflow furnace evacuated to a high vacuum to melt or soften the upper Al alloy layer 7. For example, by introducing an inert gas such as Ar at a high pressure, the upper surface of the upper Al alloy layer 7 is pressurized to reduce the voids 8. Thus, FIG.
As shown in (1), the inside of the wiring groove 5 and the connection hole 4 is completely filled with the Al alloy. As an example of high-pressure reflow conditions for the upper Al alloy layer 7, the pressure is 10 ⁶ Pa or more, the substrate heating temperature is 450 ° C., and the time is 1 minute.

Next, the upper Al alloy layer 7 and the TiN / Ti layer are exposed by, eg, CMP until the interlayer insulating film 3 is exposed.
The film 6 is polished to remove the upper Al alloy layer 7 and the TiN / Ti film 6 other than the wiring groove 5 and the connection hole 4. Thereby, as shown in FIG. 4, a buried interconnect 9 as an upper interconnect connected to the lower Al alloy interconnect 2 via the connection hole 4 is formed in the interconnect trench 5. As an example of the polishing conditions by the CMP method, the polishing pressure is 100 g / cm ² , the rotation speed of the platen is 30 rpm, the rotation speed of the polishing head is 30 rpm, SUBA IV is used as the polishing pad, and NH ₄ is used as the slurry. Using OH-based one containing foamed silica, flow rate 100c
c / min, and the polishing temperature is 25 to 30 ° C.

As described above, according to the first embodiment, after the dual damascene structure including the connection holes 4 and the wiring grooves 5 is formed in the interlayer insulating film 3, the upper layer Al is used as a wiring material for forming a buried wiring. The alloy layer 7 has a width of 3 of the width of the wiring groove 5.
Since the film is formed to be twice as thick, the upper Al alloy layer 7 is reliably connected at the wiring groove 5 and the connection hole 4, and the bridge shape is formed stably. For this reason, high-pressure reflow is performed thereafter, so that the wiring groove 5 is formed.
Further, the inside of the connection hole 4 can be completely filled with the Al alloy. Thereafter, unnecessary portions of the upper Al alloy layer 7 and the TiN / Ti film 6 are removed, whereby the embedded wiring 9 can be formed. As described above, the embedded wiring 9 as the upper layer wiring can be formed stably.

FIGS. 5 to 7 show a method of manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 5A is a plan view showing a portion of a wiring groove and a hole for forming a pad.
B, FIG. 5C and FIG. 5D are respectively BB line of FIG.
FIG. 3 shows a cross-sectional view along the line CC and the line DD. 6A, 6B, and 6C are cross-sectional views corresponding to FIGS. 5B, 5C, and 5D, respectively, and FIGS. 7A, 7B, and 7C are cross-sectional views corresponding to FIGS. 5B, 5C, and 5D, respectively. Show.

In the second embodiment, first, as shown in FIG. 5, for example, a lower Al alloy wiring (not shown) is formed on a Si substrate 11 so as to cover the lower Al alloy wiring. An interlayer insulating film 12 such as a SiO ₂ film is formed. Next, a wiring groove 13 and a hole 14 for forming a pad are formed in the interlayer insulating film 12 by a lithography process and an etching process, and a dummy pattern 15 is formed in the vicinity of these connection portions. Specifically, for example, first, a resist pattern (not shown) having a shape corresponding to the wiring groove 13, the hole 14 for forming a pad, and the dummy pattern 15 is formed on the interlayer insulating film 12 by a lithography process. . Next, using this resist pattern as a mask, the interlayer insulating film 12 is etched to a predetermined depth by, for example, RIE or the like to form a wiring groove 13, a hole 14 for forming a pad, and a dummy pattern 15. Remove. Next, a resist pattern (not shown) is formed by a lithography process to cover the outside of the pad formation hole 14, the dummy pattern 15, and the bottom of the wiring groove 13 other than the portion where the connection hole is formed. Using this resist pattern (not shown) as a mask, the interlayer insulating film 12 is etched again by, for example, RIE or the like, so that the hole 14 for forming the pad has a predetermined depth, and the connection hole is formed at the bottom of the wiring groove 13. (Not shown). Here, this pad forming hole 1
The depth of 4 is the same as the total depth of the wiring groove 13 and the connection hole. Thereafter, the resist pattern is removed.

Next, as in the first embodiment, FIG.
As shown in (1), a Ti film and a TiN film are sequentially formed on the entire surface by a magnetron sputtering method in a high vacuum, and a TiN / Ti film 16 is formed. Next, an upper Al alloy layer 17 containing, for example, 0.5% of Cu is formed on the TiN / Ti film 16 by, for example, magnetron sputtering in a high vacuum. Here, as in the first embodiment, the thickness of the upper Al alloy layer 17 is selected to be three times or more the width of the wiring groove 13. Specifically, for example, assuming that the width of the wiring groove 13 is 0.4 μm,
The thickness of the alloy layer 17 is set to be at least three times the width and 1200 n
m or more.

At this time, as in the first embodiment, the upper Al alloy layer 17 is connected at the wiring groove 13 and the connection hole, and the bridge shape is formed stably. In addition, in the second embodiment, the wiring grooves 13
The dummy pattern 15 having the same height as the upper surface of the interlayer insulating film 12 around the wiring groove 13 is formed in the vicinity of the connection portion between the pad and the hole 14 for pad formation. Sufficient coverage is obtained even at the connection portion between the wiring groove 13 and the hole 14 for pad formation where the width changes abruptly, so that the connection is ensured, and the bridge shape is also stably formed at this portion.

Next, by performing high-pressure reflow in the same manner as in the first embodiment, the upper Al alloy layer 17 is reflowed to form the wiring groove 13, the connection hole, and the hole 1 for forming the pad.
4 is filled with an Al alloy.

Thereafter, as in the first embodiment, the upper Al alloy layer 17 and the TiN / Ti film 16 are polished by, eg, CMP until the interlayer insulating film 12 is exposed. As a result, as shown in FIG. 7, the buried wiring 18 is formed inside the wiring groove 13, and the pad 19 at the end of the buried wiring 18 is formed.

As described above, according to the second embodiment, the dummy pattern 15 is formed in the vicinity of the connection between the wiring groove 13 and the hole 14 for forming a pad.
Upper Al alloy layer 1 as wiring material for forming embedded wiring
When the film 7 is formed, it is difficult to form a bridge shape due to a sudden change in width, and a bridge shape can be stably formed even at a connection portion between the wiring groove 13 and the hole 14 for pad formation. For this reason, high-pressure reflow is performed thereafter, so that the wiring groove 13 and the hole 1 for pad formation are formed.
4 can be completely filled with the Al alloy. After this, the upper Al alloy layer 17 and Ti
By removing the unnecessary portion of the N / Ti film 16, the embedded wiring 18 and the pad 19 at the end thereof can be formed. As described above, the embedded wiring 19 as the upper layer wiring and the pad 19 at the end thereof can be formed stably.

FIGS. 8 to 10 show a method of manufacturing a semiconductor device according to the third embodiment of the present invention. Here, FIG. 8A is a plan view showing a portion of a hole for forming a wiring groove and a pad, and FIGS. 8B, 8C and 8D are respectively BB of FIG. 8A.
FIG. 3 shows a cross-sectional view along the line CC, and the line DD.
9A, 9B, and 9C are FIGS.
8A and 8B are sectional views corresponding to FIGS.
0B and 10C show cross-sectional views corresponding to FIGS. 8B, 8C, and 8D, respectively.

In the third embodiment, first, as shown in FIG. 8, in the same manner as in the second embodiment, the Si layer is formed in advance up to the lower Al alloy wiring (not shown).
An interlayer insulating film 22 such as a SiO ₂ film is formed on the substrate 21 so as to cover the lower Al alloy wiring. next,
By a lithography step and an etching step, a wiring groove 23 and a hole 24 for forming a pad are formed in the interlayer insulating film 22, and an intermediate portion between the width of the wiring groove 23 and the width of the hole 24 for forming a pad is formed at a connection portion thereof. Forming a hole 25 having a width (for example, half the width of the pad forming hole 24);
A dummy pattern 26 is formed in the hole 25.

Next, as in the second embodiment, FIG.
As shown in FIG. 7, after forming a TiN / Ti film 27 on the entire surface, an upper Al alloy layer 28 containing, for example, 0.5% of Cu is formed. Here, similarly to the first embodiment, the thickness of the upper Al alloy layer 28 is selected to be three times or more the width of the wiring groove 23. Specifically, for example, the width of the wiring groove 23 is 0.4 μm
In this case, the thickness of the upper Al alloy layer 28 is set to three times or more the width and 1200 nm or more.

At this time, as in the second embodiment, the upper Al alloy layer 28 is connected at a portion of the wiring groove 23 and a connection hole (not shown) formed at the bottom thereof, and the bridge shape is stabilized. Formed. In addition to this,
In the embodiment, a hole 25 is formed at a connection portion between the wiring groove 23 and the hole 24 for forming a pad, and the hole 25 has the same height as the upper surface of the interlayer insulating film 22 around the wiring groove 13 in the hole 25. Since the dummy pattern 26 is formed, the upper layer Al
The alloy layer 27 is also connected at the connection portion between the wiring groove 23 and the hole 24 for pad formation where the width rapidly changes, and the bridge shape is also formed stably at this connection portion.

Thereafter, in the same manner as in the first embodiment, high-pressure reflow and polishing by the CMP method are performed to form a buried wiring 29 inside the wiring groove 23 as shown in FIG. A 29 terminal pad 30 is formed.

As described above, according to the third embodiment, the intermediate portion between the width of the wiring groove 23 and the width of the pad forming hole 24 is formed at the connection portion between the wiring groove 23 and the pad forming hole 24. Is formed, and the dummy pattern 2 is formed in the hole 25.
6, the same advantages as in the second embodiment can be obtained.

FIGS. 11 to 13 show a method of manufacturing a semiconductor device according to the third embodiment of the present invention. Here, FIG.
FIG. 11A is a plan view showing a portion of a wiring groove and a hole for forming a pad, and FIGS. 11B, 11C and 11D are FIGS.
1A shows a cross-sectional view along line BB, line CC, and line DD. 12A, 12B and 12C.
11B, 11C, and 11D are cross-sectional views corresponding to FIGS. 11B, 11C, and 11D, respectively, and FIGS. 13A, 13B, and 13C are cross-sectional views corresponding to FIGS. 11B, 11C, and 11D, respectively.

In the fourth embodiment, first, as shown in FIG. 11, an element is formed in advance in the same manner as in the second embodiment, and the surface is formed of an interlayer insulating film (neither is shown). After the lower Al alloy wiring 32 is formed on the covered Si substrate 31, an interlayer insulating film 33 such as a SiO ₂ film is formed so as to cover the lower Al alloy wiring 32. Next, a wiring groove 34 and a hole 35 for forming a pad are formed in the interlayer insulating film 33 by a lithography process and an etching process. Next, a connection hole (not shown) is formed at the bottom of the wiring groove 34 by a lithography process and an etching process, and a plurality of connection holes 36 are formed in a matrix on the entire surface of the bottom of the hole 35 for pad formation. . Here, it is generally desirable to form the connection holes 36 as small as possible and in large numbers.

Next, as in the second embodiment, FIG.
As shown in FIG. 2, after forming a TiN / Ti film 37 on the entire surface, an upper Al alloy layer 38 containing, for example, 0.5% of Cu is formed. Here, similarly to the first embodiment, the thickness of the upper Al alloy layer 38 is selected to be three times or more the width of the wiring groove 34. Specifically, for example, the width of the wiring groove 34 is 0.4 μm
In this case, the thickness of the upper Al alloy layer 38 is set to be at least three times the width and 1200 nm or more.

At this time, as in the second embodiment, the upper Al alloy layer 38 is connected by the wiring groove 34 and the connection hole (not shown) formed at the bottom thereof, and the bridge shape is stabilized. Formed. In addition to this,
In this embodiment, since a plurality of connection holes 36 are formed on the entire surface of the bottom of the hole 35 for pad formation, the upper Al alloy layer 38 is formed with the wiring groove 34 and the pad formation hole, whose width changes rapidly. Also at the connection portion with the hole 35 for use, the bridge shape is formed stably also at this portion.

Thereafter, in the same manner as in the first embodiment, high-pressure reflow and polishing by the CMP method are performed to form a buried wiring 39 inside the wiring groove 34 as shown in FIG. Form 39 terminal pads 40.

As described above, according to the fourth embodiment, since the connection hole 36 is formed on the entire surface of the bottom of the hole 34 for forming a pad, the same advantage as that of the second embodiment is obtained. be able to. Further, according to the fourth embodiment, the following advantages can be obtained. That is, in the semiconductor device having the dual damascene structure, the hole for forming the pad generally has a total depth of the wiring groove and the connection hole, whereas the pad in the fourth embodiment has the same depth. The formation hole 35 is formed by forming a plurality of connection holes 36 at the bottom of a hole having the same depth as the wiring groove 34.
Its volume is smaller than that of a normal pad forming hole. For this reason, since the volume of the wiring material to be buried in the pad forming hole 35 can be smaller than that of a normal pad forming hole, the upper Al alloy layer 3 after high-pressure reflow is performed.
The surface flatness of No. 8 can be further improved, and the subsequent surface flattening by the CMP method can be performed without any trouble.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical idea of the present invention are possible.

For example, T in the first embodiment described above.
The conditions for forming the iN / Ti film 6 and the upper Al alloy layer 7, the conditions for high-pressure reflow, and the conditions for polishing by the CMP method are merely examples, and film formation, high-pressure reflow, and polishing under conditions other than these are performed as necessary. May go.

In the first embodiment described above,
Although the case where the buried wiring 9 is formed in the interlayer insulating film 3 having the dual damascene structure has been described, the present invention can be applied to the formation of the buried wiring as a normal trench wiring without using the dual damascene structure. .

Further, in the above-described second, third and fourth embodiments, the case where the pad is formed at the end of the buried wiring has been described. However, according to the present invention, this pad is formed at the end of the buried wiring. In addition to the case where the pad is merely a pad, the present invention can be applied to a case where the pad is an electrode of a capacitor.

[0056]

As described above, according to the present invention, the wiring material for forming the buried wiring is formed to have a film thickness three times or more the width of the wiring groove. In this way, the bridge shape can be stably formed by the wiring material, so that the embedded wiring can be stably formed by using the high-pressure reflow method.

According to the present invention, a dummy pattern is formed in the vicinity of the connection portion between the wiring groove and the hole for forming a pad, or a plurality of connection patterns are formed at the bottom of the hole for forming a pad at the end of the embedded wiring. By forming the holes, it is possible to stably form the bridge shape by the wiring material even at the connection portion between the wiring groove and the hole for forming the pad. Can be formed stably.

[Brief description of the drawings]

FIG. 1 is a sectional view for explaining a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

5A and 5B are a plan view and a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 6 is a sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 7 is a sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

8A and 8B are a plan view and a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 9 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 10 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIGS. 11A and 11B are a plan view and a sectional view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment; FIGS.

FIG. 12 is a sectional view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention;

FIG. 13 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 14 is a cross-sectional view for explaining a method for manufacturing a conventional semiconductor device having a dual damascene structure.

FIG. 15 is a cross-sectional view for explaining a method for manufacturing a conventional semiconductor device having a dual damascene structure.

FIG. 16 is a cross-sectional view for explaining a method of manufacturing a semiconductor device having a conventional dual damascene structure.

FIG. 17 is a cross-sectional view for explaining a method for manufacturing a conventional semiconductor device having a dual damascene structure.

FIG. 18 is a cross-sectional view for explaining a method for manufacturing a conventional semiconductor device having a dual damascene structure.

FIG. 19 is a cross-sectional view for explaining a method for manufacturing a conventional semiconductor device having a dual damascene structure.

FIG. 20 is a cross-sectional view for explaining a method for manufacturing a conventional semiconductor device having a dual damascene structure.

FIG. 21 is a cross-sectional view for explaining a method for manufacturing a conventional semiconductor device having a dual damascene structure.

FIG. 22 is a cross-sectional view for describing a problem of a conventional method of manufacturing a semiconductor device having a dual damascene structure.

[Explanation of symbols]

2, 32 ... lower layer Al alloy wiring, 3, 12, 22, 3
3 ... interlayer insulating film, 4, 36 ... connection hole, 5, 1
3, 23, 34 ... wiring groove, 6, 16, 27, 37
..TiN / Ti film, 9, 18, 29, 39 ... embedded wiring, 15, 26 ... dummy pattern, 14, 2
4, 35 ... holes for pad formation

Claims (10)

[Claims] 1. A method of manufacturing a semiconductor device in which a buried wiring is formed by using a high-pressure reflow method, wherein the wiring material for forming the buried wiring is formed into a film having a thickness of at least three times the wiring width. A method of manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein said wiring material is formed in a film thickness not less than 3 times and not more than 4.5 times said wiring width. 3. The wiring material is aluminum, copper, silver,
2. The method according to claim 1, wherein the material is gold or an alloy thereof.
The manufacturing method of the semiconductor device described in the above. 4. A method for manufacturing a semiconductor device in which a buried wiring is formed by using a high-pressure reflow method, wherein a connection portion between the wiring groove for forming the buried wiring and a hole for forming a pad at the end of the buried wiring. Or a method of manufacturing a semiconductor device, wherein a dummy pattern is formed in the vicinity thereof. 5. The method according to claim 4, wherein said dummy pattern has a height substantially equal to a depth of said hole for forming said pad. 6. The wiring material is aluminum, copper, silver,
5. The method according to claim 4, wherein the material is gold or an alloy thereof.
The manufacturing method of the semiconductor device described in the above. 7. A method of manufacturing a semiconductor device in which an embedded wiring is formed by using a high-pressure reflow method, wherein a plurality of connection holes are formed at the bottom of a hole for forming a pad at an end of the embedded wiring. A method for manufacturing a semiconductor device, comprising: 8. The semiconductor according to claim 7, wherein the plurality of connection holes are formed at substantially the same depth as the connection holes formed at the bottom of the wiring groove for forming the buried wiring. Device manufacturing method. 9. The method of manufacturing a semiconductor device according to claim 7, wherein said plurality of connection holes are formed on the entire bottom surface of said pad formation hole. 10. The wiring material is aluminum, copper,
8. The method for manufacturing a semiconductor device according to claim 7, wherein the method is silver, gold, or an alloy thereof.