JPH11110215A - Information processor using multi thread program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor that is excellent in processing performance of a multi thread program compared with an existing microprocessor or an information processor using them in plural. SOLUTION: A plurality of information processing elements 9 consisting of a command selection device 3, a command storage device 4 and an operation unit 5, are arranged horizontally and result information from the command selection device 3 and the command storage device 4 is transmitted. A thread is horizontally stored in the command storage device 4 by the command and executes an operation corresponding to the command by using plural operation units 5 in order. Plural operation units 5 are always operated by simultaneously operating plural independent threads while shifting the time. All the operation units 5 can simultaneously use a data memory 7 by a cross bus switch 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus using a digital circuit, and more particularly to a microprocessor and an information processing system using the same.

[0002]

2. Description of the Related Art There are mainly two methods for improving the performance of general-purpose microprocessors. Improvement of operating frequency and parallelization. The operating frequency can be improved by improving semiconductor process technology and changing the circuit configuration such as a pipeline. The former is expected to continue to evolve in the future, but the latter is hardly expected to improve because of the speed of the memory. Therefore, in the future, performance will be improved by improving process technology and parallelizing.

However, parallelization has various limitations. Means for performing parallelization while maintaining program compatibility is well known as the superscalar method.However, the superscalar method requires a larger circuit for parallel allocation of instructions than the main processing unit, and consumes less power. It is not good in terms of point. At least from the viewpoint of reducing power consumption, it can be said that this approach should be avoided unless there are restrictions on program compatibility. The superscalar method is local parallel extraction of a program. It can be said that it is a method to intentionally parallelize the part with the most data dependencies in the program. Therefore, the performance improvement rate due to the increase in hardware for parallelization is saturating.

[0004] Therefore, typical systems for giving up compatibility of programs and proceeding with parallelization are the following VLIW system of the first conventional example and the shared memory multiprocessor system of the second conventional example.

<Conventional Example 1> Referring to FIG. 2, a schematic diagram of a conventional VLIW type microprocessor on which the present invention is based is shown. Hereinafter, this example is referred to as Conventional Example 1.

The VLIW type microprocessor includes an instruction address generation unit 201 and an instruction cache 20.
2. Instruction decode 203, data crossbar switch 20
4, branch unit 205, load store unit 20
6, two operation units 207, multi-port register file 2
08, a data cache 209, and an external bus interface 210.

In the VLIW microprocessor, instructions issued from the instruction cache 202 simultaneously control the branch unit 205, the load store unit 206, and the two arithmetic units 207. Therefore, the instruction cache 202 stores a plurality of instructions in a single line.

The branch unit 205, the load store unit 206, and the two arithmetic units 207 all share one register file 208, and are distributed by the data crossbar switch 204. Since the branch unit 205, the load store unit 207, and the two arithmetic units 207 can operate simultaneously, all input data and output data are connected to the register file 208.

The features of the VLIW type microprocessor are as follows.
The instruction decoder 203 is capable of controlling a plurality of arithmetic units 207 and load store units 206 at the same time.
Is to suppress the complexity of However, when the number of arithmetic units 207 is further increased, the number of transfer buses between the arithmetic units,
There is a problem that the number of ports in the register file 208 is extremely increased. This leads to an increase in circuit scale and a decrease in clock speed. The only solution to this disadvantage is to divide the register file 208 and the data crossbar switch 204. However, for the purpose of division, independent processes having no data dependency must coexist in an instruction sequence executed at the same time. In the VLIW type microprocessor, it is necessary for a compiler or a programmer to mix independent processing in one instruction line beforehand and store it in the instruction cache 202 in advance. This results in a loss of freedom of operation in massively parallel. In summary, in order to improve parallel processing performance in the future, it is necessary to have a structure capable of operating by dynamically combining a plurality of programs having ordinary dependencies.

The VLIW type microprocessor is
A circuit specialized for a specific application is often incorporated in parallel with the arithmetic unit. This is a method often used in a microprocessor dedicated to multimedia called a media processor. The purpose of a media processor is to provide both the high speed of a dedicated circuit and the flexibility of a general-purpose microprocessor. However, if a large number of special-purpose processing units are to be mounted in order to improve performance in the future, processing before and after data exchange with these special-purpose processing units becomes a problem. In order to maintain the degree of freedom and the performance of the combination of the dedicated circuits, it is necessary to increase the number of the integer arithmetic units 207 and the load store units 206 which mediate between the dedicated circuits. However, it is based on the VL
There is a limit of parallelization depending on the IW type. However, if these circuits are not used and the dedicated circuits are directly connected to each other, the degree of freedom of combination is lost and the versatility is lost. Future media processors will require means that can dynamically change the connections between dedicated circuits and process high bandwidth data.

<Conventional Example 2> Referring to FIG. 3, a schematic diagram of a configuration using a plurality of conventional microprocessors based on which the present invention is based is shown. Hereinafter, this example is referred to as Conventional Example 2.

FIG. 3 shows a configuration called a shared memory type multiprocessor. This is a system equipped with a plurality of microprocessors 301 having a mechanism for sharing data. In the figure, three are mounted and connected to the shared bus 304. The memory banks 305 and 306 are both shared bus 30
4 and cannot be accessed simultaneously. The shared function unit 307 is connected to the shared bus 304 in order to share the infrequently used operations. The I / O peripheral 308 is also connected to the shared bus 304.

A single microprocessor 301 includes an instruction cache 311, an instruction issuing unit 312, an integer arithmetic unit 313, a floating point arithmetic unit 314, a load store unit 315, a data cache 316, and a cache coherency control mechanism 317. The cache coherency control mechanism 317 always snoops the contents of the shared bus 304, and controls the copy sharing state of its own data cache 316.

This shared memory multiprocessor system is
Unlike the VLIW method of the conventional example 1, the microprocessors can perform completely independent processing in any combination. The shared memory multiprocessor system has the following advantages over multiprocessors of other systems. Software created for a single microprocessor can be used to some extent, dynamic inter-processor communication programs can be easily created, and the actual communication bandwidth can be reduced by a local cache for each microprocessor.

A disadvantage of the shared memory multiprocessor system is that the hardware required to improve the performance becomes the most complicated.

First, all the microprocessors 301
Has an instruction cache 311. When a medium-level parallel processing such as a loop is executed by a multiprocessor, each instruction cache 311 has a copy of the same program. Also, the bandwidth of the instruction cache replacement is required by the number of processors.
Since the loop is to reuse the same instruction, sharing of instruction memory between microprocessors 301 is desirable.

Next, the data cache 316 will be described. Since the bus is shared, it is necessary to mount a large-scale local cache and a cache coherency arbitration mechanism. The threads are non-deterministically distributed among the processors 301 to 303, and need to transfer data using the data cache coherency control 317 and the shared bus 304. When the parallelism of the microprocessor 301 is increased, the performance is limited by the limit of the transfer capability of the shared bus. However, if the bus is divided to gain bandwidth, cache control is performed for both buses,
The increase in hardware will be enormous. It is desirable that the memory bank 305 can be directly connected to the microprocessor 301 naturally.

Since it is difficult to share the arithmetic units, all of the microprocessors
4 However, the floating point arithmetic unit 314
The occurrence frequency and operation rate of the instruction are lower than that of the integer arithmetic unit 313 except for special applications. For this reason, it can be said that mounting dedicated arithmetic units as many as the number of processors is redundant. However, like the functional unit 307, the shared bus 3
04, the transfer bandwidth with the microprocessor 301 becomes insufficient. For this reason, it is required to achieve both the sharing of the dedicated arithmetic unit and the transfer bandwidth with the microprocessor.

[0019]

A method of promoting parallelization while maintaining program compatibility is known as a superscalar method, but this method has an extremely low performance ratio to the circuit scale. Therefore, the typical systems that give up the performance by giving up the compatibility of the program are the VLIW system of the conventional example 1 and the shared memory multiprocessor system of the conventional example 2 shown below.

However, the VLIW system of the prior art 1 has an upper limit on the number of parallel operations, is low in versatility in parallel programming, and lacks verticality. Since the shared memory multiprocessor of Conventional Example 2 incorporates all the circuits of the conventional microprocessor, there are many redundant circuits, and the power consumption and the circuit scale are maximized. In addition, since the bus is shared, the drawback is that the performance with respect to the parallelism is saturated due to the limitation of the bus bandwidth.

Therefore, there is a demand for a microprocessor having a simple structure and low power consumption, which has no upper limit on the degree of parallelism, has a program structure close to that of a conventional microprocessor, can utilize the parallel performance with the same program, and has a simple structure.

<Requirement of General-purpose Microprocessor with High Computing Ability while Maintaining Degree of Freedom> A circuit designed specifically for use is always faster than a general-purpose processor. However, it is based on the premise that a single function is realized. However, applications required in the future are required to realize many functions. For that purpose, dedicated circuits are prepared by the number of functions. However, it is impossible to provide all dedicated circuits to cover all of the increasingly complex application functions. Therefore, functions that do not require much performance have been successively replaced by general-purpose microprocessors. Even in the case where a dedicated circuit needs to be used, the degree of freedom is ensured by the microprocessor mediating a plurality of dedicated circuits.

The function of using a plurality of dedicated circuits needs to simultaneously secure the degree of freedom of connection between the dedicated circuits and the bandwidth. However, the improvement in bus transfer speed and the performance of a middleman microprocessor is saturating. Therefore, it is necessary to divide the bus and the microprocessor. However, the division of the bus and the microprocessor makes the load distribution and the synchronization mechanism very complicated as seen in the second conventional example. A microprocessor that can share a plurality of dedicated circuits with all processors while maintaining local performance by dividing a bus or a microprocessor is ideal.

<Requirement of High-Performance Hardware for Power Consumption> A microprocessor having the highest performance for cost has the highest power consumption and chip cost if there is no compatibility constraint with a single processor. It can be said that it is a processor that can provide high performance. If the cost of a single unit is low, the highest performance system can be constructed by using a large amount of the processor.

In other words, the power consumption can be reduced if the microprocessor is squeezed. Means for low power consumption exist at the architecture level, the circuit level, and the process level, respectively. Among them, the means at the architectural level is simply to eliminate circuits and wirings not directly related to the processing performance as much as possible.

Since the existing superscalar-type microprocessor has a paradigm of operating an existing program on a single microprocessor, there is a circuit for translating the existing program into an internal instruction-level parallel microprocessor. . In recent years, this circuit has been increasing in size. This makes low power consumption and performance incompatible.

The essence of a microprocessor is an arithmetic unit and a memory. The rest is basically a redundant circuit.
Minimizing the redundant circuit while maintaining the degree of freedom leads to low power consumption at the architecture level.

<Changes in Required Software> As a method of describing a parallel program, vector expansion by a compiler using a loop used in a vector processor type supercomputer in the past, expansion into SIMD instructions and VLIW by a compiler recently, etc. Technology. In this method, only special processing such as a loop operates in parallel, and processing before and after the loop hinders performance. This is widely known as Amdahl's law.

However, at present, a technique called multithreading, which is a technique capable of achieving both versatility of a program for performing parallel processing, high-speed switching of processing, and high-speed communication during processing, is becoming mainstream. This multi-thread,
It is created so as to be optimal for the shared memory multiprocessor shown in the conventional example 2. If the multithread is registered in the OS, the load is automatically distributed to the free microprocessor. In a multi-threaded program, the effect of Amdahl's law can be reduced compared to parallel unrolling of loops to ensure that synchronization between threads must be explicitly described and otherwise operate independently. it can. By using this multi-thread programming model, sufficient versatility and load balancing to massively parallel can be achieved at the same time. Further, multi-threading can be compatible with SIMD instructions and the like.

The pairing of data and processing is a part of a technology called object-oriented technology, which is a technology that supports future applications that will be scaled up and distributed. A processor unit composed of a microprocessor and a memory is created so as to conform to the object orientation.
Then, an object requiring a processing capability is assigned to one or more of the processor units, and an object requiring no processing capability is assigned to a shared processor unit. This method is one of the most natural forms of load distribution for object-oriented software.

In recent years, the main use of microprocessors has been shifting from scientific computing to multimedia applications. This multimedia application tends to require a large amount of data transfer capability with a lot of routine processing. Nevertheless, there is a characteristic that data dependency is relatively small between a large amount of processing, and it can be said that the distribution of data and processing is easy. Then, a plurality of processes operate simultaneously, and the combination is non-deterministic. Therefore, in order to efficiently perform the non-deterministic combination of processes, it is essential to improve the performance of a general-purpose microprocessor that mediates with the introduction of a dedicated circuit.

[0032] Multimedia applications require high-speed real-time performance. at present,
Although process scheduling using complex priorities is adopted, in the future, multiple microprocessors will be statically allocated to a process by a fixed amount and the load will be distributed by the number of allocated microprocessors. A simple structure is more desirable. The reason for setting the priority is that it is necessary to allocate a certain calculation resource.

In conclusion, it would be desirable to have a microprocessor that allows for versatility with multi-thread programming and explicit load balancing in an object-oriented manner.

[0034]

Next, the present invention will be described with reference to the drawings.

<Embodiment 1> Referring to FIG. The microprocessor 1 of the present invention has one or more instruction issuing control means 2. Then, a plurality of the program counter storage means 3, the instruction storage means 4, the arithmetic means 5, and the data storage means 7 are incorporated as a set. Then, the arithmetic means 5, the data storage means 7, and the external interface means 8 are connected to one dynamic signal connection means 6.

The instruction issuance control means 2 operates in response to a request from the external interface 8 or a request from the arithmetic unit 5. The instruction issuance control means 2 includes an instruction storage means 4
Is transferred to the first program counter storage means 3 to start the arithmetic processing.

The program counter storage means 3 is connected in series and individually connected to the instruction storage means 4. At the same time as the completion of the operation of the arithmetic unit, the program counter is transmitted to the program counter storage means 2 on the right side, and the updated program counter is received from the program counter storage means 3 on the left side. The rightmost program counter storage means 3 is connected to the instruction issuance control 2 and notifies the end of a series of operations.

The instruction storage means 4 are all connected to the operation means 5 and each transmit an instruction code for selecting a function of the operation means 5. The instruction code to be read is selected according to the value from the program counter storage means 3.

The operation means 5 receives the instruction from the instruction storage means 4 and performs an operation process, and reads out a value used for the operation from the dynamic signal connection means 6. The calculation result is transmitted to the calculation means 5 adjacent to the right or the dynamic signal connection means 6.

The dynamic signal connection means 6 allows all the arithmetic means 5, the data storage means 7, and the external interface means 7 to simultaneously communicate with one another. The dynamic signal connection means 6 selects one of all the data storage means 7 and the external interface means 7 in response to a request from the calculation means 5 and transfers the data value to the calculation means 5. Alternatively, the calculation result is transferred by selecting one of the data storage means 7 or the external interface means 7.

It is sufficient that the data storage means 7 can process only one read or one write at the same time. All the arithmetic means 5 can be arbitrated by the instruction issuing control 2 so as not to communicate with the same data storage means 7 or the external interface means 7 at the same time.

The external interface means 8 reads data necessary for the operation of the microprocessor 1 from outside the microprocessor 1 in response to a request from the operation means 5.
Alternatively, the operation result of the operation means 5 is output to the outside of the microprocessor 1.

<Second Embodiment><Internal Structure of Microprocessor 401> Referring to FIG. 4, a microprocessor 401 according to a second embodiment of the present invention will be outlined.

The four integer operation unit groups 405 and the four thread control units 403 are connected by a branch crossbar switch 402. An instruction memory 404 is connected to each of the four thread control units 403. The instruction memory 404 is connected to an integer operation unit group 405, respectively. Integer operation unit group 405
Incorporates four integer arithmetic units. Therefore, the microprocessor 401 can simultaneously execute a maximum of 16 integer operations.

All integer arithmetic units are connected to one local cache crossbar switch 406. 1
The K-byte local data caches 407 are mounted in a number equal to the number of integer operation units, and are all connected to one local memory crossbar switch 406. The local memory crossbar switch 406 is also connected to the global access control 408 and the shared floating point operation unit 409. The global access control 408 is also connected to the shared floating point arithmetic unit 409 and controls the same. Similarly, the control of the branch crossbar switch 402 and the local memory crossbar switch 406 is performed.

The branch unit 402 crossbar switch
It receives the thread status signal 419 from the four integer operation unit groups 405 and the thread resumption request signal 430 from the access control unit 408, and transmits the thread status signal 411 to the appropriate thread issuing unit 403. Four branches can be processed at the same time. The leftmost thread control unit 403 receives a thread control signal 413 from another thread control unit 403 disposed on the right side, and transmits a program counter signal 414. Also, the thread control unit 403 receives a thread control signal 41 from the rightmost thread control unit 403.
3 is received and the program counter signal 414 is received. The rightmost thread control unit 403 connects the program counter signal 413 to the global access control unit 408 and receives the incremented program counter signal 412.

The instruction memory 404 transmits the instruction decode signal 415 to the adjacent integer operation unit group 405 based on the contents of the built-in instruction memory. at the same time,
An instruction decode signal 431 which is a part of the decode signal 415 is transmitted to another instruction memory 404 arranged on the right side. In a normal pipeline, an instruction decode result is sent to the next pipeline stage. However, in the processor of the present invention, the next pipeline stage is always executed by an arithmetic unit adjacent to the right. Rightmost instruction memory 404
Transmits an instruction decode signal 431 to the leftmost instruction memory.

The integer operation unit group 405 includes four integer operation units, four branch units, and one branch arbitration unit. The function of the integer operation unit group 405 can be freely changed using the instruction decode signal 415 received from the adjacent instruction memory 404. In this respect, it is the same as a general microprocessor. And
As input data for the operation, four signals 417 for exchanging addresses and data with the local memory crossbar switch 406 and the global memory access bus 42
7, 428 are connected. The number of four is equal to the number of integer operation units included in the integer operation unit group 405. Further, in the processor of the present invention, data is also received from the integer arithmetic unit 405 adjacent to the left via the pipeline data bus signal 416 at the same time. When the arithmetic unit 405 is at the left end, the data is received from the rightmost arithmetic unit 405. The connection to the local memory crossbar switch includes a data bus, an address bus, and a control bus. Although the data bus has 32 bits, the address bus uses only 8 bits of 1 Kbyte for internal notation. The global memory access address bus signal 417 is 32 bits long.

Further, all the integer operation unit groups 405 transmit the thread state signal 419 to the branch crossbar switch 402. The thread status signal 409 is distributed to one of the four thread control units 403 according to the contents of the program counter signal in the thread status signal 419.

The local data cache 407 is a one-port cache memory having a capacity of 1 Kbyte. A total of 16 microprocessors are arranged on one microprocessor 401. They are all connected to the local memory crossbar switch 406. The local memory address bus 421 is a 26-bit signal. The local memory data bus 422 is a 32-bit bidirectional signal. By preparing 16 local data caches 407, all the integer operation units incorporated in the microprocessor 401 can access the local data cache 407 at the same time.

Local memory crossbar switch 406
Receives an address signal among the 16 local memory access signals 418 and transfers it to an arbitrary local memory address bus 421 as it is. The data bus signal of the local memory access signal 418 is connected to the local memory data bus 422 according to the content of the crossbar switch control signal 426, respectively. The data bus signal of the local memory access signal 418 and the signal of the local memory data bus 422 are all bidirectional.

Global access control unit 408
Is a branch request signal 43 from the integer operation unit group 405.
3, 434, 435 and 436 are received, and the branch crossbar switch 402 is controlled. At the same time, the local memory crossbar switch 406 is controlled using the control signal 426. Also, the global access control unit 408
Are connected to a global memory access address signal 427 and a global memory access data signal 428. The instruction cache is replaced by the instruction cache replace signal 432 and the data cache is replaced by the data cache replace signal 425. When the access is to the outside of the microprocessor 401, the external address bus 452, the external control bus 45
1 is used to access the external memory of the chip. The external data bus 450 is an output during external writing and an input during external reading. When data loading from the outside or replacement of the cache is completed, a thread resumption request is issued to the thread control unit 403 through the branch crossbar switch control signal 430 in order to generate a sleeping thread waiting for loading. Further, it receives the external interrupt signal 453, converts it into a thread issue, transmits the thread status signal 437, and causes the thread control unit 403 to generate an interrupt accepting thread.

The shared floating point arithmetic unit 409 is connected to the local cache crossbar switch 406 via a data bus 424 and an address bus 423. The shared floating-point unit 409 receives data from the integer operation unit group 405 via the local cache crossbar switch 406, and
5 directly. The shared floating-point operation unit 409 is connected to one integer operation unit group 405 that has requested the operation, instead of the local cache memory 407 by the local crossbar switch 406.

<Integer operation unit group 405> Next, FIG.
, A block diagram of the internal structure of the integer operation unit group 405 will be outlined.

The integer operation unit group 405 includes four integer operation units 501, four branch units 502,
Branch arbiter 503 for arbitrating branch unit 502
Consists of

The integer operation unit 401 mainly comprises an integer operation unit and a temporary data register. An instruction decode signal 511 for controlling execution of the arithmetic unit is received from the instruction memory 404 described above. One internal operation is performed by receiving all internal states including the temporary data register from the integer operation unit 401 in the preceding stage. All states including the operation result are transmitted to the integer operation unit 401 in the next stage. It differs from other processors in that all states are transmitted to the right every clock. To execute load store / branch to memory generated as a result of operation,
A control signal is sent to the branch unit 502, and data read from the memory is received from the branch unit 502.

The branch unit 502 executes a branch instruction and executes load store. A local memory load store can be performed by all branch units 502 simultaneously. However, execution of the branch is performed by four branch units 502.
And only one can run at the same time. Further, the load store of the global memory is one at a time for the entire microprocessor 401. In the processor of the present invention, it is necessary to perform not only thread switching, but also branching and loading of an indefinite latency time, all of which need to perform thread saving and context switching. Therefore, it is necessary to transmit a state necessary for a thread to the branch unit 403 by a branch request signal group each time a branch is performed. In the microprocessor of the present invention, three signals of a program counter, a stack pointer, and a thread ID are used as a minimum necessary thread state. These are transmitted to the branch arbiter 503 through the branch request signal group 525 according to the execution of the branch. Branch unit status signal group 516
Is an internal state required for branching.

The local memory load store of the branch unit 502 simply stores the local address 521 unconditionally toward the local cache crossbar switch 406;
The local data 523 may be stored. In the case of loading, the data is read into the right local data 523 with a delay of one clock. In the scheduling, the global access control unit 408 controls the local cache crossbar switch 406. Since one data cache memory 407 is statically allocated to a thread, the control of the local memory crossbar switch 406 is basically static. For the data cache memory 407 to which the branch unit 502 is not assigned, the branch unit 502 holds the data on the spot regardless of the transmission of the thread to the right, and the target data cache memory bank 407 is assigned to the branch unit 502. Wait for. Unassigned data cache memory bank 407
Access latency requires a minimum of 16 clocks. Instead, arbitration of out-of-bank access to the same bank by 16 threads becomes possible.

The branch arbiter 503 receives all the branch request signal groups 525 to 528 from the four branch units 502, selects one, and transmits the branch request signal 419 to the branch crossbar switch 402. The branch request signal groups 525 to 528 that are not selected become pipeline stall and are issued after the next clock. This implementation is based on the assumption that the frequency of branching is basically one-fourth or less of the instruction.

<Integer operation unit 501> Next, reference will be made to FIG. FIG. 3 is a block diagram of an internal structure of an integer operation unit 501.

Reference numerals 601 to 619 denote edge trigger flip-flops. The program counter 601, the stack pointer 602, and the thread information 603 are signals transmitted from the branch unit 403 when a new branch or thread is issued. Decoded instruction code latch 604
Is a signal always transmitted from the instruction memory 404.

The program counter 605 is a 26-bit signal that indicates the instruction address of the thread in the pipeline stage, and is used for calculating the branch destination. The condition execution instruction control latch 606 is a control signal for executing write back of the operation result of the integer operation unit 501 or suspension of execution of a branch instruction. The flag register latch 607 is a state holding register for a case where the flag is not updated. The flag register update latch 608 is
It is connected to the first operand bus 627 and is used to directly substitute the value of a register into a flag. The ALU operation result flag latch 609 holds the flag of the operation result of the integer operation unit 501 one clock before, which is arranged on the left. In general, the calculation of a flag tends to be a critical path, and therefore, the assignment to the flag register 607 is performed in the next stage of the operation. ALU operation result latch 6
Reference numeral 10 denotes a latch for holding the operation result of the ALU 630. The barrel shifter operation result flag latch 611 is a latch that holds a flag change generated in the barrel shifter 631. The barrel shifter operation result latch 612 is a latch that holds the operation result of the barrel shifter. The store data latch 613 is a latch that holds store data until the store is executed at the next clock of the operation.

The register write-back latch 614 is used to delay the timing of writing the result back to the first to fourth general-purpose register latches 615 to 618. Since the write-back of the register needs to be performed at the same timing as the writing of the read data from the local memory, it is necessary to temporally delay by one clock.

The first to fourth general-purpose register latches 615 to 618 are used for operand registers used for operations. Stack pointer latch 619
Holds a stack pointer address used for writing back the operation result, temporarily saving the state, and the like.

Program counter update selector 621
Selects the value to be transmitted to the next program counter 601 from the previous program counter 605 and the program counter 601 to be updated. When the thread is restarted due to the termination of the branch or the undefined latency load, the program counter 601 to be updated is selected. Otherwise, the previous program counter 605 is used as it is. Unlike a general microprocessor, no program counter adder is required.

The program constant generation circuit 622 generates a lower-order PC that is not included in the program counter 605. Numerical values from 0 to 15 are assigned to the 16 integer arithmetic units 501 to generate values.

In response to the decoded instruction code 604, the flag register update selector 623 provides a previous flag register latch 607, a previous flag register update register 608, and a previous ALU operation result flag latch 60.
9. A signal to be transmitted to the flag register latch 607 of the next stage is selected from the barrel shifter operation result latches 610 of the previous stage. 608, AL in the assignment instruction to the flag register
609 is selected for the U instruction, 611 for the shift instruction, and 607 for the other instructions.

The conditional execution instruction control circuit 624 controls branching, data forwarding and write-back according to the contents of the flag register 608 and the decoded instruction code 604. It does not stop the operation immediately.
For branch control, a condition execution control signal 646 is transmitted to the branch unit 502. For the write-back control of the result data 642 to the general-purpose register latches 615 to 619, the general-purpose register update registers 634 to 638 are controlled to substitute the value of the data write-back bus 642 only when the condition is satisfied. Regarding the data forwarding, the operation result bus 641 and the write-back bus 6 are forwarded by the operand selectors 627 to 629.
Select whether to substitute the data of 42. Even if the actual instruction has a register data dependency, forwarding is performed only when the condition is satisfied.

The constant generation circuit 626 generates a constant to be used for the operation in accordance with the content of the decoded instruction code 604 and substitutes it for the second operand selector 628.

The first operand selector 627 includes a first operand bus 643, a result transmission bus 641, a data write back bus 642, and a program counter bus 6.
One is selected from 25 and substituted into the ALU circuit 630, the barrel shifter 631, and the flag register update latch 608.

The second operand selector 628 includes a second operand bus 644, a result transmission bus 641, a data write back bus 642, and a constant generation circuit 626.
One is selected and substituted into the shift number control input of the ALU circuit 630 and the barrel shifter 631.

The store data selector 629 includes a third operand bus 645, a result transmission bus 641, a data write back bus 642, and a program counter bus 62.
5 and the output of the flag register update selector 623, and assigns it to the store aligner 632.

The store aligner 632 stores a byte or a 16-bit word unit according to a store address.
This unit is appropriately arranged on a 32-bit data bus.

Thread register forward bus 633
Is a bus for another subsequent thread to use the value of the operation result bus 641 of the integer operation unit 501 as an operand. Thereby, communication between multi-threads can be performed at high speed.

The first general register update selector 634 is
One of the first general-purpose register latch 615 and the data write-back bus 642 is selected and assigned to the first general-purpose register latch 615 of the next stage. The second general register update selector 635 to the fourth general register update selector 637 perform the same operation.

The stack pointer update selector 638
Stack pointer latch 619, data write back bus 642, and stack pointer update latch 602
Is selected and assigned to the stack pointer register 638 of the next stage.

The memory store data bus 640 is 32-bit data stored in the local memory 407 and the external memory.

The operation result bus 641 is used to write the operation result back to the local memory 407. The local memory 407 is used as an address for accessing an external memory.

The data write back bus 642 transfers the operation result or load data to the general purpose registers 615 to
This is a bus for writing back to 19.

The first operand bus 643 is used for reading the general-purpose registers 616 to 618 and the stack pointer 619. The second operand bus 644 and the third operand bus 644
The same applies to the operand bus 645.

<Branch / Load Store Unit 502> Next, the internal structure of the branch unit 502 will be outlined with reference to FIG.

The branch unit 502 includes a thread state latch 701, a load data latch 702, a load data holding buffer 703, a local memory write address latch 704, and a local memory write data latch 70.
5, address selector 706, address buffer 70
7, a store data selector 708, a store data buffer 709, a thread state update selector 710, a branch control unit 711, a load aligner 712, and a local memory access protection check 713.

The thread status latch 701 is provided for the thread I
The thread state required for branching, such as D, is held. It can be updated by selecting the value of the thread status signal 647 by the thread status update selector 710.

The load data latch 702 is a 32-bit latch used to hold the value read from the data bus until the next clock. The load data holding buffer 703 is used to hold read data from a non-owned local memory.

Local memory write data latch 70
4, and local memory write address latch 705
Is a 32-bit latch used to delay writing to local memory.

The address selector 706 is connected to the local data cache memory 407 or the global bus 4
27, the address value to be output to the operation result bus 641,
A local memory write address latch 705 from the previous clock and an address buffer 707 are selected from the three.

The address buffer 707 is a 32-bit buffer and stores the local cache memory 4 outside the bank.
Up to two load store addresses can be stored in order to wait for the access of 07 and the arbitration of the output to the global bus 427.

The store data selector 708 selects a data value to be output to the local memory 407 or the global bus 427 from the memory store data bus 640, the local memory write data latch 704, or the data bus buffer 709. I do.

The data bus buffer 710 is a 32-bit buffer and can store up to two store data in order to wait for local memory access outside the bank and arbitration of output to the global bus 427.

The branch control unit 711 performs out-of-bank local memory access, execution of a global load / store instruction, execution of a branch instruction, and arbitration with the branch arbiter 503. In the case of a branch, the program counter to be updated is received from the operation result bus 641. The stack pointer to be updated is received from the memory store data bus 640. Other thread states, such as the thread ID, are received from the thread state latch 701. These are collectively output from the branch request signal group 525 to the branch arbitration unit 503. Here, when the branch is canceled due to the conditional execution instruction, the branch cancel operation is accepted and the branch operation is stopped.

When reading data in byte units, the load aligner 712 shifts the data, extends the code to 32 bits, and the like.

The local memory access check 713 checks whether an address signal issued to the local memory is an access to a unique local memory. In the case of write access to a unique local memory, writing to the local memory is performed at the next clock using the data latch 704 and the address latch 705. In the case other than the unique local memory, the data is held using the address buffer 708 and the data buffer 710, and is output to the local memory or the global memory bus 427.

If the branch arbitration unit 525 cannot receive the branch acknowledgment signal 714, the arbitration of the branch fails and the branch cannot be executed. In that case, all the branch information is transmitted to the right adjacent arithmetic unit 501 using the data bus group 515. The original thread becomes a pipeline stall and waits for data to be saved. At the next clock, the right adjacent branch unit 502 executes the same branch again.

<Instruction Issuing Unit 404> The internal structure of the instruction issuing unit 404 will be outlined with reference to FIG. The instruction issuing unit 404 is a unit that outputs an instruction code required for the integer operation unit group 405 based on the program counter provided from the branch unit 403.

The instruction issuing unit 404 includes the X decoder 8
01, 128-bit SRAM cell 802, sense amplifier and Y selector 803, instruction memory access control unit 804, three instruction code selectors 805, 6
It comprises two 32-bit instruction code latches 806 and an instruction decode unit 807.

Based on the signal of the program counter 821,
The instruction code is read from the SRAM cell 802. SRA
Four instruction codes are simultaneously read from the M sense amplifier 803.

Replacement signal 851 having a width of 128 bits
Are directly connected to the sense amplifier 803. The instruction replacement is executed in one clock.

The instruction code 830 with the youngest instruction address
Is immediately sent to the instruction decode unit 807. However, the next instruction code 831 is stored in the instruction code latch 806 and issued one clock later. The last instruction code is issued three clocks later. At the same time, instruction codes of four independent threads are transmitted to four instruction decode units 807.

The thread status signal 821 is sent to the leftmost integer operation unit 501 only at the time of branching or new thread generation. Branching is always performed in units of four instructions. When the branch destination address is not the beginning of a multiple of 4, the integer operation unit 501 up to the branch destination cannot be used, so that the performance is reduced.
However, if the branch destination address is always arranged in a multiple of 4 by software, the performance does not decrease.

The arithmetic unit control signal 835 is a signal in which instruction codes of a plurality of threads are mixed. The operation unit control signal 835 includes all the control signals used in one integer operation unit 501 and one branch unit 502. It consists only of control signals used in the clock. The control signal executed at the next clock is passed to the instruction decode unit 807 of the next clock by the decoded instruction 836, and is output as the operation unit control signal 837 at the next clock.

<Thread Issue Unit 403> The internal structure of the thread issue unit 403 will be outlined with reference to FIG. The thread issuing unit 403 is a unit that executes a branch instruction and a thread issuing instruction. It is also a unit that stores information on threads that are not operating or threads that are suspended due to external memory access or the like.

The thread issuing unit 403 includes a thread issuing arbitration unit 901, a stack pointer associative memory 902, a thread state memory 903, a thread start preparation flag 904, an instruction cache address tag memory 905, and a local cache bank number having four shift register configurations. Tag 906, instruction cache address comparator 907, thread issuing unit 90
8, a program counter shift register 909.

First, the function of the branch crossbar switch 402 will be outlined. The thread status signal 419 issued from the branch unit 502 is divided into four thread control units 4 according to the contents of the lower two bits of the program counter.
The thread status signal 411 is transmitted by selecting the thread status signal 411 from among the three types. The branch crossbar switch 402 performs this transmission. When a branch to the same thread control unit 403 occurs at the same time, only one is transmitted, and the rest waits for branch acceptance after the next clock in the integer operation unit group 405.

Thread arbitration 901
Is a unit that performs control to restart a thread waiting for a global load or the like in response to a request from the branch control signal 430. This is a round-robin scheduler for preventing that the waiting thread of the adjacent thread issuing unit 403 cannot issue forever if the threads of the thread issuing unit 403 can issue continuously.

When the thread state signal 411, which is the minimum information necessary for a thread, is transmitted from the branch crossbar switch 402, the thread state signal 411 is basically stored in the thread state memory 903 in the order of arrival. At the same time, the stack pointer associative memory 902 at the same address
Stores the upper 4 bits of the stack pointer. In the case of a thread generation or a branch instruction, the thread start preparation flag 904 is set to 1 from the beginning. In the case of a load instruction or a thread waiting for the shared floating-point operation unit 904, the thread start preparation flag 904 is set to 0.

The local cache bank number 906 is
This is a shift register composed of four 4-bit registers. The leading value is input to the stack pointer associative memory 902 via the local memory bank signal 930.
The first registered one of the threads whose local memory banks match is selected, and a thread state signal 936 is output from the corresponding thread state memory 903. Further, the thread start preparation flag 904 is also referred to and transmitted to the thread issuing unit 908.

Program counter shift register 909
Is a shift register composed of four stages of 32-bit registers. If there is no branch or thread issuance, the first value is used for comparing the instruction cache tag.

Next, the instruction cache determination function will be described. The instruction memory 404 is the thread issue memory 40
The cache is accessed once every three accesses, that is, once per four instructions from one thread. However, since four threads exist at the same time, the instruction cache is checked every clock regardless of whether the thread is issued. The program counter is output to the thread status signal 935 from the top of the program counter shift register 909 or from the thread status memory 903. The lower bits of the program counter are used as a program counter index signal 937 to refer to the instruction cache tag memory 905. The upper 20 bits of the program counter 429 are output as a program counter address tag 938. Then, the instruction cache address tag 93
The 9-bit and 20-bit comparators 907 confirm whether they match. If they do not match, a cache miss occurs. In this case, the instruction issued in the future is canceled, and the thread being executed is forcibly branched to the leftmost address of the instruction memory 404.

Finally, the thread: 1. Acquisition authority of thread issuance by thread issuance arbitration 901 The stack pointer is in the local cache bank 90
6 matches the left end. 3. The thread start preparation flag 904 is 1. 4. Instruction cache addresses match. A thread is issued only when all of these conditions are satisfied.

When an instruction cache replacement request or a local memory replacement request occurs, a thread status signal 414 is issued for the time being, but no instruction is executed, and the branch unit 502
8 only.

<Global access control unit 408>
> The internal structure of the global access control unit 408 will be outlined with reference to FIG. Control of the local memory crossbar switch 406 and branch crossbar switch 402, arbitration of memory access other than the local memory 407 unique to each thread, and operation of memory access outside the microprocessor 401, instruction, data memory replacement operation, and interruption of memory Perform acceptance.

Global access control unit 408
Are the branch crossbar switch control 1001, the interrupt vector generation unit 1002, the interrupt input unit 100
3, global data cache tag memory 1004,
Global data cache comparator 1005, global data cache memory 1006, external bus interface unit 1007, local memory crossbar switch control 1008, internal load store interface 1009, branch accepting unit 1010, program counter incrementer 1011, instruction cache replacement buffer 1012, data It is composed of a cache replacement buffer 1013.

The branch crossbar switch control 1001 controls the branch crossbar switch 402 based on a request from the branch receiving unit 1010.

The interrupt vector generation unit 1002
Interrupt input 453 to the interrupt control unit 1003
Create a special thread for In this microprocessor, an interrupt is equivalent to creating a highest priority thread. The thread information is transmitted to the branch unit by the branch crossbar switch control unit 1001.

Global access cache memory 10
04 and the global address tag memory 1005 are 1
This is a 28-bit width cache memory. Used to speed up cache replacement and non-local memory access. A request from the internal load store interface 1009 refers to the content indicated by the global address signal 1021. If the contents of the global access tag memory 1005 match the upper bits of the global address signal 1021, the global data cache memory 1004 and the data bus signal 1010
22 are exchanged.

External bus interface unit 100
7 is an external bus control signal 451 and an external address signal 4
52, and an external data bus signal 453, and receives external data from the external data bus signal 453.

The memory crossbar switch control 1008
The local memory crossbar switch 406 whose connection is changed every clock is controlled. However, the connection is changed only by the rotation operation between the arithmetic unit group 405 and the data cache memory 407, and the connection cannot be changed freely.

Load store interface 1009
Are connected to a global access address bus 427 and a global memory access data bus 428. First, one global access as a load store request from a thread is received. Then, the data is output to the global address bus 1021. For store access to external memory, store data is immediately transferred to global data bus 1
022 and output. Data read from outside is written back to the global memory access data bus 428 unless the data cache is replaced.

Load store branch accepting unit 1010
Is the branch request signal 43 from the four branch units 502
3 to 436, and requests the branch crossbar switch 1001 for control in response to the request.

Program counter control unit 1011
Supplies a boot-time program counter when the microprocessor 401 is started. During operation, a program counter signal 429 from the thread control unit 403 is input, incremented, and the next program counter signal 412 is output to the thread control unit 403.

Instruction cache replacement buffer 101
Reference numeral 2 denotes a latch for synchronizing the replacement of the instruction cache with the resumption of the thread.

Data cache replacement buffer 10
13 simultaneously replaces the four local data caches 407. Replacement data having a width of 128 bits is received from the internal bus 1022, and divided into four clocks, and one local data cache 40 is provided for every 32 bits.
Transfer to 7. <Data cache memory 407> Referring to FIG.
The internal structure of the data cache 407 will be outlined.
The data cache 407 is an S with only one port
It is a RAM, and further has a lock mechanism and the like for inhibiting access from other threads.

The data cache memory includes a one-port data cache RAM 1101, a data tag RAM 11
02, an address tag comparator 1103, and a lock mechanism control function 1104.

The bus lock function is a mechanism for prohibiting access other than a specific thread. When the bus lock state is reached, access from other threads is restricted by the control circuit 11
04 returns an access violation notification signal 1114.

<Shared floating point unit 409> FIG.
, The internal structure of the shared floating-point unit 409 will be outlined. Shared floating point units are 1 at the same time
Only one thread can be used. When the floating-point operation is completed, a request is made to generate a sleeping thread.

The shared floating point unit 409 comprises a local floating point register 1201, a floating point data path 1202, an address decode unit 1203, and an instruction decode 1204.

The floating-point data bus 1202 receives an instruction from the data bus 423 and, at the same time, receives data from a register from the data bus 423 and stores it in the local register 1201. At the end of the operation, the global access control unit 408 is requested to restart the thread. The resumed thread transfers the result data from the local register 1201 to the general-purpose register.

<Program Model of Microprocessor 401> The instruction set of the microprocessor 401 is designed to speed up thread generation, speed up context switch,
It is created for the purpose of concealing branch latency larger than conventional microprocessors. Others are as close as possible to the instruction set of a conventional von Neumann microprocessor. The pipeline stall function for automatically stopping the pipeline due to the occurrence of a register dependency that cannot be forwarded is not implemented in the second embodiment, but is possible.

<Instruction Set> Referring to FIG. 13, a basic instruction set of microprocessor 401 of the present invention will be described.

Basically, similarly to a general RISC microprocessor, there is an instruction set for performing operations only between general-purpose registers and accessing a memory with an explicit load / store instruction. However, general-purpose registers are not basically retained before and after branching. When a cache miss or the like occurs, the register is automatically saved.

The flag register changes according to the result of the integer operation. All instructions have a condition field, whose execution can be controlled by the contents of the flag register. For example, the operation is performed when the zero flag is 1, and the operation is performed when the carry flag is other than 0. Therefore, there is no special conditional branch instruction. This is because it is necessary to avoid using a branch as much as possible because the branch latency is higher than that of the existing pipeline processor.

The operation instruction performs an operation between registers regarding an integer operation. Multiplication, floating-point operation, and the like are coprocessor instructions because the operation unit is shared between threads.

A branch instruction branches to an address obtained by adding a specified register and an immediate value. Since general-purpose registers are not held before and after the branch, necessary registers must be saved on the stack before the branch, and the necessary registers must be read from the stack again after the branch. Since conditional execution is naturally applicable to branch instructions, there is no dedicated conditional branch instruction.

The thread management instruction is used for creating and terminating a thread. The FORM instruction can newly generate a thread of the address, the stack pointer, and the thread information specified by the general-purpose register separately from the current thread. CH
The GTH instruction terminates a conventional thread and newly generates a specified thread. The EXIT instruction terminates the conventional thread.

Synchronous instructions support atomic load stores that are essential for multithreading. The LLOCK instruction locks the accessed local memory bank 407 at the same time as reading data. When another thread loads the memory in the locked state, the pipeline is forcibly installed, and the thread enters a sleep state. The STULK instruction unlocks the locked memory at the same time as storing the data.

The system interrupt instruction restarts the sleeping thread whose thread ID value matches the value indicated by the register value. The behavior is exactly the same as that of an external interrupt.

A coprocessor instruction is an instruction that uses an operation unit shared between threads. The coprocessor instruction uses the general-purpose register of the integer operation unit by directly transferring it as an operand. There is always a limit of one thread that can be used simultaneously.

<Multithread programming model>
Referring to FIG. 14, how the multi-thread program is executed will be described.

The microprocessor 401 of the present invention can simultaneously operate 16 threads, but can always simultaneously process more threads than the number of arithmetic units. The thread 1401 waiting to be executed is divided by the local memory bank indicated by the stack pointer to be used. Threads are stored for each memory bank, and the execution state thread 140
Wait for an empty 2. Only one thread is allocated to one local memory 407 for the thread 1402 in the execution state. Threads in different local memory banks cannot be sent to the running state, even if the thread is free.

All the threads in the execution state can generate another thread by the FORK instruction. The generated thread is stored in the waiting state thread 1401 at a number corresponding to the local memory address of the stack pointer. A thread can stop itself with an EXIT instruction.

In the microprocessor of the present invention, the branch instruction is completely equivalent to the thread switching. In the branch instruction, the thread is put into the waiting thread 1401, and another waiting thread is sent to the execution thread 1402 to be executed. The latency of a single thread is considerably inferior to that of a conventional microprocessor, but the operation of another thread hides the latency. Priority is given to maximizing the use efficiency of the entire arithmetic unit over the processing latency of a single thread.

The instruction memory 1403 is composed of four instruction memories 404. All threads can access one instruction memory 1403. Because threads often issue separate iterations of the loop and use the same code, sharing instruction memory 1403 is useful.

The reason why the thread issuance is limited by the bank of the local memory is to arbitrate as many as 16 local memory accesses. When arbitration is performed for each of the 16 inputs, a reduction in the latency of memory access is inevitable.

<Register Set> The register set of the microprocessor 401 will be described with reference to FIG.

R0 is a register from which 0 is always read and the written value is not held. R1, R2, R3, R
Reference numeral 4 denotes a general-purpose register which can be freely read and written.

SP is a stack pointer, which always indicates the address of the local memory, and can be accessed in one clock. At the time of a context switch, the register is automatically stored, and only the SP is saved. In the case of a thread, the memory bank indicated by the address of the SP is set as a local memory.

[0147] TI indicates a thread state. The TID is a thread ID indicating the currently executing thread by a number, and needs to be separately given to all threads. FLG is an entity of a 4-bit flag register.

PC is a read-only register used to execute a branch relative to the current instruction address.

Among these registers, the information necessary for resuming the thread is only PC, SP, and TI. All other registers are saved to the address indicated by the SP of the local memory at the time of the context switch.

<Memory Map and Load Balancing> Referring to FIG. 16, a local memory arrangement and a thread load balancing method will be described.

The microprocessor of the present invention is premised on multi-threading. Therefore, all the threads that exist at the same time have their own stack. The assignment of a local memory bank to a thread is synonymous with the memory bank indicated by the stack pointer.

In the microprocessor of the present invention, the memory is 1
Disperse into 6 pieces. Threads perform best if they make the best use of local heap memory access. Conversely, the microprocessor according to the present invention uses the OS
It is assumed that heap memory is arranged in consideration of load distribution by

All memory spaces are allocated to local cache memory banks. One local memory bank accesses a continuous memory space of 1 Mbyte. The local memory bank is the address bus 2
It is uniquely determined by the 0th to 23rd bits.

Properly distributing the program load to the 16 pipelines is equivalent to allocating individual local memory banks to processes. Infrequent processes may share one local memory bank and require performance, or processes requiring real-time latency may occupy one or more local memory banks. This alone enables load distribution that does not require OS control such as priority control.

Access to the local cache memory allocated to the thread is completed in one clock. However, access to the other allocated local memory cache requires 16 clocks or more. If the cache misses, access to the outside is further performed, and the latency is undefined. However, access latencies other than the local cache can be concealed by the multi-thread mechanism.

The memory banks that can be accessed by the arithmetic unit are sequentially allocated at the time of startup. For branching, it is not enough that the operation unit at the address of the branch destination is empty, and the memory bank at that time must match the stack pointer. Therefore, in the worst case, the thread may be restarted 16 clocks after the issuance of the branch instruction. In this case, the same memory bank is used, another thread having a different instruction address is prepared, and a thread is issued from a person who can execute the thread first. Naturally, the latency of a single thread is further reduced, but the overall performance can be prevented from being reduced, and the latency of a single thread can be hidden.

<Internal Operation of Microprocessor 401>
Next, the operation of the microprocessor 401 will be outlined.

Referring to FIG. 17, the operation of the basic instruction will be mainly described. In order to show the basic operation of each instruction of the microprocessor 401, the blocks are arranged in the order of operation with the vertical axis as the time axis. The execution of a single instruction has a configuration similar to that of a conventional RISC pipeline processor, except for the first-stage thread issue and the general-purpose register. For a standard RISC pipeline, see Computer Structure and Design Hardware and Software Interfaces (Author David A. Patt
erson / John L. Hennessy publisher Nikkei BP).

In the first ThreadIssue stage, a thread is issued. In the future, it will be referred to as the TI stage as an abbreviation.

This TI stage is not necessary for all instructions, and is executed immediately after branching or thread generation, or every four instructions.

Since instruction reading is performed in units of four clocks, the TAG check of the instruction cache is also performed in four clocks.
It becomes a command place. If the instruction execution program counter is not aligned at 41 due to branching or restart of pipeline stall, the arithmetic unit will not operate until that instruction, but branching is possible.

The replacement of the instruction cache and the data cache is not executed until there are no threads that use the memory bank 407 and do not need to be replaced.

In the next InstructionFetch stage, instructions are read and decoded. It is called an IF stage as an abbreviation.

One program counter is accepted and four instructions are issued at a time. Only the first one instruction is immediately input to instruction decode 814. The following instruction is stored in the latch 806 for one clock, and is decoded at the next clock. The instruction after three clocks is maintained in the latch 806 for three clocks. Instruction decode 814 is 1
Instruction decoding is performed in instruction units. The control signal of the pipeline EX stage is immediately issued, and is passed to the instruction decode adjacent to the right of the subsequent pipeline DF stage and WB stage to control the next and subsequent stages. Conversely, it is output to the arithmetic unit 501 together with the DF stage control and WB stage control signals of the instruction adjacent to the left.

In a typical microprocessor, registers are stored in a register file that is relatively slower than a latch. Then, one pipeline stage called an instruction decode stage (abbreviated ID stage) is formed by pairing the decode and the access of the register. However, the microprocessor 401 of the second embodiment includes:
Since the number of registers is small and the clock is shifted to the right at every clock, the drive is performed directly from the latch without the register file. However, an independent ID stage is required depending on the speed of instruction cache reading and instruction decoding.

In the next Execution stage, an operation is performed. It is called EX stage as an abbreviation.

In accordance with the decoded instruction content, a register or data from the DF stage or WB stage of an already executed instruction is selected from the operands used in the operation. Three operand values are prepared and the integer operation ALU6
30, the barrel shifter 631, the store aligner 632, etc., and store the result in the latch 609 or the like.

When the instruction cache is accessed, the instruction TAG is checked by the comparator 909. When a miss occurs in the instruction cache, the DF and WB stages following the instruction become invalid.

In the next DataFetch stage, the data memory is accessed. It is called a DF stage as an abbreviation.

In the load store instruction, the ALU 630 is used to calculate an address. The calculated address is immediately sent to the local cache memory 407 via the crossbar switch 406. In the case of a load instruction, the data is immediately read out and sent to the original processor via the crossbar switch 406 and the load aligner 710.

In the case of a store instruction, since it is necessary to determine a local memory address and a cache miss, it is not immediately written in the DF stage. After the determination in the DF stage, data is written at a timing corresponding to the DF stage of the next instruction. In this case, the data cache 407 is desirably configured to be able to process independent read / write simultaneously, because the read operation in the DF stage of the next instruction is mixed.

The access to the global memory is determined in the DF stage in parallel with the access to the local memory. If the access is a global read access, the branch unit 709 shifts to a thread waiting state.

In the case of a branch instruction, the branch destination program counter is calculated by the ALU 630 and sent to the thread issuing unit 403 by the branch unit 709 together with the SP and the TI register.

In the case of pipeline stall such as global data read, the current program counter is sent to the branch unit 709 as it is, and branch processing is performed. When the branch instruction is taken, the built-in sequencer automatically rewrites the other general-purpose registers to the stack in the DF stage of the subsequent clock.

In the last WriteBack stage,
Write back to the register. Abbreviated name is called WB stage.

In a conventional microprocessor, this is a stage provided for a relatively slow register file. Since access to the local memory is likely to be a critical path, if the load data from the local cache memory 407 cannot keep up with the latch 702,
Processing such as the load aligner 710 also enters the WB stage. In that case, ALU from WB stage to EX stage
Data forward is impossible, and the data load latency is reduced.

<Overall Diagram of Pipeline> The coexistence of pipelines in the microprocessor 401 of the present invention will be described with reference to FIG.

The microprocessor of the present invention has 16 pipeline microprocessors connected to each other. Therefore, circuits equivalent to 4 + 64 = 68 pipeline stages are simultaneously present on one chip.

In a normal multiprocessor, a plurality of pipeline stages are completely independent, and one thread is statically allocated to one processor. In the microprocessor 401 of the present invention, one thread can use all of these 68 pipeline stages, but only five can be used at the same time. However, if attention is paid to one thread, a notation equivalent to the operation of a normal five-stage pipeline processor such as 1801 can be obtained. However, the difference is that the same circuit is not used successively and the pipeline stage adjacent to the right is always used. The microprocessor of the present invention has a Th
16 threads from read2 to Thread8 can operate simultaneously. No two pipeline stages are used at the same time. For example, if Thread2 is I
At the time when F2 is used, Thread 14 is set to IF
3 is used. At the time when the thread 2 uses DF2, the Thread 14 uses DF3.

<Pipeline Operation in Branch Instruction> The operation of a branch instruction will be described with reference to FIG.

The branch instruction does not save the register before and after it. Therefore, it is necessary to explicitly save the register. The branch instruction is executed in the DF stage, and places thread 1 in a wait state. The vacant bank is
In the next TI stage, the thread 4 in the waiting state is issued.

If the integer arithmetic unit whose lower four bits of the instruction address of the branch destination match is not used, the thread 1 in the waiting state accepts the branch and restarts the thread 1. Even if a thread is issued, the operation starts only when the pipeline reaches an arithmetic unit that also matches the lower two bits of the instruction address.

<Operation of Pipeline in Pipeline Install> The operation at the time of a cache miss will be described with reference to FIG.

Since unexpected matters such as cache misses need to be hidden from the processing of instructions, it is necessary to save registers automatically. An instruction cache miss found in the EX stage causes the EX stage of the immediately following instruction to be passed to the stack pointer address calculation. If another thread 4 can be started when the four register states have been saved, the thread is restarted.

Thread 1 is restarted from the instruction four instructions before, and the four registers are stored again.

<Details of Internal Operation of Microprocessor>
The following describes in detail how the internal operations of the instructions described so far are implemented.

First, the branching and thread generation operations will be described. In the microprocessor of the present invention, both the branch and the thread generation are performed by the thread issuing unit 403.
Of the thread structure to the The difference between branching and thread creation is that the former releases the original pipeline and runs another thread, while the latter continues executing the original pipeline.

Next, the operation of the pipeline stall will be described. In the microprocessor of the present invention, the pipeline stall is a branch to its own address accompanied by automatic register saving. The branch is executed at least 16 clocks after ending operations such as cache replacement and exception processing. When stopping the pipeline due to an exception event, the pipeline is always installed.

Next, an instruction cache miss will be described. The instruction cache is always determined by the thread issuing unit 403. If the instruction cache needs to be replaced, it immediately becomes pipeline stall. At the same time, a request for instruction cache replacement is made to the global access unit 408 and the thread issuing unit 403. In the instruction cache replacement cycle, instruction replacement and thread resumption are performed simultaneously. The instruction replacement bus 432 having a width of 128 bits is used to prevent the interference of other threads, and is performed in the first clock of the read of the resumed thread.

Next, a memory load store to the local cache memory 407 will be described. One local cache memory 407 uniquely owned by a thread can be accessed unconditionally in one clock. The data store cannot be written without waiting for the judgment of the local bank and the judgment of the tag of the cache.
Writing will be performed on the stage. DF of next instruction
If the stage is a load, the data write is carried over to the next clock. However, except in the case of a cache miss, the pipeline does not stop by the combination of reading and writing to the local cache.

Next, the operation of storing data in a memory other than the local memory will be described. For the local cache memory 407 not owned by the thread, it is necessary to aim for a timing at which the thread possessing the local memory does not access the memory. The local address signal 521 and the local data bus signal 524 are held when another thread held in the address buffer 707 and the data buffer 709 and holding the cache bank to be accessed arrives.
Output to However, when the original thread performs load store, that thread has priority in the first time. After waiting for 16 clocks, the second time, the original thread can be pipeline-installed and output to the local cache. The original thread load store is stored in the address latch 704 and the data latch 705 and executed at the next clock regardless of the instruction.

Next, a data cache miss will be described. The thread that owns the data cache memory bank as the SP memory bank generates a pipeline stall when a data cache miss occurs,
The register can be saved. In the case of a cache miss of the stack pointer, the latch is held, and the register is saved after the cache in the stack area is replaced.

A thread that does not possess the data cache memory bank as the SP memory bank immediately switches to global memory access when a data cache miss occurs, and reads a value from outside. No cache replacement operation is performed.

The cache miss of the stack pointer inhibits the operation of another thread being replaced, and shifts and holds the state on the pipeline.

Next, global memory access will be described. A cache miss of the local cache 407 or access to an external memory not assigned to the cache occurs.

When a global memory access occurs, the branch control 711 requests the arbitration of the global access buses 427 and 428 to the branch / load store unit. Until the bus can be acquired, the data is stored in the address buffer 707 and the data buffer 708.

The global memory does not accept input from another thread until a series of data read / write and cache replacement are completed. The data is transmitted from the branch crossbar control unit 1001 to the thread issuing unit 503 simultaneously with the end of the read / write operation.

The read value is input to the data cache replacement bus 425, and transmitted to the local cache after four clocks. This allows four data cache replacements at the same time.

Next, an external memory access will be described. External memory access occurs at the time of a global memory data cache miss. Address bus 1022
Is output to the external address bus 452 as it is. Data is sequentially transferred to the data bus 1023 every 32 bits.
To the global bus 1022.

Finally, the interruption will be described. In the microprocessor 401 of the present invention, an interrupt response is equivalent to thread generation by employing a high-speed context switch mechanism. That is, the thread generation unit 4
It is only necessary to create a thread for the thread state prepared in 03. The interrupt unit 1005
The interrupt vector number is transmitted to the interrupt vector generation unit 1002. Interrupt vector generation unit 1002
Generates a program counter, a stack pointer, and thread information according to the type of interrupt, and transmits the generated information to the thread control unit 403.

<Example of Multithread Programming> Referring to FIG. 21, an actual method of using threads will be described. Thread A generates thread B and performs parallel processing. After confirming both ends, the original thread A is resumed.

The thread A stores 2 in the shared variable, and uses the unused SP from the OS to create the state of the thread B.
And TI are obtained.

Both threads branch to the same LabelC, and access the shared variable Counter atomically. The thread that reached the second time is Counter
To 0, at that point the Label of the following code
D can be restarted. And the SP and TI of the original thread A
Inherit the state. Any number of threads can be run in parallel in the same way.

<Load Balancing Method> The load balancing will be described with reference to FIG.

All processes and threads request a stack and a heap area from the OS. A process that requires processing power can exclusively acquire a stack or heap area over one or more memory banks from the OS.

In this figure, process A has three processors, processor B has two processors,
There is little interruption by other processes. In this way, processes that require real-time processing power
A guarantee of load distribution can be obtained.

<Embodiment 3> The internal structure of a microprocessor 2301 according to a third embodiment of the present invention will be described with reference to FIG.

The microprocessor 2301 is used in the second embodiment.
In addition to the microprocessor 401, a multiplier and a floating-point arithmetic unit are mounted on an integer pipeline, and a multiprocessor structure is introduced. In the multiprocessor, not only a memory sharing mechanism but also a mechanism for performing thread management between the multiprocessors is introduced. The memory is deliberately connected directly to the microprocessor and distributed to ensure a communication bandwidth with the memory.

The difference between the microprocessor 2301 of the third embodiment and the microprocessor 401 of the second embodiment is only the operation unit group 2305 and the global access control unit 2308.

<Operation Unit Group 2305> The internal structure of operation unit group 2305 will be described in detail with reference to FIG. In addition to the integer operation unit group 405, multiplication,
And built-in floating point function.

At the same time as the four operation units 501, two multiplication / SIMD units 2401 and one floating point operation unit 2402 are incorporated. They share the floating point register 2403. Then, the operand data crossbar switch 2404 adjusts the instruction execution timing.

The floating-point register 2403 is the same shift register as the general-purpose register in the integer operation unit, and is transmitted at four clocks.

Operand data crossbar switch 240
4 connects instruction issuance from all integer arithmetic units 501 to the leftmost operand input of floating point arithmetic unit 2402. Then, the result data is transferred to all four timings of the floating-point register 2403.

[0214] These multiplication units 2401 are implemented as instructions and are not coprocessors. In addition, there is no need to wait for a thread to synchronize as in the case of a branch or global data load. Therefore, in one arithmetic unit group 2305, four processors are 2
It is the same as sharing one multiplier and one floating point arithmetic unit.

This floating point unit 2402 can execute one floating point instruction per one operation unit group 2305. The address of the instruction may be arbitrary. However,
If a floating-point operation of two or more instructions appears in four instructions, the pipeline is stuck and restarted after 16 clocks. In the case of a multiplication instruction, the number is up to two instructions. Therefore, there is no restriction on the arrangement of floating point units in the program model. Simply exceeding the limit only slows down execution.

[0216] The floating point unit 2402 can cope with variable latency instructions such as a division instruction. However, the thread that has executed the instruction is in a waiting state until the end of the division instruction. This is the same operation as the load instruction to the global memory.

<Global access unit 2308>
Referring to FIG. 25, global access unit 230
8 will be described. The difference from the global access unit 408 of the second embodiment is that the external local bus and the external shared bus are separated, and that a thread can be generated from the external shared bus. Therefore, the only difference is the shared bus interface 2501 and the local bus interface 2502.

External shared bus interface 2501
Has a function of reading data from an external device and allowing the external microprocessor 2301 to access its own local bus.

In the case of external memory access, the local memory access control unit 2503 obtains the arbitration of the internal address bus 1022 and the internal data bus 1023, and
8. Control the local bus interface 2502.

[0220] The microprocessor 2301 of the present invention comprises:
The method of maintaining cache coherency between multiprocessors is somewhat different. Since the local memory caches 407 cannot have data of the same address, there is no need for arbitration. However, for the purpose of accelerating the access from outside the chip, the global cache memory has a local cache memory 4 of another processor.
07 may exist. In this case, it becomes necessary to perform cache coherency control between the global caches 1007.

<Multiprocessor System> Referring to FIG. 26, a microprocessor 2 according to the third embodiment of the present invention will be described.
An example of a system using 301 will be described.

The memory 2611 has a local bus 2612
Through to the microprocessor 2301 directly. The shared bus 2613 is connected to the microprocessor 2301
It is used for communication between each other and connects a shared I / O device 2614.

The local I / O device 2615 is a device requiring a memory bandwidth such as a graphic accelerator. It is directly connected to the local bus 2612 of the microprocessor 2301 to secure a communication bandwidth with the microprocessor 2301.

The memory can be distributed by hardware of the thread communication mechanism of the microprocessor of the present invention. For access to a memory area not owned by the microprocessor itself, there is a method of actually issuing a transfer request between the microprocessors. However, even if the data is not directly transferred, the microprocessor 23 having the memory
01 can generate a thread for performing data processing. In this case, the bandwidth of the shared bus 2613 can be minimized.

<Multiprocessor Memory Map> FIG.
7, the memory space of a multiprocessor system using the microprocessor 2301 of the present invention will be described.

The memory space of each microprocessor 2301 is statically allocated to the memory space 2702 of the system. Unlike the microprocessor 301 of the conventional example 2, the microprocessor which receives the transaction output to the shared bus is uniquely determined with respect to the address.

Object 2711 Requiring Communication Bandwidth
And the object 2712 are arranged in the same microprocessor 2703. Since the object 2713 does not require a communication bandwidth with the object 2711,
It can be located in the microprocessor 2704. Thus, the communication bandwidth between objects can be optimized by allocating the memory.

<Multiprocessor Shared Bus Transaction> Referring to FIG. 28, the contents of a bus transaction between multiprocessors will be described.

In addition to a single data access and a burst data access of a normal microprocessor, there are a single access with a lock required for a shared memory and a thread generation request command between microprocessors. Conversely, the cache coherency control command existing in the multiprocessor of the second conventional example is not required.

<Effect of Loop Unrolling> The effect of loop unrolling will be described with reference to FIG.

The microprocessor 401 of the present invention is always executed by an arithmetic unit corresponding to the lower 4 bits of an instruction. That is, if the lower 4 bits of the instruction having a high utilization rate are biased, there will be an unused operation unit. This problem can be solved by a general speed-up technique, loop unrolling.

Reference numeral 2901 denotes a program of one thread. Reference numeral 2902 denotes 16 arithmetic units. The code of 2901 uses only six instructions, and uses only the first six arithmetic units. In other words, the remaining pipeline 2904 is completely passed to another thread. However, if there is no request from other threads to make up for it, performance cannot be exhibited.

[0233] Therefore, 3
Combine one thread into one and extend one thread to 14 instructions. Reference numeral 2911 denotes an inline one thread program. Thereby, the arithmetic unit 29
12 will be used 14 pieces.

Also, for a general long thread,
Adjusting to an instruction length that is a multiple of 16 gives the best performance.

[0235]

The effect of the microprocessor of the present invention is as follows.
The logic performance per clock, frequency performance, programming model, chip area, and low power consumption will be described separately.

<Logical performance per clock>

The microprocessor of the present invention has the following advantages in the operation performance. 1. Parallel processing by multi-thread operation is possible. 2. It is possible to hide the access latency to the external memory by multithreading. 3. Thread instructions and data can be easily shared, and it is also effective for small-scale iteration-type parallelism.

The microprocessor of the present invention is inferior to the conventional pipeline microprocessor because the branch latency is large at the speed of a single thread. However, it is more than compensated for by multithreading and parallel processing.

Hereinafter, quantitative prediction of performance in general-purpose applications will be described. Computer Archi
technology: A Quantitative Ap
Provision Second Edition (Author)
John H. Hennessy AND David
A. Patterson Publisher MorganKa
ufmann Pubishers, Inc. Use the statistical data described in). Hereinafter, this document is referred to as Reference Document 1.

From the standpoint of a single thread, the microprocessor of the present invention is substantially equivalent to a microprocessor under the following conditions. -General-purpose register 5 load store register model-16K byte direct map instruction cache-1K byte direct map data cache-Branch latency is undefined For simplicity, it is assumed that a single thread uses only a local memory bank.

In the microprocessor of the present invention, assuming that sufficient threads are shared, the overall performance is obtained by subtracting the overhead of the context switch caused by load store, branch, and cache miss. It is assumed that the interlock due to the register dependency has been removed by the scheduling of the compiler.
According to the statistical data of p105 and p384 in Reference 1, the frequency of load store instructions: 35% of all instructions, the frequency of branch instructions: 20% of all instructions, and the probability of a data cache miss in load stores:
24.61% ・ Probability of cache miss of 16K byte instruction cache: 0.64%

The following is a predicted value of the number of clocks required for a context switch. It is assumed that the instruction addresses of the thread at the context switch destination are evenly distributed. It is assumed that the penalty for data cache replacement can be hidden by the operation of another thread. Branch instructions: 7.5 clocks on average, occurring at a frequency of 20% Pipelining: 9.5 clocks on average, 9.2
Occurs at a frequency of 5%

Under the above conditions, one pipeline IP
The C performance (the number of executed instructions in clock units) is about 0.3. In the overall microprocessor of the present invention, since the 16 pipelines hardly interfere with each other, a value less than 4.8, which is 16 times this value, is the overall IPC performance.

As described above, in the microprocessor of the present invention, the penalty of the branch instruction is very large, which hinders the performance. If the number of branches is reduced by the loop unrolling technique, the performance can be further improved.

In the following, the performance will be predicted on the assumption that the frequency of branch instructions is reduced to once every 64 instructions by loop unrolling. In this case, the IPC is about 0.5. The overall IPC improves to near 8.

Further, when the number of arithmetic units is increased,
Increasing the transfer capacity of the replacement of the data cache hardly interferes with the performance of a single pipeline. Therefore, a linear increase in performance with respect to the input hardware resources can be realized.

<Frequency Performance> Although the microprocessor of the present invention has a large number of arithmetic units integrated therein, the structure of a pipeline for each instruction is almost the same as that of a normal microprocessor. There is no increase in selector inputs or register ports due to an increase in the number of parallel operations.

In the VLIW type microprocessor, the transfer between the result data, operands, and the register file becomes complicated as the number of arithmetic units increases, and the speed is suppressed. On the other hand, in the microprocessor of the present invention, by limiting data transmission between the operation units in a single direction, the transfer of operands between the operation units can be realized by a simple circuit, and the number of circuit stages can be reduced.

Further, since the arithmetic units are adjacent to each other, the wiring between the arithmetic units is the shortest distance. The transfer between the arithmetic unit and the local data cache is the only long-distance wiring.

With the above effects, frequency performance equal to or higher than that of a conventional pipeline system, VLIW system, or other microprocessor can be obtained. Especially,
It is excellent in that it is easy to achieve both improved parallel performance and frequency performance.

<Programming Model> The microprocessor of the present invention employs a general instruction set
It is almost the same as a microprocessor, and can create programs using the general concept of multithreading.

The advantages of the programming model for the existing microprocessor of the present invention are mainly verticality with increased parallelism, multi-thread support, simple load balancing, and multi-processor verticality. Each will be described in detail.

First, the verticality associated with the improvement in the degree of parallelism will be described. In the VLIW microprocessor of the first conventional example, it is necessary for a compiler or the like to appropriately arrange processes to be executed simultaneously each time.
A large number of completely independent processes can be executed simultaneously without modifying the program. Further, even when the number of the arithmetic units 405 is further increased, the performance can be improved by using the multi-thread program created first as it is.

Next, multithread support will be described. Synchronization of a multi-thread program in an existing microprocessor requires either thread synchronization waiting by spin lock or explicit call of a scheduler of the OS. The microprocessor of the present invention does not require either of them, and enables high-speed context switching without the intervention of an OS by using a thread generation / deletion instruction and an automatic context switching mechanism. This makes it possible to realize high-speed synchronization between threads with a natural description.

Next, load distribution will be described. This is a mechanism in which the stack of objects and the memory arrangement of the heap distribute the load as it is. Therefore, there is no need to use complicated OS functions such as priority control between processes.
The computing resources of the microprocessor can be uniformly distributed to the threads.

Finally, multiprocessor load distribution will be described. When a plurality of microprocessors of the present invention are used, a multi-thread program developed on a single microprocessor of the present invention can be used as it is. O
Only the heap memory allocation mechanism of S needs to manage the information of the multiprocessor and distribute the load.

<Chip Area> To show the effect of reducing the chip area of the microprocessor of the present invention, Compute
r Architecture Pipelined
And Parallel Processor D
design (author Michael J. Flynn)
The model is based on the description of p96.

In the second embodiment of the present invention, the predicted area value of each unit is as follows. Unit A corresponds to 1 mm square in a 1 micron process. -Integer operation unit 405 7A x 16-Data cache 407 4A x 16-Instruction memory 404 13.4A x 4-Thread issuing unit 402 Approx. 4A x 4-Global data cache 8K 26.6A-Shared floating point unit 409 37.8A Under this condition, the integer operation performance is 16 parallel at maximum.

Assuming that the control circuit required for the memory is 30%, the overhead associated with wiring is reduced by 50% in the logic section.
% And 15% in the memory section. In this case, the logic section becomes 248.7A, the memory section becomes 216A, and the final processor area becomes 464.7A.

Assuming that the overhead to be mounted on an actual semiconductor die is 20%, the chip area is 557A.
The chip area at 25 microns is 34 mm square.

The conditions of the third embodiment of the present invention will be described. The following units are added to the second embodiment. The calculation performance is
The integer operation performance becomes 16 parallel in 8-bit units, and the floating point becomes 4 parallel. 16-bit SIMD integer multiplier 2401 20A × 8 Double-precision floating-point addition multiplier 2402 37.8A × 4

Under the same preconditions, the logic section is 65
8A, and the final processor area is 878A. The chip area is 1050A, and the chip area at 0.25 micron is 65 mm square.

For comparison with the existing microprocessor, the MMXPentium microprocessor from Intel Corporation of the United States is cited. 0.2 of this microprocessor
The chip size of the 5 μm plate is 95 mm square. The microprocessor has a maximum degree of integer parallelism of 2, a floating point of 1, and a maximum of 16 even when using SIMD instructions in byte units.

Furthermore, the microprocessor of the present invention
Natural expansion of the number of parallel units such as arithmetic units is possible. That is the reason for both the hardware configuration and the software compatibility.

First, for an n-fold increase in the number of arithmetic units, the data cache memory is O (n), and the increase in the instruction memory is O (n) or less.

The increase in the number of bus lines between the operation units can be reduced to O (n). The existing super scalar method, VLIW method, is in contrast to O (n × n) in order to guarantee free transfer between all the arithmetic units.

In the microprocessor according to the present invention, the increase in the circuit size beyond the linear increase is caused by the branch crossbar switch 4.
02 and the data crossbar switch 406. It is unavoidable that the increase will be on the order of O (n × n) as it is. However, regarding the data crossbar switch 406, since the arrangement order of the memory banks at the transfer destination is fixed, the same system as the barrel shifter can be adopted if the reduction in local memory access latency is tolerated. In this case, the order of circuit increase can be O (n × logn).

<Low Power Consumption> There are a large number of technologies for low power consumption, but means for reducing power consumption at the architectural level can be realized by minimizing circuits and wiring for performance. The microprocessor of the present invention minimizes circuitry and wiring for performance. Specifically, there are the following advantages as compared with the conventional microprocessor.

Compared with a superscalar processor, by eliminating instruction-level parallelism that requires the transfer of complicated results, the circuit and wiring can be reduced by minimizing the degree of freedom in data transfer. I made it.

It can be said that the distance of the transmission of the result of the operation is minimum even though it is a multiprocessor. The only long-distance bus lines that become critical are signals to the local memory cache. Therefore, the wiring capacity of the entire chip can be minimized.

It is possible to reduce the instruction memory capacity and the replacement frequency by sharing the instruction cache between the arithmetic units. Since the instruction memory is likely to have the same copy in performing the routine processing, the capacity of the instruction memory can be reduced by sharing the instruction cache. For the same reason, the replacement frequency of the instruction cache can be reduced.

It is also possible to omit the data memory by sharing the data memory between the arithmetic units. In a general multiprocessor, even when sharing data, each of them must own a data cache. However, in the microprocessor of the present invention, all data is stored in one data cache, and a plurality of data caches have the same contents. Is not stored.

With these effects, power consumption for performance can be minimized.

<Sacrifices> Although the microprocessor of the present invention has performance that surpasses conventional microprocessors in most respects, it also has some disadvantages not found in conventional microprocessors.

First, there is no compatibility. Naturally, a multi-thread program is assumed. However, except for the object-oriented optimization and the multi-thread function, the programming model is close to the conventional RISC instruction, and software porting is easy.

Second, the performance of a single thread is lower than that of a conventional microprocessor. The reason is that the branch latency is huge and the latency of memory access outside the bank is relatively large. However, since another thread can operate at either latency time, the overall performance can be concealed to some extent.

Second, the latency of data access is large. In an object-oriented programming model or the like, it is necessary to always allocate data access ranges and locations to local memory. However, the object-oriented programming model is still a widely used technique for creating software, and it is useful to be able to improve performance by explicitly specifying it in a form that is compatible with it.

Lastly, the operation efficiency of the arithmetic unit is lower than that of the conventional super scalar system or the like. In the microprocessor of the present invention, since the thread cannot be restarted until the address arrangement of the memory bank and the instruction match,
A situation occurs in which the arithmetic unit cannot operate at all because the appropriate thread cannot be started. However, the problem does not occur unless the branch and the memory access outside the memory bank are performed. Therefore, in an application that should provide high performance, tuning may be performed by means such as loop unrolling.
Since the overall degree of parallelism can be greatly increased, the performance improvement by tuning is large.

<To further improve the performance> The increase in the number of general-purpose registers contributes to the reduction of the bandwidth to the local memory. However, it is necessary to make a trade-off decision to increase the evacuation state of the context switch. Means such as switching by a register window without saving the register can also be considered, but this naturally increases the scale.

The effect of improving the bandwidth of the replacement of the data cache is great. At present, since one 32-bit global data bus is used to replace the data cache, it is obvious that the replacement penalty is large. It is desirable to adopt a 128-bit bus or the like for replacement, or to replace a plurality of data caches in parallel.

The branch prediction mechanism helps reduce pipeline vacancies during context switches. However, in the microprocessor of the present invention having the latency hiding function,
The effectiveness of the branch prediction mechanism is not so absolute. Whether to use transistors for increasing the number of parallel processing units or to enhance the branch prediction mechanism is determined by a trade-off with respect to required performance.

<Summary of Comparison with Conventional Method> Finally, the results of comparison between the microprocessor of the present invention and the conventional microprocessor will be summarized.

Low power consumption compared to superscalar system
There is an advantage that there is no limit on parallelism. On the contrary, there is a disadvantage that they are not compatible.

Compared to the VLIW system of the first conventional example, the same program can be used to achieve the performance with no parallelism limit, an increase in the number of arithmetic units, or even in a multiprocessor configuration. There is an advantage. The disadvantage is that the thread issuing mechanism is complicated.

Compared to the shared memory multiprocessor of Conventional Example 2, there are advantages that the circuit scale for the performance is small and that the performance can be easily improved by dividing the memory. On the contrary, it can be said that the existing multiprocessor compatible OS cannot be used.

[Brief description of the drawings]

1 is a diagram of a first embodiment of the present invention. FIG. 2 is a diagram of a VLIW processor of a first conventional example. FIG. 3 is a diagram of a multiprocessor system of a second conventional example. FIG. 4 is a diagram of a second embodiment of the present invention. Fig. 6 is a detailed configuration diagram of one integer operation unit in Fig. 5 Fig. 7 is a detailed configuration diagram of one branch unit in Fig. 5 Fig. 8 is a configuration diagram of an instruction issuing mechanism of Fig. 4 FIG. 10 is a block diagram of the global access unit of FIG. 4. FIG. 11 is a block diagram of the data cache memory of FIG. 4. FIG. 12 is a block diagram of the shared floating-point unit of FIG. 4. FIG. FIG. 15 Register set table FIG. 16 Memory configuration diagram FIG. 17 Diagram of pipeline execution of a single instruction FIG. 18 Conceptual diagram of pipeline operation of entire chip FIG. Red switching operation diagram FIG. 20 Pipeline installation operation diagram FIG. 21 Program example using threads FIG. 22 Load distribution method FIG. 23 Overall diagram of third embodiment FIG. 24 Detailed diagram of arithmetic unit group in FIG. 25 Diagram of global access unit in FIG. 23 FIG. 26 Example of system configuration using microprocessor of third embodiment FIG. 27 Multiprocessor memory layout diagram FIG. 28 Bus transaction diagram of shared bus FIG. 29 Utility of loop inline expansion

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Microprocessor 2 Instruction issue control 3 Program counter storage means 4 Instruction storage means 5 Operation means 6 Dynamic signal connection means 7 Data storage means 8 External interface 201 Instruction address generation 202 Instruction cache 203 Instruction decode 204 Data crossbar switch 205 Branch unit 206 Load store unit 207 Operation unit 208 Register file 209 Data cache 210 External bus interface 301 Microprocessor 302 Microprocessor 303 Microprocessor 304 Shared bus crossbar switch 305 Data memory 306 Data memory 307 Dedicated operation unit 308 I / O device 311 Instruction cache 312 Instruction Issue control 313 Integer arithmetic unit 314 Floating point arithmetic unit 31 Load store unit 316 Data cache 317 Cache coherency control unit 401 Microprocessor 402 Branch crossbar switch 403 Thread control unit 404 Instruction memory 405 Integer operation unit group 406 Local cache access crossbar switch 407 Local cache bank 408 Global access control 409 Shared special operation unit 411 Thread status signal 412 Program counter signal 413 Control signal between thread control units 414 Thread status signal 415 Instruction code signal 416 Pipeline data bus between integer operation units 417 Global memory access address bus 418 Global memory access data bus 419 Thread status signal 421 Local cache Ad Bus 422 local cache data bus 423 shared processor address bus 424 shared processor data bus 425 data cache replacement bus 426 local cache crossbar switch 406 control signal 427 global access address bus 428 global access data bus 429 program counter signal 430 branch crossbar switch 402 Control signal 431 Instruction code signal 432 Instruction replacement data bus 433, 434, 435, 436 Global access request signal 437 Thread status signal 450 Processor external data bus 451 Processor external control bus 452 Processor external address bus 453 Processor external interrupt request signal 501 Integer operation Unit 502 Branch unit 503 Branch arbiter 5 11, 512, 513, 514 Instruction decode signal 515 Data bus group 516 Branch unit status signal group 521 Local memory access address bus 522 Global memory access address bus 523 Local memory access data bus 524 Global memory access data bus 525, 526, 527, 528 Branch request signal group 601 Program counter latch 602 Stack pointer latch 603 Thread ID latch 604 Decoded instruction code latch 605 Program counter latch 606 Condition execution instruction control signal latch 607 Flag register latch 608 Flag register update latch 609 ALU operation result flag latch 610 ALU Operation result latch 611 Barrel shifter Operation result flag latch 612 Barrel shift Operation result latch 613 Store data latch 614 Register write-back data holding latch 615 First general register latch 616 Second general register latch 617 Third general register latch 618 Fourth general register latch 619 Stack pointer latch 621 Program counter update selector 622 Program counter Constant generation circuit 623 Flag register update selector 624 Condition execution instruction control circuit 625 Program counter bus 626 Constant generation circuit 627 First operand selector 628 Second operand selector 629 Store data selector 630 ALU circuit 631 Barrel shifter 632 Store align circuit 633 Register between threads register forward Bus 634 first general register update selector 635 second general register update selector Lector 636 Third general register update selector 637 Fourth general register update selector 638 Stack pointer update selector 639 Stack pointer signal 640 Memory store data bus 641 Operation result bus 642 Data write back bus 643 First operand bus 644 Second operand bus 645 Third operand bus 646 Condition execution control signal 647 Thread status signal 701 Thread status latch 702 Load data latch 703 Load data holding buffer 704 Local memory write data latch 705 Local memory write address latch 706 Address selector 707 Address buffer 708 Store data selector 709 Store Data buffer 711 Thread state update selector 711 Branch control unit 71 Load aligner 713 Local memory access check 714 Branch accept signal 801 X decoder 802 RAM cell 803 Sense amplifier and write buffer 804 Instruction memory access control 805 Instruction selector 806 Instruction code latch 807 Instruction decode unit 821 Thread status signal 822 Program counter 830, 831 832, 833 Instruction code 834 Decoded instruction 835 Operation unit control signal 836 Decoded instruction 837 Operation unit control signal 838 Decoded instruction 839 Operation unit control signal 840 Decoded instruction 841 Operation unit control signal 842 Decoded instruction 851 Instruction replace bus 901 Thread issue arbitration 902 Stack pointer associative memory 903 Thread State memory 904 thread start preparation flag 905 instruction cache address tag 906 local cache bank number 907 instruction cache address comparator 908 thread issue unit 909 program counter shift register 921 thread issue arbitration request 922 thread issue arbitration request 923, 924 local cache bank signal 925, 926 Program counter signal 931, 932, 933 Thread status memory word line signal 934 Local cache bank signal 935 Thread start preparation flag signal 936 Thread status signal 937 Program counter index 938 Program counter address tag 939 Instruction cache address tag 1001 Branch crossbar switch 40 Control 1002 Interrupt vector generation unit 1003 Interrupt input unit 1004 Global address tag memory 1005 Global address tag comparator 1006 Global data cache memory 1007 External bus interface unit 1008 Local memory crossbar switch 406 control 1009 Internal load store interface 1010 Load store branch receiving unit 1011 Program counter incrementer 1012 Instruction cache replacement buffer 1013 Data cache replacement buffer 1021 Address bus 1022 Data bus 1101 Data cache RAM 1102 Data cache tag RAM 1103 Address tag comparator 1104 Protection mechanism check 1111 Address bus 1 12 Data bus 1113 Read / write control signal 1114 Access violation notification signal 1201 Floating point register 1202 Floating point data path 1203 Address decode unit 1204 Instruction decode unit 1401 Thread waiting 1402 Thread running 1403 Instruction memory 1801, 1802, 1803 Thread 2301 Microprocessor 2305 Operation unit group 2308 Global access control unit 2350 Global address / data bus 2351 Global control bus 2352 Interrupt signal 2353 Local control bus 2354 Local address bus 2355 Local data bus 2401 Integer multiplication unit 2402 Floating point operation unit 2403 Floating point register unit 2404 Output bus 2501 Shared bus interface 2502 Local bus interface 2611 Local memory 2612 Local bus 2613 Shared bus 2614 Shared I / O device 2615 Local I / O device 2616 Local I / O device 2701 OS 2702 Memory space 2703, 2704, 2705 Microprocessor local Memory space 2711, 2712, 2713 Object 2901 One thread program 2902 Integer arithmetic unit array 2903 Integer arithmetic unit 2904 Inactive integer arithmetic unit 2911 Inline thread program 2911 Integer arithmetic array 2913 Integer arithmetic in use state Machine

[Procedure amendment]

[Submission date] December 2, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 1

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claim 9

[Correction method] Change

[Correction contents]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] Claim 10

[Correction method] Change

[Correction contents]

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] Claim 11

[Correction method] Change

[Correction contents]

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] Claim 12

[Correction method] Change

[Correction contents]

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] Claim 13

[Correction method] Change

[Correction contents]

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] Claim 14

[Correction method] Change

[Correction contents]

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] Claim 15

[Correction method] Change

[Correction contents]

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] Claim 16

[Correction method] Change

[Correction contents]

[Procedure amendment 10]

[Document name to be amended] Statement

[Correction target item name] Claim 17

[Correction method] Change

[Correction contents]

Claims (17)

[Claims] An instruction selection value storage means for accumulating an instruction selection value, an instruction selection value storage means for outputting an instruction in response to an instruction selection value input, an operation means for performing an operation in accordance with the content of the instruction, Temporary storage means for storing results and the like, having a plurality of arithmetic processing elements composed of these, and transmitting an instruction selection value and an operation result of the arithmetic processing element to an instruction selection value storage means and an arithmetic means of an adjacent arithmetic processing element; An information processing apparatus characterized in that another arithmetic processing element is repeatedly connected in series to the arithmetic processing element, and the instructions of the threads are stored one by one in the connection order of the arithmetic processing elements. 2. An information processing apparatus according to claim 1, wherein said information processing apparatus has the same number of storage means as said arithmetic means, and all the arithmetic means dynamically select their own storage means and use them simultaneously. An information processing apparatus, comprising: 3. An information processing apparatus according to claim 2, further comprising: an instruction selection value storage unit for storing a plurality of instruction selection values, wherein a new instruction selection is automatically performed on the empty instruction selection value storage unit. An information processing apparatus having thread issuance control means, wherein a thread is dynamically assigned to an arithmetic processing element by assigning a value. 4. The information processing apparatus according to claim 3, wherein the result of the last arithmetic processing element connected in series is
Connected as the input of the arithmetic means of the arithmetic processing element in the front row,
An information processing apparatus for updating an instruction selection value at the same time and transmitting the updated instruction selection value to an instruction selection value storage means of an arithmetic processing element in the front row. 5. The information processing apparatus according to claim 4, wherein the starting position of the thread in the processing element can be freely set, and the execution restart position of the processing element can be freely changed during operation. An information processing device that is a feature. 6. The information processing apparatus according to claim 5, further comprising a plurality of thread issuance control means, and selecting a thread issuance control means and a starting point of the operation processing element by using an output value of the operation means. An information processing apparatus characterized by the above-mentioned. 7. An information processing apparatus according to claim 4, wherein the number of storage means is equal to the number of calculation means, and the information transmission means is configured to freely connect the calculation means and storage means in a one-to-one manner and simultaneously transmit the information. An information processing apparatus having means for passing the connection of the storage means together with the operation result to an adjacent operation processing element at the same time as the end of the operation. 8. The information processing apparatus according to claim 7, wherein a plurality of storage means are uniquely selected by an output value from the arithmetic means, and all arithmetic means specify different storage means. A plurality of arithmetic processing elements are prevented from being connected to one storage means at the same time by transmitting the selected value to the adjacent arithmetic processing element together with the transfer of the result of the arithmetic means. Information processing device. 9. An information processing apparatus according to claim 6, wherein, for a non-deterministic exceptional event of an arithmetic processing element, all arithmetic results from said arithmetic processing element are stored using a storage means selection value. Automatically transferring the instruction selection value of the interrupted operation processing element to the thread issue control means, and transmitting the operation result saved at the same time as the end of the exceptional event to the information processing element; An information processing apparatus characterized by restarting the operation of (1). 10. An information processing apparatus according to claim 8, wherein an exceptional event is generated when the information processing element needs to input / output information to / from other than the storage means connected one-to-one. Information input / output from / to the low-speed storage means, transmitting the saved information and the input information to the arithmetic processing element at the same time as the termination, and restarting the operation of the arithmetic processing element. Processing equipment. 11. The information processing apparatus according to claim 10, wherein when the arithmetic processing element needs to input / output information to / from a unit other than the storage unit connected in a one-to-one manner, the information processing unit includes the arithmetic unit. An information processing apparatus having transmission information storage means for independently communicating with a storage means, and transmitting information when the storage means for communicating with the transmission information storage means is connected. 12. An information processing apparatus according to claim 11, wherein a part of the contents of a storage means external to said information processing means is temporarily stored in said storage means inside said information processing means, and said information is stored in said storage means. An information processing apparatus for performing communication and automatically exchanging contents with an external storage means when data is not temporarily stored, and wherein a plurality of storage means simultaneously execute an operation of exchanging contents. 13. The information processing apparatus according to claim 8, wherein the storage means selection value is stored together with the instruction selection value in the thread issuance control means, and the stored storage means selection value is output when the instruction selection value is output. An information processing apparatus for comparing a value with a storage unit selection value of an arithmetic processing element and outputting an instruction selection value to the arithmetic processing element only when the values match. 14. An information processing apparatus according to claim 11, further comprising special operation means independent of the operation processing elements connected in series, and connecting all the operation processing elements and the special operation means. An information processing device, wherein the element transmits a state to the thread issue control means together with a request for operation of the special operation means, and restarts the operation of the operation processing means simultaneously with the end of the operation of the special operation means. 15. An information processing apparatus according to claim 4, wherein one special operation means is connected to two or more operation processing elements among the operation processing elements connected in series. An information processing apparatus characterized in that arithmetic means can be used from all connected arithmetic processing elements. 16. An information processing apparatus according to claim 2, further comprising an information processing apparatus communication means for communicating with a storage means connected to another information processing apparatus. . 17. A system using a plurality of information processing apparatuses according to claim 2 and claim 8, wherein each of the information processing apparatuses has individual storage means, and a plurality of information is stored by one storage means selection value. 17. An information processing apparatus, wherein all storage means connected to the processing apparatus are uniquely selected and transferred by the information processing apparatus communication means according to claim 16.