JPH11111999A - Manufacture of thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a silicon film which coats a gate electrode from being interrupted by a step by gently working, under good control, an inclination angle of a cross sectional sidewall of a gate electrode in a bottom gate type thin-film transistor. SOLUTION: A high-melting point metal film 22 and, an oxide film 23 are formed on a transparent substrate 21, which is coated with a resist mask. Both are subjected to isotropic etching to form a trapezoidal gate electrode 25 whose cross section expands on the side of the transparent substrate 21. A silicon nitride film 26 and a silicon oxide film 27, which coates the gate electrode 25 are laminated. On a gate insulating film comprising the silicon nitride film 26 and the silicon oxide film 27, a polycrystalline silicon film 28 which is to be an active region is laminated. An angle formed at crossing of a sidewall of the gate electrode 25 and the surface of the substrate 21 is set to 20 degrees or less.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a bottom gate type thin film transistor suitable for a switching element for pixel display of an active matrix type display panel.

[0002]

2. Description of the Related Art FIG. 4 is a sectional view showing the structure of a bottom gate type thin film transistor. A gate electrode 2 made of a refractory metal such as tungsten or chromium is arranged on the surface of an insulating transparent substrate 1. The gate electrode 2 has a tapered shape in which both ends become wider on the transparent substrate 1 side. On the transparent substrate 1 on which the gate electrode 2 is arranged, a silicon oxide film 4 is laminated via a silicon nitride film 3. The silicon nitride film 3 prevents impurities contained in the transparent substrate 1 from entering an active region described later, and the silicon oxide film 4 functions as a gate insulating film together with the silicon nitride film 3. On the silicon oxide film 4, a polycrystalline silicon film 5 is stacked across the gate electrode 2. This polycrystalline silicon film 5 becomes an active region of the thin film transistor.

A stopper 6 made of an insulating material such as silicon oxide is arranged on the polycrystalline silicon film 5. The polycrystalline silicon film 5 covered by the stopper 6 becomes the channel region 5c, and the other polycrystalline silicon films 5 become the source region 5s and the drain region 5d. On the polycrystalline silicon film 5 on which the stopper 6 is formed, a silicon oxide film 7 and a silicon nitride film 8 are stacked. This silicon oxide film 7
The silicon nitride film 8 serves as an interlayer insulating film for protecting the polycrystalline silicon film 5 including the source region 5s and the drain region 5d.

[0004] Contact holes 9 are formed at predetermined locations of the silicon oxide film 7 and the silicon nitride film 8 on the source region 5s and the drain region 5d. In the contact hole 9 part, the source region 5s and the drain region 5d
Source electrode 10s and drain electrode 10d connected to
Is arranged. Source electrode 10s and drain electrode 10
An acrylic resin layer 11 transparent to visible light is laminated on the silicon nitride film 8 on which d is disposed. The acrylic resin layer 11 flattens the surface by filling irregularities generated by the gate electrode 2 and the stopper 6.

Acrylic resin layer 11 on source electrode 10s
, A contact hole 12 is formed. Then, the aluminum wiring 10 is formed through the contact hole 12.
A transparent electrode 13 made of ITO (indium tin oxide) or the like is connected to the acrylic resin layer 11 so as to be spread. The transparent electrode 13 forms a display electrode of the liquid crystal display panel.

A plurality of the above thin film transistors are arranged in a matrix on a transparent substrate 1 together with a display electrode.
In response to a scanning control signal applied to the drain electrode 1
The video information supplied to Od is applied to the display electrodes. Incidentally, the polycrystalline silicon film 5 is formed with a sufficient crystal grain size so as to function as an active region of the thin film transistor. As a method for forming a large crystal grain size of the polycrystalline silicon film 5, a laser annealing method using an excimer laser is known. This laser annealing method is to crystallize silicon by laminating amorphous silicon on a silicon oxide film 4 serving as a gate insulating film and irradiating the silicon with an excimer laser to once melt the silicon. It is. If such a laser annealing method is used, it is not necessary to increase the temperature of the transparent substrate 1, so that a glass substrate having a low melting point can be adopted as the transparent substrate 1.

[0007]

The silicon film 5 serving as an active layer is laminated so as to straddle a step formed by the gate electrode 2. At this time, although the gate electrode 2 has a trapezoidal cross section such that the side wall intersects the surface of the transparent substrate 1 in a tapered shape, the step of the polycrystalline silicon film 5 is liable to occur at the step. ing. That is, chromium (Cr) used as the gate electrode 2 has a high heat dissipation property, and the glass substrate 1 has a poor heat dissipation property. Therefore, when the polycrystalline silicon film is heated and melted by an excimer laser and then recrystallized, Polycrystalline silicon film 5 on gate electrode 2
The recrystallization speed is different between the polysilicon film 5 on the substrate 1 and the difference in the recrystallization speed. This difference causes a difference in the grain size of the polysilicon and the polysilicon film 5 near the side wall of the gate electrode 2. Is considered to break the step. For this reason, the conduction between the channel region 5c and the source / drain regions 5s and 5d is interrupted, thereby causing a significant reduction in the manufacturing yield of the device.

It has been found that this phenomenon can be avoided to some extent by making the inclination angle of the cross-sectional side wall of the gate electrode 2 gentle. However, there is a drawback that it is difficult to process a refractory metal such as chromium into a trapezoid with good reproducibility. Accordingly, an object of the present invention is to provide a manufacturing method for preventing a step in a polycrystalline silicon film from occurring.

[0009]

According to the present invention, there is provided a thin film transistor, comprising: a substrate; a gate electrode disposed on a surface of the substrate; a gate insulating film laminated on the substrate so as to cover the gate electrode; A semiconductor film stacked on the gate insulating film over an electrode, and an interlayer insulating film stacked on the semiconductor film, wherein the gate electrode forms an oxide film on a surface of the high melting point metal film. And etching the oxide film and the refractory metal film simultaneously.

According to the present invention, since the etching rate of the oxide film is high, the etching proceeds in the thickness direction of the refractory metal film, and at the same time, the etching in the horizontal direction is accelerated. It can be formed well.

[0011]

1 to 3 are sectional views for explaining steps of a method for manufacturing a thin film transistor according to the present invention. In these figures, the same parts as those in FIG. 1 are shown. (A) First Step On a transparent insulating substrate 21 made of non-alkali glass or the like, a high melting point metal such as chromium or molybdenum is laminated by sputtering to a thickness of 700 to 1300 ° to form a high melting point metal film 22. I do. An oxide (CrO2 for chromium, MoO2 for molybdenum) corresponding to the deposited metal is deposited on the refractory metal film 22 by a sputter method or a natural oxidation method that is left in an N2 atmosphere for 5 hours or more. Then, an oxide film 23 having a thickness of 10 to 200 ° is formed (see FIG. 1A). (B) Second Step A resist mask 24 is formed on the oxide film 23 formed on the refractory metal film 22, and the refractory metal film 24 and the oxide film 23 are patterned into a predetermined shape by the resist mask 24. A gate electrode 25 is formed. In this patterning process, etching proceeds in an isotropic mode by using a nitric acid-based wet etchant.
r) etching rate for chromium oxide (CrO
2) The etching rate is about 20% faster, so that the etching proceeds in the thickness direction of the refractory metal film 22 and at the same time, the oxide film 23 is etched in the lateral direction, and the exposed surface of the refractory metal film 22 is exposed. Exposure to etchants. As a result, the cross section of the gate electrode 22 is formed in a tapered shape expanding on the transparent substrate 21 side. be able to. (See FIG. 1B).

Here, the upper limit of the thickness of the gate electrode 25 is as follows.
It is preferable that the difference in crystal grain size be as small as possible, and the lower limit of the film thickness be as large as possible so that the resistance value (wiring resistance) of the gate electrode 22 is reduced. The thickness of the oxide film 23 is the same as that of the gate electrode 25.
It is preferable that the thickness is as thin as 10 to 200 ° because the step due to the above is not increased. (C) Third Step Silicon nitride is laminated on the transparent substrate 21 to a thickness of 500 to 1500 ° by a plasma CVD method. As a result, a silicon nitride film 26 that prevents precipitation of impurity ions from the transparent substrate 21 is formed. Subsequently, silicon oxide is deposited on the silicon nitride film 26 to a thickness of 1000 to 2000 ° by a plasma CVD method. This allows
A silicon oxide film 27 serving as a gate insulating film is formed together with the silicon nitride film 26. Then, the silicon oxide film 27
On top, 400-80 silicon is deposited by plasma CVD.
An amorphous silicon film 28 is formed by laminating to a thickness of 0 °. The above silicon nitride film 26, silicon oxide film 27, and amorphous silicon film 28 can be continuously formed by the same device. Further, the silicon film 28 'is irradiated with an excimer laser and heated until the amorphous silicon is melted. Thus, silicon is crystallized to form a polycrystalline silicon film 28 (see FIG. 1C). (D) Fourth Step Silicon oxide is deposited on the polycrystalline silicon film 28 by 1000-2.
A silicon oxide film 29 is formed by laminating to a thickness of 2,000. Then, this silicon oxide film 29 is formed on the gate electrode 25.
The stopper 30 is formed so as to overlap the gate electrode 25. In forming the stopper 30, a mask layer can be eliminated by forming a resist layer over the silicon oxide film 30 and exposing the resist layer from the transparent substrate 21 side using the gate electrode 25 as a mask (FIG. 1 (D)). (E) Fifth Step P-type or N-type ions corresponding to the type of transistor to be formed are implanted into the polycrystalline silicon film 28 on which the stopper 30 has been formed. That is, when a P-channel transistor is formed, P-type ions such as boron are implanted, and when an N-channel transistor is formed, N-type ions such as phosphorus are implanted. By this implantation, a region exhibiting P-type or N-type conductivity is formed in the polycrystalline silicon film 28 except for the region covered by the stopper 30. These regions become the source region 28s and the drain region 28d on both sides of the stopper 30, and the stopper 3
The region covered with 0 becomes the channel region 28c (FIG. 2).
(A)). (F) Sixth Step The polycrystalline silicon film 28 on which the source region 28s and the drain region 28d are formed is irradiated with an excimer laser, and heated so that silicon does not melt. Thereby, impurity ions in the source region 28s and the drain region 28d are activated. Then, the stopper 30 (the gate electrode 2)
The polycrystalline silicon film 28 is patterned into an island shape with a predetermined width left on both sides of 5) to separate the transistors independently (see FIG. 2B). (G) Seventh Step Silicon oxide is deposited on the polycrystalline silicon film 28 by a plasma CVD method to a thickness of 1000 to 2000 °, and silicon nitride is continuously deposited to a thickness of 2000 to 3000 °. Thus, an interlayer insulating film composed of two layers, the silicon oxide film 31 and the silicon nitride film 32, is formed. After the silicon oxide film 31 and the silicon nitride film 32 are formed, the silicon oxide film 31 is heated at about 350 to 450 ° C. in a nitrogen atmosphere to introduce hydrogen ions contained in the silicon nitride film 32 into the polycrystalline silicon film 28. A contact hole 33 penetrating through the silicon oxide film 31 and the silicon nitride film 32 is formed corresponding to the source region 28s and the drain region 258 (see FIG. 2C). (H) Eighth Step A drain electrode 34 made of a metal such as aluminum is formed in the contact hole 33. The drain electrode 34 is formed, for example, by patterning aluminum sputtered on the silicon nitride film 32 in which the contact hole 33 is formed (FIG. 3).
(A)). (I) Ninth Step Subsequently, an acrylic resin solution is applied on the silicon nitride film 33 on which the drain electrode 34 has been formed, and baked to form an acrylic resin layer 35. The acrylic resin layer 35 flattens the surface by filling irregularities due to the stopper 30 and the drain electrode 34. Further, a contact hole 36 penetrating the acrylic resin layer 35 is formed on the source region 28s,
A transparent electrode 37 made of ITO or the like connected to the source region 28s is formed in the contact hole 36.
The transparent electrode 37 is formed, for example, by patterning ITO sputtered on the acrylic resin layer 35 in which the contact holes 36 are formed (see FIG. 3B).

Through the above first to ninth steps, a bottom gate type thin film transistor is formed. In this thin film transistor, the step of the polycrystalline silicon film 28 on the side wall of the gate electrode 25 could be greatly reduced by setting the angle of the cross section side wall of the gate electrode 25 to 20 degrees or less. According to the measurement, the defective rate due to the step break of the polycrystalline silicon film was reduced from about 30% to about 1% as compared with the conventional case where the angle was set to 45 degrees or more.

[0014]

According to the present invention, the polycrystalline silicon film 28
Can be controlled with good reproducibility to an inclination angle of the cross-sectional side wall of not more than 20 degrees, whereby the step disconnection failure rate can be greatly reduced. Therefore, while improving the manufacturing yield,
Improved reliability can be expected.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a method for manufacturing a thin film transistor of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a thin film transistor of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a thin film transistor of the present invention.

FIG. 4 is a cross-sectional view showing a structure of a conventional thin film transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 21 Transparent substrate 22 High melting point metal film 23 Oxide film 25 Gate electrode 26, 32 Silicon nitride film 27, 31 Silicon oxide film 28 Polycrystalline silicon film 28c Channel region 28s Source region 28d Drain region 30 Stopper 33, 36 Contact hole 34 Drain electrode 35 Acrylic resin layer 36 Transparent electrode

Claims (3)

[Claims] A step of forming a high-melting-point metal film on an insulating substrate, and forming an oxide of the high-melting-point metal on the surface of the high-melting-point metal, the etching rate of which is higher than that of the high-melting-point metal; Forming a resist mask thereon, wet-etching the refractory metal and the oxide to form a gate electrode having a cross-sectional side wall inclined, a gate insulating film laminated over the gate electrode, and A method for manufacturing a thin film transistor, comprising: a step of forming a semiconductor film laminated on the gate insulating film over a gate electrode; and a step of laser annealing the semiconductor film to polycrystallize the semiconductor film. 2. The method according to claim 1, wherein the refractory metal is chromium (Cr). 3. The method according to claim 1, wherein the thickness of the oxide is 10 to 200 °.