JPH11146659A - Positive/negative pulse switching power unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a positive/negative pulse switching power unit, which can make efficient stable pulse width control without being affected by the condition of a load even when the width of its output pulse is continuously changed from a narrow pulse width to a wide pulse width with a simple circuit configuration and a power source (single-sided power source) for its semiconductor switching elements. SOLUTION: Four semiconductor switching elements SW1, SW2, SW3, and SW4 are successively and repeatedly made to make switching operations in a fixed combined turning-on/off mode, by connecting the switching elements SW1, SW2, SW3 and SW4 in an H bridge and, at the same time, impressing a DC voltage upon an H-bridge switching circuit 1 in which the switching elements SW1, SW2, SW3, and SW4 are respectively connected in parallel with diodes D1, D2, D3, and D4, and supplying gate pulses to the gates of the switching elements SW1, SW2, SW3, and SW4 from a gate control circuit 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a positive / negative pulse type switching power supply for alternately applying a positive / negative pulse voltage to a load, and relates to a DC switching power supply, a high frequency plasma power supply, a sputtering power supply, a lamp power supply, a laser power supply, a high voltage pulse. It can be widely used as a power source, a power source for corona treatment, a power source for ion plating, a power source for a welding machine, a battery charger, and the like.

[0002]

2. Description of the Related Art Japanese Unexamined Patent Publication No. 9-172787 discloses a positive / negative pulse type high voltage power supply having improved rising / falling characteristics of positive / negative pulse high voltage by adopting the following configuration. .

That is, a first switching element SW1, a second switching element SW2, and a third switching element SW3 are connected in series between the positive voltage generating section + E and the ground, and the first switching element SW1 The connection point with the second switching element SW2 is connected to the load R, and the fourth switching element SW4 is connected between the negative voltage generator -E and the load R. After the first switching element is turned on and a positive voltage is applied to the load, the second switching element is turned on and a circuit is connected to the ground via a diode D3 connected in parallel with the third switching element.
Discharge the positive charge of the load. Next, after the fourth switching element is turned on to apply a negative voltage to the load, the third switching element is turned on and the circuit reaches the load via the diode D2 connected in parallel with the second switching element. As a result, the negative charge of the load is discharged.

According to this conventional technique, the positive and negative pulse high voltage values can be varied positively and negatively, so that there is an advantage that the ion balance can be adjusted as a power supply for a static eliminator. There is a problem that requires a power supply (positive voltage generator + E and negative voltage generator -E).

Further, Japanese Patent Publication No. 7-57100 discloses that
The four semiconductor elements have an H-bridge type configuration, and the switching of the semiconductor elements requires 50% / 50% for each of the positive and negative sides.
Is alternately switched. And this circuit is P
Adopting DM (pulse density modulation) method, the output pulse has a positive / negative 50% / 50% waveform, and pause between the pulses as shown in FIG.
A high-voltage pulse resonating with the output side is obtained.

However, according to this conventional technique, there are problems that the circuit configuration is complicated, modulation control is difficult, and the modulation width cannot be made large.

Further, conventionally, as shown in FIG. 7, four first, second, third, and fourth semiconductor switching elements SW are provided.
1, SW2, SW3, and SW4 are H-bridge connected, and diodes D1, D
When an H-bridge switching circuit in which 2, D3 and D4 are respectively connected in parallel is used, switching operation is generally sequentially and repeatedly performed in four ON / OFF combinations shown in Table 2 below.

[0008]

[Table 2]

In FIG. 7, four semiconductor switching elements SW1, SW2, SW3 and SW4 are all turned off.
(Both ends of the load are OFF). Next, when a signal is simultaneously input to the gates of the semiconductor switching elements SW1 and SW3, a current flows in the direction of I1, and the load is charged. Thereafter, the gate signals of SW1 and SW3 are turned off, but the charge charged on the load side remains charged. This time, the semiconductor switching elements SW2, SW
When signals are simultaneously input to the gates of the gates 4, a current flows in the direction of I2, and the load is discharged. After this, SW
2. Although the gate signal of SW4 is turned off, the electric charge charged on the load side remains charged.

Therefore, as shown in the timing chart of FIG. 8, even if the gate signal to SW1, SW2, SW3, SW4 ends, the output pulse does not immediately fall and is affected by the stray capacitance of the load and leakage inductance. In the case of light load and C load, the waveform extends to the rising of the next pulse as shown in FIG. 7A, and in the case of L load, the waveform before and after each pulse is distorted as shown in FIG. As a result, accurate pulse width control cannot be performed.

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to continuously change the width of an output pulse from a narrow pulse width to a wide pulse width without being affected by load conditions.
Efficient and stable pulse width control (pulse width modulati
on: pulse width modulation), which can be realized with a simple circuit configuration, and a positive / negative pulse type switching power supply device in which a single power supply (single power supply) is required for the semiconductor switching element.

[0012]

SUMMARY OF THE INVENTION The present invention provides first, second, and third aspects.
Third and fourth four semiconductor switching elements SW1, S
While connecting W2, SW3 and SW4 to H bridge,
Diodes D1, D2, D
3, an H-bridge switching circuit in which D4 is connected in parallel, a DC power supply for applying a DC voltage to the H-bridge switching circuit, and a gate pulse supplied to the gates of the four semiconductor switching elements SW1, SW2, SW3, SW4. And a gate control circuit for switching operation. This gate control circuit includes four semiconductor switching elements SW1, SW2, SW3, and SW4 as shown in Table 3 below.
The switching operation is sequentially and repeatedly performed in the five ON / OFF combination modes shown in FIG.

[0013]

[Table 3]

In order to ensure the stability and safety of the operation of the semiconductor switching element, the time width when turning off the second semiconductor switching element SW2 is the time when turning on the first semiconductor switching element SW1. A third semiconductor switching element SW3
Is preferably longer before and after than when turning on the fourth semiconductor switching element SW4.

If the width of the gate pulse supplied to the semiconductor switching element is varied, the width of the output pulse can be adjusted efficiently without waveform distortion.

Further, if the frequency of the gate pulse supplied to the semiconductor switching element is varied, the frequency of the output pulse can be adjusted efficiently without waveform distortion.

[0017]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

As shown in FIG. 1, the positive / negative pulse type switching power supply according to the present invention comprises first, second, third, and fourth switching power supplies.
Semiconductor switching elements SW1, SW2, SW
3, SW4 is connected to an H-bridge (a semiconductor module including two FETs is an H-bridge), and diodes D1, D2, D3,
An H-bridge switching circuit (inverter circuit) 1 in which D4s are connected in parallel is used. Further, a single DC power supply 2 is used as a power supply for the H-bridge switching circuit 1, and a load 3 is connected to a middle point between the first and second semiconductor switching elements SW1 and SW2 and to the third and fourth semiconductor switching elements. Connected between SW3 and SW4 midpoint. The H-bridge switching circuit 1 is operated by a gate control circuit 4 as shown in FIG.
By performing the switching operation sequentially and repeatedly in the combination mode of five ON / OFF, the load 3
And positive and negative pulses are applied alternately. The applied voltage corresponds to the voltage from the DC power supply 2.

FIG. 2 shows an equivalent circuit of the H-bridge switching circuit 1. FIG. 3 shows a timing chart of gate signals supplied from the gate control circuit 4 to the gates of the semiconductor switching elements SW1, SW2, SW3, and SW4, and output signals output to the load 3. As shown in this figure, the second semiconductor switching element SW2 is
The time width when turning on the FF is longer before and after than the time width when turning on the first semiconductor switching element SW1, and turning off the third semiconductor switching element SW3.
Is longer before and after than the time width when the fourth semiconductor switching element SW4 is turned on.

In FIG. 2, when SW1 is turned on after SW1 is turned off, a current flows in the direction of I1, and the load 3 is charged positively. Next, when SW2 is turned on after SW1 is turned off, a current flows in the direction of I2 through SW2 and D3, so that the leakage inductance and stray capacitance of the load 3 are forcibly reset by SW2 and D3. You.

Thereafter, after SW3 is turned off,
When 4 is turned on, a current flows in the direction of I3, and the load 3 is negatively charged. Next, after SW3 is turned off, S
When W4 is turned on, current flows in the direction of I4, and the load 3
Is forcibly reset by SW2 and D3.

The operation will be described below with reference to Table 3. Then, SW2 and SW3 receive a gate signal and are turned ON, and both ends of the load 3 are short-circuited.

Then, the gate signal of SW2 is turned on,
The gate signal is input to SW1 with a slight delay and this is turned on.
Then, since SW3 remains OFF, current flows from SW1 through load 3 in the direction of I1, and the load is charged positively.

Then, after the gate signal input to SW1 is completed and turned off, the gate signal is input again to SW2 and turned on again. Therefore, the charge charged in the load 3 is equal to SW2 and D3. Discharge through. As a result, it returns to the same state as.

Then, when SW3 is turned off and a gate signal is input to SW4 with a slight delay and turned on, SW2 remains ON, so that load 3
, A current flows in the direction of I3 to charge the load 3 negatively.

Then, after the gate signal input to SW4 is completed and turned off, the gate signal is input again to SW3 and turned on again. Therefore, the charge charged to the load is equal to SW3 and D2. Pass through and discharge. As a result, it returns to the same state as.

Thus, the combination of SW1 and SW2, SW3
So that the pair of and SW4 are not turned on at the same time,
By giving a dead time and switching in order, an output signal having a waveform proportional to the input signal (gate signal) can be obtained. In this case, the stray capacitance and the leakage inductance on the load side are reset by the switching operation as described above, so that an output waveform without distortion is obtained.

Next, four semiconductor switching elements SW
The gate control circuit 4 shown in FIG. 4 for causing the switching operations of SW1, SW2, SW3 and SW4 as described above will be described.

In this example, a general AC power source is used as an original power source, and is rectified into a direct current by a DC rectifier circuit 6 via a starter circuit 5.
1 is supplied as a single DC power supply 2, and a reference voltage (for example, ± 15 V) rectified by a reference voltage circuit 7 is supplied to a gate control circuit 4.

The gate control circuit 4 controls the pulse oscillation circuit 8 by using four semiconductor switching elements SW1, SW2, SW
3, a common gate signal generation source for SW4. The pulse from the pulse oscillating circuit 8 is supplied to the first semiconductor switching element SW1 by an AND operation.
The gate signal is generated by the circuit 9 and the insulated (ISO) drive circuit 13, and the second semiconductor switching element SW2
For the third semiconductor switching element SW3, a gate signal is output to the NOR circuit 11 and the insulated drive circuit 15 for the third semiconductor switching element SW3. For the four semiconductor switching elements SW4, the AND circuit 12 and the insulated drive circuit 16 supply the respective gates as gate signals.

A pulse from the pulse oscillating circuit 8 and a pulse whose rising edge is delayed by the delay circuit 17 are input to the AND circuit 9 and the NOR circuit 10.
The pulse from the pulse oscillation circuit 8 and the pulse whose rising edge is delayed by the delay circuit 18 are input to the 1 and AND circuit 12.

The pulse width of the pulse oscillation circuit 8 can be arbitrarily varied (for example, 0 to 50%) by the pulse width setting device 17,
The frequency can be arbitrarily adjusted by the frequency setting device 20.

FIG. 5 shows the operation timing of the gate control circuit 4. As shown in this figure, the width of the pulse output from the NOR circuit 10 is longer before and after than the width of the pulse output from the AND circuit 9, and the width of the pulse output from the NOR circuit 11 is The pulse width is longer before and after than the width of the pulse output from.

Such pulses from the AND circuit 9, the NOR circuit 10, the NOR circuit 11, and the AND circuit 12 are passed through the insulated drive circuits 13, 14, 15, 16 to the respective semiconductor switching elements SW1, SW2,
By supplying the signals to the gates of SW3 and SW4, these semiconductor switching elements perform the switching operation as described above, and alternating positive and negative pulses are obtained. This positive / negative pulse is output from the transformer 21. The output pulse according to the present invention is shown at the bottom of the timing chart of FIG.

[0035]

According to the present invention, the following effects can be obtained. (1) Since the four semiconductor switching elements have an H-bridge configuration and use an H-bridge type switching circuit (inverter circuit) in which diodes are connected in parallel to each semiconductor switching element, positive and negative voltages corresponding to the supplied power supply voltage are used. A pulse output can be obtained.

(2) The switching circuit (inverter circuit) is of an H-bridge type, which is simple and requires only a single power supply, thereby reducing the cost.

(3) Since a resonance circuit is not used, it is not affected by load conditions. Further, since the leakage flux and stray capacitance of the load can be forcibly reset, waveform distortion due to these effects can be eliminated.

(4) Since an output waveform accurately corresponding to the gate signal is obtained, efficient and stable pulse width control (pulse width modulation) and frequency control become possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration and a current flow of an H-bridge switching circuit used in the present invention.

FIG. 2 is an equivalent circuit diagram of the above.

FIG. 3 is a timing chart showing the operation of the above.

FIG. 4 is a block diagram of an example of a positive / negative pulse switching power supply of the present invention including the H-bridge switching circuit of FIG. 1;

FIG. 5 is a timing chart showing the operation of the gate control circuit in FIG.

FIG. 6 is a timing chart showing the operation of the conventional example.

FIG. 7 is a diagram illustrating a configuration and a current flow of a conventional H-bridge switching circuit.

FIG. 8 is a timing chart showing the operation of the above.

[Explanation of symbols]

SW1, SW2, SW3, SW4 Semiconductor switching elements D1, D2, D3, D4 Diode 1 H-bridge switching circuit 2 DC power supply 3 Load 4 Gate control circuit 5 Start-up circuit 6 DC rectification circuit 7 Reference voltage circuit 8 Pulse oscillation circuit 9, 12 AND circuit 10, 11 NOR circuit 13, 14, 15, 16 drive circuit 17, 18 delay circuit 19 pulse width setting device 20 frequency setting device 21 transformer

Claims (4)

[Claims] 1. An H-bridge connection of first, second, third, and fourth semiconductor switching elements SW1, SW2, SW3, and SW4, and diodes D1, D2, D3, and D4 connected to each of the semiconductor switching elements. , A DC power supply for applying a DC voltage to the H-bridge switching circuit, and the four semiconductor switching elements SW1, SW2, SW
3, a gate pulse is supplied to the gate of SW4, and these four semiconductor switching elements are shown in Table 1 below.
A positive / negative pulse type switching power supply device comprising: a gate control circuit for sequentially and repeatedly performing a switching operation in five ON / OFF combination modes of: [Table 1] 2. The method according to claim 1, wherein the second semiconductor switching element SW2 is
The time width when turning on the FF is longer before and after than the time width when turning on the first semiconductor switching element SW1, and turning off the third semiconductor switching element SW3.
The gate control circuit sets the four semiconductor switching elements SW1, SW2, SW3, and SW4 so that the time width when the fourth semiconductor switching element SW4 is turned on is longer before and after the time when the fourth semiconductor switching element SW4 is turned on. 2. A positive / negative pulse type switching power supply device according to claim 1, wherein a gate pulse is supplied to the gate of the switching power supply. 3. The positive / negative pulse type switching power supply according to claim 1, wherein the gate control circuit has a pulse width adjusting section capable of adjusting the width of the gate pulse. 4. The positive / negative pulse type switching power supply according to claim 1, wherein the gate control circuit has a frequency adjusting section capable of adjusting a frequency of the gate pulse.