JPH11149416A - Data assurance device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the reliability of data assurance by connecting a memory access control means between a control means and plural storage means, by which data transmitted from the control means is simultaneously written in the respective storage means, based on the indication of the control means. SOLUTION: A memory access control circuit 2 is connected between a controller 1 and the memories 3a and 3b. When the operation setting signal of logic 11 is transmitted from the controller 1, the memory access control circuit 2 permits CS signals (a) and (b) to be active, the memories 3a and 3b permits only a WR signal to be valid and an RD signal to be invalid and the both of the memories 3a and 3b become in a writing possible state. When data are transmitted from the controller 1 at this time, data are simultaneously written in the respective addresses of the memories 3a and 3b, which are designated by the controller 1. Besides, when the operation setting signal of logic 01 is transmitted from the controller 1, the CS signal (a) is made to be active and the CS signal (b) is made to be nonactive.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data assurance apparatus, and more particularly to a data assurance apparatus that multiplexes and stores data to guarantee data.

[0002]

2. Description of the Related Art In recent years, it has been pointed out that data stored in a memory may be destroyed by the influence of external noise. Although the probability of destruction of data by extraneous noise is extremely low, when handling important data, a data guarantee that duplicates and saves data in case of emergency is adopted. FIG. 3 is a block diagram showing a configuration of a conventional data assurance device. This data assurance device includes a memory 1 for storing data.
3 and a control device 11 for writing data to the memory 13 in duplicate. The control device 11 and the memory 13 are connected to an address bus 14, a data bus 15
And the control bus 16.

When writing data to the memory 13, the control device 11 divides the memory 13 into a main area 13a and a sub area 1a.
3b and the same data is written to both the main area 13a and the sub area 13b. Alternatively, the control device 11
Data is written to the main area 13a, and then the main area 1a is written.
The data written in 3a is copied to the sub area 13b. Conventionally, data is guaranteed by generating the same data in two areas of one memory 13 in this manner.

[0004]

However, if the same data is written to the memory 13 twice or the written data is copied in order to duplicate the data, a program for guaranteeing the data becomes complicated. Also, if data is duplicated in tens of kilobytes using the conventional method,
The load of the software processing of the control device 11 increases. When a program for performing data assurance is complicated and the load of software processing is increased, there is a problem that the possibility that data writing to the memory 13 is not performed accurately increases.

When data is duplicated and stored in one memory 13, there is a problem that the stored data is lost when a device constituting the memory 13 fails.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to improve the reliability of data assurance.

[0007]

In order to achieve such an object, the present invention provides a plurality of storage means for storing data, a control means for issuing an instruction to write data to each of these storage means, A memory access control unit connected between the control unit and each of the storage units and writing data sent from the control unit based on an instruction of the control unit into each of the storage units simultaneously;

In order to store data in a plurality of storage means,
Even if one of the storage means fails, data loss can be avoided. In addition, since the data is written into each storage means by the memory access control means only by giving an instruction to the memory access control means, it is possible to simplify a program for performing data assurance, The software processing load of the means can be reduced.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a data guarantee device according to the present invention. The data assurance device includes memories 3a and 3b as storage means for storing data, a control device 1 for issuing an instruction to write data to these memories 3a and 3b, and a control device 1 based on the instruction of the control device 1. The memory access control circuit 2 writes the transmitted data into the memories 3a and 3b at the same time.

An address bus 4 is wired between the control device 1, the memory access control circuit 2 and each of the memories 3a and 3b, and a data bus 5 is wired between the control device 1 and each of the memories 3a and 3b. . A control bus 6a is wired between the control device 1 and the memory access control circuit 2, and the memory access control circuit 2 and each of the memories 3a, 3
The control bus 6b is wired between the control bus 6b.

The control device 1 transmits a WR (write) signal, an RD (read) signal,
A bit operation setting signal is sent to the memory access control circuit 2. Further, the memory access control circuit 2 sends the input WR signal and RD signal to the memories 3a and 3b via the control bus 6b, and outputs a CS (chip select) signal a and a CS signal b based on the operation setting signal. These are sent to the memories 3a and 3b, respectively.

Next, the operation of the data guarantee apparatus shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a diagram showing the relationship between the logic of the operation setting signal and the operation of the data guarantee device shown in FIG. When the operation setting signal of logic “11” is transmitted from the control device 1, the memory access control circuit 2 activates both the CS signal a and the CS signal b. Thereby, the memories 3a and 3b make only the WR signal valid and make the RD signal invalid.

Therefore, when the control device 1 outputs the operation setting signal of logic "11" and the WR signal, both the memories 3a and 3b become writable. At this time, when the data is transmitted from the control device 1, the data is simultaneously written to each address of the memories 3a and 3b designated by the control device 1. When the logic of the operation setting signal is "11", the RD signal is invalidated, so that data is not simultaneously read from the memories 3a and 3b.

When an operation setting signal of logic "01" is transmitted from the control device 1, the memory access control circuit 2 activates the CS signal a and deactivates the CS signal b. Conversely, when the operation setting signal of logic “10” is sent from the control device 1, the memory access control circuit 2 makes the CS signal a non-active and makes the CS signal b active. The logic of the operation setting signal is “01” and “1”.
In any case of "0", the memories 3a and 3b validate both the WR signal and the RD signal.

Therefore, when the control device 1 outputs the operation setting signal of logic "01" or "10" and the WR signal, one of the memories 3a and 3b becomes in a writable state. At this time, when data is sent from the control device 1, the data is written to the address of the memory 3a or 3b designated by the control device 1. In addition, the control device 1 outputs an operation setting signal of logic “01” or “10” and R
By outputting the D signal, one of the memories 3a and 3b becomes readable. At this time, when an address of the memory 3a or 3b is designated by the control device 1, the data stored at that address is read.

As described above, in the data assurance device shown in FIG. 1, the control device 1 controls the logic of the operation setting signal so that the simultaneous writing to the memories 3a and 3b, the individual writing to the memory 3a or 3b, Individual reading from the memory 3a or 3b becomes possible. Although the data assurance device having two memories 3a and 3b has been described here, it goes without saying that the data assurance device according to the present invention functions effectively even when there are three or more memories.

[0017]

As described above, according to the present invention,
Since the data is stored in the plurality of storage units, even if one of the storage units fails, the data is not lost, so that the reliability of the data guarantee can be improved. Further, in the present invention, since the data is written into each storage means by the memory access control means only by giving an instruction to the memory access control means, it is possible to simplify a program for performing data assurance. It is possible to reduce the load of software processing of the control means. Therefore, the possibility of data writing failure is reduced, and the reliability of data assurance can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data guarantee device according to the present invention.

2 is a diagram showing a relationship between the logic of an operation setting signal and the operation of the data guarantee device shown in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional data guarantee device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Control device, 2 ... Memory access control circuit, 3a, 3
b: memory, 4: address bus, 5: data bus, 6
a, 6b: Control bus.

Claims (1)

[Claims] A plurality of storage means for storing data; a control means for issuing an instruction to write the data in each of the storage means; a control means connected between the control means and each of the storage means, A memory access control unit for simultaneously writing the data sent from the control unit based on the instruction to each of the storage units.