JPH11149457A - Cpu degrading system for cluster connection multi-cpu system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a degrade system for multi-processor system with which reliability can be improved by completing initializing operation while disconnecting a fault section without losing normal CPU as little as possible. SOLUTION: A CPU control part 2 is provided with a freeze register for controlling the disconnection of a CPU 1 from a cluster bus 7 and a CPU status register showing the condition of connecting the CPU with the cluster bus, each CPU on the cluster bus 7 writes a flag showing cluster connection into the CPU status register corresponding to the present CPU at the time of operation start, afterwards, the initial diagnosis of the CPU is started and when the CPU is judged as a fault, it is written in the freeze register. Then, the fault CPU is logically disconnected from the cluster bus, and the CPU control part 2 disconnects the CPU from the system without responding to a request from the fault CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computing system having a multi-processor for sharing memory among a plurality of CPUs, and more particularly, to a method in which a plurality of CPUs are connected as a cluster and regarded as one node. In a cluster connection multi-processor system connected to a system bus, the present invention relates to a high-reliability small-to-medium-scale server computing system degrading method in which a fault-tolerant system at the time of system startup is regarded as important.

[0002]

2. Description of the Related Art Conventionally, a multi-processor having a plurality of CPUs
In a processor system, when a failed CPU is present at the time of starting the system, the failed CPU is separated and the system is degraded and started.

For this reason, all the CPUs are provided with a common storage device immediately after the power is turned on, write the initial diagnosis result of each CPU into each unit of the storage device, and when there is a faulty CPU, the main CPU performs a degrading process. The method is adopted.

For example, Japanese Patent Application Laid-Open No. Hei 4-329462 discloses a conventional multi-processor system in which even if some of the slave processors malfunction, the multiprocessor system can be dynamically degenerated and the operation can be continued. A multi-processor dynamic degenerate operation scheme has been proposed.

[0005] This system uses a CPU provided in a common area.
By updating the function assignment table by the main processor, when a certain sub-processor fails, the function allocation of the normal sub-processor can be changed and the degraded operation can be performed dynamically.

For example, Japanese Patent Application Laid-Open No. 4-181435 discloses a system having a multiprocessor.
When a hard error occurs in a processor, the degeneration information is created, stored, and used, whereby the processor in which the hard error has occurred can be reliably recognized, the degeneration operation with the processor disconnected from the system is performed, and the reliability is reduced. Computer systems have been proposed to improve the performance. In this system as well, degeneration information of each processor is written in a common area, and the degenerate operation is enabled by the main processor referring to the degeneration information and starting up with the failed processor separated.

[0007]

However, the conventional degrate technique has the following problems.

The first problem is that the main processor that actually performs the degeneration processing is predetermined in hardware, and if the main CPU fails, the system will not start at all. A situation can occur.

A second problem is that a common storage device that can be commonly used by all CPUs is required, which leads to an increase in the mounting area of external circuits and an increase in cost. .

Further, as a third problem, a faulty CP
A system using more CPUs without increasing the electrical load of the bus by connecting a plurality of nodes to the system bus by connecting the U and the CPU control unit as a node by bus connection (cluster connection). When a cluster-connected multi-processor system is adopted, even if at least one of the CPUs on the cluster fails, the CPU control unit is adversely affected, and each node including a normal CPU is used. There is a problem that a situation arises in which the system must be disconnected from the system bus.

As a fourth problem, in this cluster-connected multi-processor system, the CP
Various failure factors such as an individual failure of U and an individual failure of the CPU control unit increase, and it is necessary to use a degeneration technique corresponding to each failure factor.

Accordingly, the present invention has been made in order to solve the above-mentioned problems of the prior art, and its object is to solve the problem as much as possible when the CPU fails and the CPU control unit fails. The faulty part is separated from the system without losing the normal CPU, and the initialization operation is completed.
It is an object of the present invention to provide a method for degrading a failed CPU in a cluster-connected multi-processor system for improving reliability against a system failure.

[0013]

In order to achieve the above object, a CPU degration method of a cluster-connected multi-processor system according to the present invention comprises a plurality of CPUs and a node unique to the system which controls each CPU. A CPU control unit to which an ID number is assigned is connected by a cluster bus, and a memory and an I / O shared by the plurality of CPUs.
O, in a multi-processor system in which the plurality of CPU control units are coupled via a system bus, the CPU control is at least a control register for controlling disconnection of a CPU from the cluster bus. (Freeze register) and the CPU cluster
And a register (CPU status register) indicating a bus connection status. When each of the CPUs on the cluster bus starts an initial operation, a CP corresponding to its own CPU is started.
A flag indicating the cluster connection is written in the U status register. After that, the initial diagnosis of the CPU is continued. It is characterized in that the CPU is disconnected and the CPU control unit does not respond to a request from the failed CPU at all, so that the CPU is controlled to be disconnected from the system.

Further, the CPU degrate method of the cluster-connected multi-processor system of the present invention is the same as that of
A U control unit for controlling the CPU of the CPU on the cluster bus
CPU indicating a unique CPU ID number in the PU control unit
An ID register, a node (NODE) ID register indicating a unique node ID number in the system, a dedicated signal line (connect line) indicating a logical connection state between the CPU control unit and the system bus, and a plurality of other CPU control units. Register that receives the connection line from the control unit and holds the mounting status of the control unit at reset (configuration register)
And the system bus and each of the CPU controllers
A register (disconnect detection register) indicating that the PU and the CPU control unit are disconnected from the system bus after the initial diagnosis, and a control register (disconnect control) for logically disconnecting and controlling the system bus and the CPU control unit. Connect register), and after the initial diagnosis of the CPU, all the CPUs in the node are determined to be faulty.
Has written to the freeze register, and all the CPUs in the node have failed,
If there is no write operation to the PU status register within a certain period, the connect line is immediately negated and the CPU
Disconnects the control unit from the system bus.
If the PU initial diagnosis is completed normally, the CPU status register, freeze register, and CPU ID number register are read out, and the CPU
The CPU with the smallest D number becomes the node master CPU, starts initial diagnosis of each CPU control unit, and when an abnormality is recognized in the CPU control unit and it is determined that a failure has occurred, it is written to the disconnect register. After the connection line is negated and disconnected from the system bus, and the initial diagnosis of the CPU and the CPU control unit is completed, the normal node master CPU reads the configuration register and the disconnect detection register, and reads the node having the smallest ID number. -The master CPU is controlled to be determined as the system master CPU.

The CPU degrate method of the cluster-connected multi-processor system of the present invention comprises a memory storing programs for initial diagnosis of CPU, initial diagnosis of CPU control unit, and initial diagnosis of system, and resets when power is turned on. At time (a), each of the CPU control units asserts a connect line, notifies the other CPU control units of the mounting status of the CPU control unit, and receives and holds the connect line from the other CPU control unit, and (B) the plurality of CPUs read the initial diagnosis program from the memory,
(C) The CPU writes to the CPU status register in the CPU control unit to indicate the presence of the CPU. (D) The CPU performs an initial diagnosis inside the CPU itself, and when an abnormality is found in the CPU, Judge as failure, write to the freeze register, and all CPUs
When the CPU writes to the freeze register, the connection line is negated and the CPU control unit is logically disconnected from the system bus (e). The CPU reads the freeze register and the CPU ID register, completes the initial diagnosis of the CPU normally, and sets the CPU having the smallest CPU ID number to the node master CPU in the CPU controller.
(F) the node master CPU is the CPU
Execute the initial diagnosis of the control unit, and if an abnormality is found in the CPU control unit, write to the disconnect register,
The connection line is negated, and the CPU control unit and the system
(G) The node master CPU, which has completed the initial diagnosis of the CPU control unit normally, reads the configuration register, the disconnect detection register, and the node ID register, and connects to the system bus. Check the node ID of the CPU control unit which is in the state and has the smallest node ID number.
When it is equal to the D number, it becomes the system master CPU,
By performing the system initial diagnosis, the failure C
It is characterized in that the PU is dynamically disconnected from the system.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below. FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

Referring to FIG. 1, in an embodiment of the present invention, a plurality of CPUs 1 constitute a cluster bus 7;
A plurality of CPU controllers 2 for controlling between each cluster bus 7 and the system bus 6 are provided, and a memory 3 shared by a plurality of CPUs 1 and an I / O controller 5
It is configured as a multi-processor system connected by a bus 6.

In the embodiment of the present invention, as shown in FIG. 2, each of the CPUs 1 writes a status register immediately after the start of operation to indicate the presence of its own CPU.
A register 201 is provided, and when each CPU 1 starts the initial CPU diagnosis and is determined to be faulty, the CPU 1 is separated from the cluster bus 7 by writing to the freeze register 200.

A CPU ID number register 205 used for determining a node master CPU among a plurality of CPUs 1 connected to one CPU control unit 2 is provided.

When the node master CPU determines that the CPU control unit 2 has failed, the node master CPU writes the data to the disconnect register 204, thereby causing the system bus 6 to fail.
From the CPU controller 2 is logically disconnected.

Further, in determining the system master CPU, as shown in FIG. 1, a connection line 8 indicating the mounting status of the CPU control unit 2 and the logical connection status with the system bus 6 is provided. The configuration register 20 which holds the connect line 8 from the CPU control unit immediately after reset release and reflects the mounting state of the CPU control unit
2 and a disconnect register 204 that reflects the current state of the connect line 8.

Immediately after the power-on operation starts, each CPU 1
In order to indicate the existence of the own CPU, a write to the CPU status register 201 is performed, and a CPU initial diagnosis is started.

If it is determined that a failure has occurred, a write to the freeze register 200 is performed to instruct disconnection from the cluster bus 7.
Does not respond to any request from the failed CPU, thereby logically separating the failed CPU.

After the completion of the CPU initial diagnosis, each CPU 1
Reads the PU ID number register 205, CPU status register 201, and freeze register 200,
The CPU having a normally operating CPU and the smallest ID number is the node master CPU,
The initial diagnosis of the PU control unit is started.

In the initial diagnosis of the CPU control unit, the CPU
If the control unit 2 is determined to be faulty, it writes to the disconnect register 204 to disconnect the faulty CPU control unit 2 from the system bus 6, and at the same time, the connect line 8 is negated and the other CPU control unit Is notified of the disconnect.

The node master CPU 1 that has normally completed the initial diagnosis of the CPU control unit is in a connected state with the system bus 6 by referring to the disconnect register 204 and the node ID number register 206 after polling for a certain period. The node master CPU having the smallest node ID number becomes the system master.

[0027]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 3 is a diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 3, in one embodiment of the present invention, nodes 60 to 63 include CPUs 10 to 17 connected by a cluster bus 7 and CPU controllers 20 to 2.
3 are connected to the system bus 6 and the local bus 9, and the connection lines 80 to 83 are respectively connected to all the CPU control units.

A ROM (read only memory) 4 stores initial diagnostic firmware common to all processors, and is accessed from each node via a local bus 9. In the configuration shown in FIG. 3, the number of nodes and the number of CPUs connected to the intra-node cluster bus are merely examples for reference, and the present invention is not limited to these configurations. .

FIG. 4 is a diagram showing an example of the configuration of the CPU controllers 20 to 23 according to one embodiment of the present invention. Referring to FIG. 4, each of the CPU control units 20 to 23 includes a freeze register 200, a CPU status register 201, a configuration register 202, a disconnect detection register 203, a disconnect register 204,
CPU ID number register 205, node (NODE)
ID number register 206 and logic circuit (logic gate) 2
11-218, including a freeze register 200;
The CPU status register 201 corresponds to the two CPUs to be connected, and is connected to the disconnect register 20.
Immediately after the reset together with 4, it has an initial value "0".

The counter 207 starts counting after reset is released, and continues to assert the counter overflow line 208 when the count value exceeds a predetermined counter set value. After resetting the counter setting, the CPU
Is set to a time longer than the specification time until the request starts to be issued, and if there is no request from the CPU beyond this set time, it is used to determine that the CPU has failed or is not mounted.

The CPU ID number register 205
Returns the ID number according to the CPU that has issued the read request, and the node ID number register 206 is externally set in hardware.

The configuration register 202 holds the connect lines 80 to 83 with flip-flops (F / F) immediately after the reset is released.
63, and the disconnection detection register 203 reflects the current state of the connect lines 80-83.

After the reset is released, the CPU control units 20 to 23 reset the CPU status register 201, the freeze register 200, the disconnect register 204,
Counter overflow line 208, logic circuits 211-2
According to the initial state of 18, "1" is output from the connect line.

On the other hand, the connection lines 80 to 83 of the CPU control units 20 to 23 are received, and after the reset is released, each connection line is held and reflected in the configuration register 202, and the CPU control unit exists. In this case, "1" is set in a predetermined bit.

FIG. 5 is a flowchart showing the processing flow of one embodiment of the present invention.

First, after the reset is released, each of the CPUs 10 to 17 is reset.
Reads the contents of the ROM 4 storing the initial diagnostic firmware via the local bus 9 and executes the instructions written in the ROM (step 101).

If the contents of the ROM 4 can be read, the CPU writes data to the CPU status register 201 (step 102), and sets a predetermined bit to "1".
Is written.

If the ROM cannot be read due to a failure, or if the CPU is not mounted, no value is written to the CPU status register 201, so that it is recognized as not existing in the entire system from the beginning.

The normal CPU then executes the CPU initial diagnosis firmware (step 103), detects an abnormality (step 104), and if it is determined to be faulty, writes to the freeze register 200 (step 11).
2) Instruct to disconnect the failed CPU from the cluster bus 7. Thereafter, the CPU control unit does not respond to any request from the failed CPU, and is consequently logically disconnected from the cluster bus 7.

Here, if the CPU is not mounted or the CPU status register 201 is not written due to a failure, the CPU status register 201
(AND) and the outputs of the AND gates 211 and 213 which take the logical product of the counter overflow line 208 asserted after a certain period of time become "1", and the freeze register 200 To “1”
Is written, an AND gate 212,
The output of 214 becomes "1" and is input to the AND gate 217. As a result, if all the CPUs in the node cannot operate (step 115), a NOR (NOR) is performed.
The connection line is negated via 218, immediately notified to another CPU control unit, and the CPU control unit itself is disconnected from the system bus (step 116).

The CPU control unit negating the connect line stops any response via the system bus thereafter.

If a normal CPU remains in the node, the CPU status register 201, the freeze register 200, and the CPU ID number register are read (step 105), and the CPU that is operating normally has its own CPU ID. Node master CPU if equal to number
(Step 106).

Other CPUs are node / slave C
It becomes a PU and moves to a dedicated polling routine (step 114).

The CPU serving as the node mask then:
When the CPU control unit performs an initial diagnosis (step 107), detects an abnormality (step 108), and determines that a failure has occurred,
A write is made to the disconnect register 204 (step 113), the connect line is negated via a NOR (NOR) gate 218, immediately notified to another CPU control unit, and the CPU control unit itself is disconnected from the system bus. (Step 116).

The node master CPU, which has normally completed the initial diagnosis of the CPU control unit, waits for a certain period of time for all nodes to complete the initial diagnosis processing, and then waits for the configuration register 202 and the disconnect detection register 20.
3. The node ID number register 206 is read (step 109), and is connected to the system bus 6;
Check the node with the smallest number, and check its own node ID
If it is equal to the number, it becomes the system master CPU (step 110).

Otherwise, it becomes a slave CUP and moves to a dedicated polling routine (step 114).

The system master CPU completes initialization of the entire system (step 111).

As described above, according to the present embodiment, a plurality of CPUs constitute one node by the cluster bus,
Further, in a system in which a plurality of nodes are connected to a system bus, even when any CPU or any CPU control unit fails, a CP which becomes a master in each hierarchy is used.
U is dynamically changed so that the degrating process can be performed efficiently. As described above, the present invention is not limited to the above-described embodiment, but includes various embodiments according to the principle of the present invention.

[0049]

As described above, according to the present invention,
A plurality of CPUs and a CPU control unit are connected as a cluster and regarded as one node, and a plurality of nodes are connected to a system bus, thereby constructing a system using more CPUs without increasing the electrical load on the bus. Is possible,
When a cluster-connected multi-processor system is adopted, the master CPU in each hierarchy is dynamically changed in response to an individual failure of the CPU, an individual failure of the CPU control unit, etc. Alternatively, it is possible to solve the problem that the whole system cannot be started due to the failure of the master node, and it is possible to efficiently perform the degrating process.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of an embodiment of the present invention.

FIG. 2 is a diagram for simply describing a configuration inside a CPU control unit in the embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration inside a CPU control unit according to an embodiment of the present invention.

FIG. 5 is a flowchart illustrating the operation of one embodiment of the present invention.

[Description of Signs] 1, 10 to 17 CPUs 2, 20 to 23 CPU control unit 3 Memory 4 ROM 5 I / O control unit 6 System bus 7 Cluster bus 8, 80 to 83 Connect line 9 Local bus 60 to 63 nodes

Claims (4)

[Claims] A plurality of CPUs and a CPU control unit for controlling each of the CPUs are connected by a cluster bus, a memory shared by the plurality of CPUs, and an I / O.
A multi-CPU system in which the plurality of CPU control units are coupled via a system bus, wherein the CPU control controls the CPU to disconnect the CPU from the cluster bus. (Referred to as a “freeze register”), and a register (referred to as a “CPU status register”) indicating a connection status of the cluster bus of the CPU, wherein each of the CPUs on the cluster bus operates. At the start, a flag indicating a cluster connection is written in the CPU status register corresponding to the own CPU, and thereafter,
Initial diagnosis of the PU is started, and if an abnormality is found in the CPU and it is determined that the CPU is faulty, the freeze register is written to logically disconnect the CPU determined to be faulty from the cluster bus. , The CPU control unit includes:
A CPU degrading method for a cluster-connected multi-processor system, wherein the CPU is controlled so as not to be disconnected from the system by not responding to a request from the failed CPU at all. 2. The system according to claim 1, wherein the CPU control unit is configured to control a unique CP of the CPU on the cluster bus in the CPU control unit.
U, a CPU ID number register indicating the ID number of the U, a node ID number register indicating a node ID number unique to the system, and a dedicated signal line (“connect”) indicating the logical connection status between the CPU control unit and the system bus. A register for receiving connection lines from a plurality of other CPU control units, and holding a mounting state of the control unit at the time of reset (referred to as a “configuration register”); A register (referred to as a “disconnect detection register”) indicating that the CPU and the CPU are disconnected from the system bus after an initial diagnosis of the CPU and the CPU control; Control register ("Disconnect
After the initial diagnosis of the CPU, when all the CPUs on the cluster (node) connected to the CPU control unit are determined to have failed and all the CPUs have written to the freeze register; and If there is no write operation to the CPU status register within a certain period due to failure or non-mounting of all CPUs in the node, the connection line is immediately negated, and the CPU control unit and the system When the CPU is disconnected from the bus and the initial diagnosis of the CPU is completed normally, the CPU status register, the freeze register, the CP
The U / ID number register is read out, and the normal CPU with the smallest CPU / ID number in each CPU control unit becomes the node / master CPU, and starts initial diagnosis of each CPU control unit. If it is determined that a failure has occurred, write to the disconnect register, negate the connect line and disconnect from the system bus. The master CPU reads the configuration register, the disconnect detection register, and the node ID register, and operates normally, and the node master CPU having the smallest ID number is the system master C.
The cluster connection multi-C according to claim 1, wherein control is performed so as to be determined as a PU.
CPU degrading method for PU system. 3. An initial diagnosis of a CPU, an initial diagnosis of a CPU control unit,
A memory for storing respective programs for system initial diagnosis; and at reset such as when power is turned on, (a) each of the CPU control units asserts a connect line, and the mounting status of the CPU control unit is changed by another CPU control unit. , While the other C
(B) the plurality of CPUs read out the initial diagnosis program from the memory, and (c) the CPU reads the connection line from the PU control unit. Write to the CPU status register of
(D) The CPU performs an initial diagnosis inside the CPU itself, determines that a failure has occurred in its own CPU, writes to the freeze register, and writes all the If the CPU writes to the freeze register, the connection line is negated and the CP
The U control unit is logically disconnected from the system bus (e). On the other hand, the CPU that has normally completed the initial diagnosis reads the CPU status register, the freeze register, and the CPU ID number register, and performs normal operation. To C
The CPU that has completed the PU initial diagnosis and has the smallest CPU ID number is the node master CPU in the CPU control unit.
(F) the node master CPU is
The U control unit initial diagnosis is performed, and if an abnormality is found in the base CPU control unit, a write is performed to the disconnect register, the connect line is negated, and the logical connection between the CPU control unit and the system bus is performed. (G) The node master C that has successfully completed the initial diagnosis of the CPU control unit.
The PU reads the configuration register, the disconnect detection register, and the node ID register, and connects to the node I of the CPU control unit having the smallest node ID number while being connected to the system bus.
D is checked, and if this node ID is equal to its own node ID number, it becomes the system master CPU and performs the initial diagnosis of the system to dynamically disconnect the failed CPU from the system. Claim 1
C of the cluster-attached multi-processor system described
PU degrate method. 4. A plurality of CPUs and a CPU for controlling the CPUs
A control unit is connected via a cluster bus to form a CPU node, and the CPU control unit is connected to a CPU control unit of another CPU node via a system bus, a memory, and an I / O.
C in the multi-CPU system connected to the control unit
A PU degrading method, wherein the CPU control unit includes at least a first register for CPU disconnection control and a second register indicating a connection state of a cluster bus of the CPU; And a means for dynamically determining a master in each hierarchy, that is, a CPU and a node.
System CPU degrading method.