JPH11149719A5 - - Google Patents
Info
- Publication number
- JPH11149719A5 JPH11149719A5 JP1997348208A JP34820897A JPH11149719A5 JP H11149719 A5 JPH11149719 A5 JP H11149719A5 JP 1997348208 A JP1997348208 A JP 1997348208A JP 34820897 A JP34820897 A JP 34820897A JP H11149719 A5 JPH11149719 A5 JP H11149719A5
- Authority
- JP
- Japan
- Prior art keywords
- signal
- cpu
- video
- interrupt
- bits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Description
【００２１】
記録時の入力信号の流れを説明すると、まず、ＤＶビデオカメラ１によりビデオ電気信号に変換された映像信号は、ビデオ圧縮するエンコード／デコード部１ａにより、高能率符号化され、オーディオデータをマルチプレクスされ、ＤＶ方式で定義されるＤＩＦブロックからなるＡＶデジタルデータストリームが得られる。ＡＶデジタルデータストリームは、標準解像度のＳＤ（Standard Definition ）、高圧縮ＳＤ、高解像度テレビジョン受像器（High Definition Television; HDTV）に対応するＨＤ（High Definition ）の３つの仕様によりそれぞれ規格として定義されている。[0021]
To explain the flow of input signals during recording, first, the video signal converted into an electric video signal by the DV video camera 1 is highly efficiently encoded by the encoding/decoding unit 1a, which compresses the video, and then audio data is multiplexed to obtain an AV digital data stream consisting of DIF blocks defined by the DV format. AV digital data streams are defined as standards according to three specifications: standard definition SD (Standard Definition ), highly compressed SD, and HD (High Definition) compatible with high definition television receivers (HDTV).
【００５８】
またこれとともに、外部ベクタ生成回路１１３は、割込み要求のあったデバイスに割り当てられた上述の割り込みレベル信号をうけたＣＰＵが発するベクタフェッチのストロー部（状態制御）信号とＲＥＡＤ信号、およびこの状態で割込み優先レベルＩＲＬ０−〜ＩＲＬ３−をうけて、ＣＰＵにより内部で下位４ビットのアドレス信号に変換されＣＰＵから出力されてきた割込み優先レベル番号をＡＤＲ[３．．０]のアドレスバスの下位４ビットで入力される。[0058]
At the same time, the external vector generation circuit 113 receives the vector fetch strobe (state control) signal and READ signal issued by the CPU upon receiving the above-mentioned interrupt level signal assigned to the device that has issued the interrupt request, as well as the interrupt priority levels IRL0- to IRL3- in this state, and receives the interrupt priority level number that is converted into an address signal of the lower 4 bits by the CPU and output from the CPU as input to the lower 4 bits of the address bus ADR[3..0].
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9348208A JPH11149719A (en) | 1997-09-10 | 1997-12-17 | Information recording apparatus and method, and recording medium |
| TW087114482A TW451188B (en) | 1997-09-10 | 1998-09-01 | Information recording method and apparatus and information recording medium |
| EP98307180A EP0902432A3 (en) | 1997-09-10 | 1998-09-04 | Information recording method and apparatus and information recording medium |
| US09/150,197 US6684026B2 (en) | 1997-09-10 | 1998-09-08 | Information recording method and apparatus and information recording medium |
| MYPI98004110A MY120761A (en) | 1997-09-10 | 1998-09-09 | Information recording method and apparatus and information recording medium |
| CNB981267718A CN1178223C (en) | 1997-09-10 | 1998-09-10 | Information recording method and equipment |
| KR1019980037264A KR100626101B1 (en) | 1997-09-10 | 1998-09-10 | Method and apparatus for recording information and Method and apparatus for reproducing information |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9-245657 | 1997-09-10 | ||
| JP24565797 | 1997-09-10 | ||
| JP9348208A JPH11149719A (en) | 1997-09-10 | 1997-12-17 | Information recording apparatus and method, and recording medium |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006327509A Division JP2007109392A (en) | 1997-09-10 | 2006-12-04 | Information recording apparatus and information recording method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11149719A JPH11149719A (en) | 1999-06-02 |
| JPH11149719A5 true JPH11149719A5 (en) | 2004-12-16 |
Family
ID=26537339
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9348208A Pending JPH11149719A (en) | 1997-09-10 | 1997-12-17 | Information recording apparatus and method, and recording medium |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11149719A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4509229B2 (en) * | 1997-11-29 | 2010-07-21 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Audio recording method and apparatus, record carrier, and reproducing apparatus |
| JP2001229616A (en) | 2000-02-10 | 2001-08-24 | Matsushita Electric Ind Co Ltd | Data recording method and data recorder using the method |
-
1997
- 1997-12-17 JP JP9348208A patent/JPH11149719A/en active Pending
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