JPH11150448A - Oscillation circuit - Google Patents

Abstract

(57) [Problem] To provide an oscillation circuit that generates an oscillation signal having a high frequency equal to or higher than a fundamental oscillation frequency by a simple circuit without largely changing a circuit configuration. SOLUTION: An oscillation unit 10, a comparison circuit 20, and a multiplication unit 30 are provided. In the oscillation unit 10, the on / off state of transistors Q1 and Q2 is alternately switched, so that the capacitor C1 repeatedly performs charging and discharging. Outputs oscillation signal. The comparing unit 20 compares both electrode potentials of the capacitive element C1, and outputs a comparison signal according to the comparison result. The multiplication unit 30 obtains an exclusive OR of the comparison signal of the comparison unit 20 and the oscillation signal of the oscillation unit 10, that is, the signal of the node ND3 or ND4, thereby obtaining a double signal of the fundamental oscillation frequency of the oscillation unit 10. it can. As a result, an oscillation signal having a frequency higher than the fundamental oscillation frequency can be generated without making a significant change to the oscillation circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation circuit capable of generating a double signal of an oscillation signal having a basic oscillation frequency with a simple circuit configuration without making a major change to the circuit.

[0002]

2. Description of the Related Art An example of a voltage controlled oscillator (VCO) used in a PLL is an emitter-coupled VCO.
Is mentioned. In such a VCO, the oscillation frequency is determined according to the capacitance of the capacitor and the current value of the current source.

FIG. 3 is a circuit diagram showing a configuration example of a commonly used emitter-coupled VCO. In the VCO of the present example, the transistors Q1 and Q2 alternately switch the on / off state, so that the capacitive element C1 connected between the emitters of the transistors Q1 and Q2.
Are repeatedly charged and discharged. As the capacitor C1 is charged and discharged, the collector voltages of the transistors Q1 and Q2 change alternately, and these voltages are changed to the transistors Q3 and Q4.
Are input to both input terminals of the differential amplifier circuit including the transistors Q5 and Q6, respectively.

[0004] The differential amplifier circuit amplifies the input voltage and outputs a differential voltage. Further, the differential voltage is fed back to the bases of the transistors Q1 and Q2 via an emitter follower including the transistors Q7 and Q8. As a result, the transistor Q1
And the switching of the ON / OFF state of Q2 is continued, and the charging and discharging of the capacitor C1 are repeatedly performed. Accordingly, continuous oscillation signals can be output from the nodes ND3 and ND4, for example.

In the circuit example shown in FIG. 3, the operating currents supplied by the current sources I1 and I2 are both I _0, and the capacitance value of the capacitive element C1 is C ₀ . Furthermore, the maximum voltage difference [Delta] V _C between the collector and the supply voltage V _CC of the transistors Q5 and Q6 constituting a differential amplifier circuit, i.e., ([Delta] V _C = V
When _CC -V _R) to, the illustrated VCO oscillation frequency f
₀ is obtained by the following equation.

[0006]

F ₀ = I ₀ / (4ΔV _C C ₀ ) (1)

FIG. 4 shows that the nodes ND1 and ND2 and nodes ND3 and ND4 when the VCO shown in FIG.
3 shows the waveforms of FIG. Note that the nodes ND1 and ND
2 have a phase difference of π, and similarly, the waveforms of the nodes ND3 and ND4 also have a phase difference of π.

FIG. 4A shows, for example, the waveform at the node ND3, and the dotted line in FIG. 4B shows the waveform at the node ND1.
The solid line in FIG. 3B shows the waveform of the node ND2. As described above, the nodes ND3 and ND
4 have a phase difference of π, when the node ND3 shown in FIG.
4 is at low level. Conversely, when the node ND3 is at a low level, the node ND4 is held at a high level.

Here, a description will be given assuming that the state where the node ND3 is at a low level and the node ND4 is at a high level is an initial state. In this state, the transistor Q1 is kept off and the transistor Q2 is kept on. In this case, the electric charge of the electrode connected to the node ND1 of the capacitor C1 is released via the current source I2, so that the potential of the node ND1 gradually decreases. And node N
When the potential of D1 becomes lower than the potential of the node ND3 by a voltage drop between the base and the emitter of the transistor Q1, the transistor Q1 switches from the off state to the on state. In response, the collector voltage of transistor Q1 decreases, and transistor Q5 is turned off. Therefore, the collector voltage of transistor Q5 rises and reaches the level of power supply voltage V _CC , so that the potential of node ND3 also rises and the on state of transistor Q1 is determined.

On the other hand, in the differential amplifier circuit including the transistors Q5 and Q6, the transistor Q5 is turned off, so that the transistor Q6 is turned on. In response, the collector voltage of transistor Q6 decreases, the potential of node ND4 also decreases, and transistor Q2 switches from the on state to the off state. In this state, the potential of node ND1 is substantially constant. On the other hand, the electric charge stored in the electrode of the capacitor C1 connected to the node ND2 is released via the current source I2, and the potential of the node ND2 gradually decreases. And the node ND2
Is higher than the potential of the node ND4,
When the voltage drops below the base-emitter voltage drop of
The transistor Q2 switches from the off state to the on state.

As described above, since the on / off states of the transistors Q1 and Q2 change alternately, a square wave shown in FIG. 4A is output from the node ND3. Further, as described above, a waveform having a phase difference π from the node ND3 is obtained from the node ND4. Further, with the switching of the on / off states of the transistors Q1 and Q2, the potentials of the nodes ND1 and ND2 become as shown in FIG. When the transistor Q1 or Q2 switches from the on state to the off state, the emitter potential of the transistor is raised to a high level by capacitive coupling of the capacitive element C1. Then, when the emitter potential gradually decreases due to the discharge of the accumulated charge from the electrode of the capacitor C1, and the difference from the base potential becomes larger than the base-emitter voltage drop,
The on / off state of the transistors Q1 and Q2 is switched.

As described above, the VCO of this embodiment can generate an oscillation signal having a frequency corresponding to the capacitance value of the capacitor, the current value of the current source, and the reference voltage.

[0013]

[SUMMARY OF THE INVENTION Incidentally, in a system using a conventional VCO described above, for example, when the oscillation signal of doubled frequency 2f ₀ of the fundamental frequency f ₀ for some reason is needed, the capacitor The capacitance value C _{0 of} C1,
Alternatively, either one of the reference voltages V _R is set to half, or the current value I ₀ of the current sources I1 and I2 is set to double, and VC
It is necessary to double the oscillation frequency of O itself. But,
An increase in the operating current leads to an increase in power consumption, or a decrease in the capacitance value of the capacitor and the reference voltage, an increase in jitter of the oscillation signal, and a deterioration in the SN ratio of the oscillation signal. Further, in order to increase the basic frequency of the VCO, various changes need to be made in consideration of high-frequency operation at the time of circuit design, which may complicate circuit design and increase costs.

The present invention has been made in view of the above circumstances, and an object of the present invention is to generate an oscillation signal having a frequency higher than the fundamental oscillation frequency by a simple circuit without having to largely change the circuit configuration. It is to provide a possible oscillating circuit.

[0015]

In order to achieve the above object, an oscillation circuit according to the present invention comprises a first amplifier and a second amplifier which form a differential amplifier pair.
, A capacitive element connected between the emitters of the first and second transistors, and first and second current sources for supplying a predetermined operating current to the emitters of the first and second transistors And the first and second
An oscillation circuit provided with an oscillation unit that generates an oscillation signal having a predetermined frequency by positively feeding back a signal appearing at the collector of the transistor to the bases of the first and second transistors, The first of the above capacitive elements
And the potential of the second electrode are compared, and based on the comparison result,
A voltage comparison circuit is provided for generating a second oscillation signal having a predetermined phase difference with respect to the oscillation signal, for example, a phase difference of π / 2.

Further, the oscillation circuit of the present invention comprises a first and a second transistor forming a differential amplification pair, and the first and second transistors.
And a first and second current source for supplying a predetermined operating current to the emitters of the first and second transistors,
An oscillating unit is provided that generates an oscillation signal having a predetermined frequency by positively feeding back the signals appearing at the collectors of the first and second transistors to the bases of the first and second transistors. An oscillation circuit that compares the potentials of the first and second electrodes of the capacitive element and has a predetermined phase difference, for example, a phase difference of π / 2, with respect to the oscillation signal based on the comparison result. A voltage comparison circuit for generating the second oscillation signal, and the oscillation signal from the oscillation section and the second oscillation signal from the voltage comparison circuit.
A multiplying circuit for generating a multiplied signal of the oscillation signal.

In the present invention, preferably, the comparison circuit includes a third transistor having a base connected to the first electrode of the capacitor and a collector connected to a load element, and a base connected to the capacitor. A fourth transistor connected to the second electrode of the element and having a collector connected to the load element, wherein the emitters of the third and fourth transistors are connected to each other, and the connection point is a predetermined operating current. Connected to a current source that supplies

Further, in the present invention, preferably, the multiplying circuit is constituted by an exclusive OR circuit. The exclusive OR circuit has one input terminal to which the output signal of the comparing circuit is applied, and A second comparison circuit in which a predetermined reference voltage is applied to an input terminal of the second comparison circuit, an output signal of the comparison circuit is applied to one input terminal, a predetermined reference voltage is applied to the other input terminal, and A third comparing circuit having one output terminal commonly connected to the second output terminal, and the second and third transistors in accordance with a signal fed back to the base of the first or second transistor. A current supply circuit for alternately supplying the first and second operating currents to the comparison circuit.

According to the present invention, a VCO, for example, two transistors forming a differential amplifier pair and two current sources for supplying operating currents to the emitters of these transistors, and further connected between the emitters of these transistors, Emitter-coupled VCO composed of a capacitive element that repeats charging and discharging as the transistor is turned on / off
As a result, oscillation signals having a phase difference of π are output. The comparison circuit compares the potentials of both electrodes of the capacitor constituting the VCO, and outputs a second oscillation signal having a phase difference of π / 2 from the oscillation signal according to the comparison result. A predetermined signal processing based on the second oscillation signal and the oscillation signal generated from the VCO, for example, calculating an exclusive OR of the two signals to generate a signal twice the fundamental oscillation frequency of the VCO. be able to.

As a result, an oscillation signal having a frequency twice as high as the fundamental oscillation frequency can be obtained without making a significant change in the circuit configuration. Can be obtained.

[0021]

FIG. 1 is a circuit diagram showing an embodiment of an oscillation circuit according to the present invention. As illustrated, the oscillation circuit of the present embodiment includes an oscillation unit 10, a comparison unit 20, and a multiplication unit 30. The oscillating unit 10 is configured by an emitter-coupled VCO. As shown,
In the oscillating unit 10, a differential amplifier circuit includes the transistors Q1 and Q2, the capacitance element C1, the resistance elements R1 and R2, and the current sources I1 and I2. Transistor Q
2, Q4 and current sources I3, I4 constitute an emitter follower that outputs the collector voltage of the differential amplifier circuit. The transistors Q5 and Q6, the current source I5 and the resistance elements R3 and R4 form a differential amplifier circuit for amplifying the output signal of the emitter follower. The differential signal output from the differential amplifier circuit is applied to the transistors Q7 and Q8.
The current is fed back to the bases of the transistors Q1 and Q2 via the emitter followers formed by the current sources I6 and I7.

The bases of the transistors Q1 and Q2 are respectively connected to the node ND3, ND4, a collector connected to the supply voltage V _CC through a respective resistance elements R1, R2, the emitter is connected to the current source I1, I2, respectively I have. The capacitive element C1 is connected between the emitters of the transistors Q1 and Q2.

The transistor Q3 and the current source I3,
The transistor Q4 and the current source I4 each constitute an emitter follower. The base of transistor Q3 is connected to the collector of transistor Q2, and the base of transistor Q4 is connected to the collector of transistor Q1. The emitter of the transistor Q3, Q4 are connected to the current source I3, I4, respectively, collectors are both connected to the power supply voltage V _CC. Transistors Q3 and Q4
A voltage lower than the collector voltage of the transistors Q1 and Q2 by the base-emitter voltage drop is output from the emitters of the transistors Q3 and Q4.

The transistors Q5 and Q6 form a differential amplifier circuit. The bases of the transistors Q5 and Q6 are connected to the emitters of the transistors Q4 and Q3, the emitters are connected to each other, and the connection point is connected to the current source I5. Further, the collectors of the transistors Q5 and Q6 are connected to the power supply voltage V _CC via the resistance elements R3 and R4, respectively.

Transistor Q5 constituting differential amplifier circuit
And the collector voltages of Q6 and Q6 are output to nodes ND3 and ND4 via emitter followers including transistors Q7 and Q8 and current sources I6 and I7. The base of the transistor Q7 is connected to the collector of the transistor Q5, the collector is connected to the power supply voltage V _CC , and the emitter is connected to the current source I6. Similarly, transistor Q8
A base connected to the collector of the transistor Q6, the collector connected to the power source voltage V _CC, the current source I to the emitter
7 is connected.

The emitter of the transistor Q7 is connected to the node ND.
3. The emitter of the transistor Q8 constitutes the node ND4. Further, node ND3 is connected to the base of transistor Q1, and node ND4 is connected to the base of transistor Q2.

In the oscillating unit 10 having the above configuration,
The switching of the on / off state of the transistors Q1 and Q2 constituting the differential amplifier circuit is repeatedly performed, whereby the capacitor C1 is repeatedly charged and discharged, and the oscillation having a predetermined frequency is output from the node ND3 or ND4. A signal is output. FIG. 2 is a waveform diagram showing signal waveforms at various points when the oscillation circuit shown in FIG. 1 operates. Hereinafter, the operation of the oscillation unit 10 will be described in detail with reference to FIGS.

FIG. 2A shows the waveform of the voltage of the node ND3, and FIGS. 2B and 2C show the waveforms of the nodes ND1 and ND3.
The waveform of D2 is shown. As shown in FIG. 2A, it is assumed here that the node ND3 is held at a low level as an initial state. Although not shown, the signal waveform at the node ND4 has a phase difference π with the signal waveform at the node ND3. That is, when the node ND3 is at a low level, the node ND4 is held at a high level, and when the node ND3 is at a high level, the node ND4 is held at a low level.

In the above initial state, the transistor Q
1 is set to the off state, and the transistor Q2 is set to the on state. If the base current is negligibly small when the transistor Q2 is kept on, the collector current is the sum of the currents of the current sources I1 and I2. That is, 2I ₀ . As a result, the collector potential and the collector-emitter voltage of the transistor Q2 become constant, so that the emitter potential of the transistor Q2 does not change and is kept at a constant value. Since the transistor Q1 is held in the OFF state, its collector is held substantially the power supply voltage V _CC level. In response, the potential of node ND3 is also kept constant.

In the differential amplifier circuit including the transistors Q5 and Q6, since the transistor Q5 is maintained in the ON state and the transistor Q6 is maintained in the OFF state, the potentials of the nodes ND3 and ND4 are changed to the resistance elements R3 and R4 and the current sources. It is determined by I5 and the base-emitter voltage drop of transistors Q7 and Q8 constituting the emitter follower.

Here, the power supply voltage V _CC is 5 V, the resistance values r ₃ and r ₄ of the resistance elements R ₃ and R ₄ are both ₄ kΩ, the current value I ₁ of the current source I 5 is 100 μA, the transistor Q 7,
Both the base-emitter voltage drop V _BE of Q8 is 0.7
V, the potential V at the nodes ND3 and ND4
_ND3 and _VND4 are respectively obtained as follows.

[0032]

[Number 2] _{V ND3 = (V CC -r 3} I 1) -V BE = 3.9V V ND4 = V CC -V BE = 4.3V ... (2)

In the following description, when the transistor Q5 or Q6 is on, the resistance elements R3 and R3
The voltage drop r ₃ I ₁ generated in _No. 4 is denoted as ΔV _C. That is, (ΔV _C = r ₃ I ₁ = r ₄ I ₁ ).

Since the transistor Q1 is off,
Capacitive element C1 is charged by the current I ₀ of the current source I1, the potential of the node ND1 gradually decreases. Node ND
1 is lower than the base potential of the transistor Q1, that is, the potential V _{ND3 of the} node ND3 by the voltage drop between the base and the emitter of the transistor Q1.
Switches from the off state to the on state. Here, the voltage drop between the base and the emitter of the transistors Q1 and Q2 is V
_{Assuming BE} , when the transistor Q1 is switched from the off state to the on state, the potential V _{ND1 of the} node ND1 decreases,
This is performed when the potential shown in the following equation is reached.

[0035]

V _ND1 = V _ND3 -V _BE = V _CC -ΔV _C -2V _BE (3)

Assuming that the base-emitter voltage drop V _BE of the transistors Q1 and Q2 is 0.7V, when the potential V _ND1 of the node ND1 drops to 3.2V according to the equation (3), the transistor Q1 is turned off. Switches to the ON state.

When the transistor Q1 is turned on, the collector potential of the transistor Q1 decreases, and accordingly, the transistor Q1
5 switches from the on state to the off state. For this reason, the on / off states of the transistors Q5 and Q6 are switched,
The transistor Q5 is turned off, and the transistor Q6 is turned off. As a result, the potentials of the nodes ND3 and ND4 interchange with each other, and (V _ND3 = V _CC -V _BE = 4.3V, V
_ND4 = become _{V CC -ΔV C -V BE = 3.9V} ). As described above, the potential of the node ND3 rises from the low level of 3.9V to the high level of 4.3V, and the potential of the node ND4 drops from the high level of 4.3V to the low level of 3.9V. The on state of Q1 is determined, and at the same time, the transistor Q2 is turned off.

In this case, the transistor Q1 is kept on, and the potential V _{ND3 of the} node _ND3 becomes (V _CC -V _BE
= 4.3V), the potential V of the node ND1 is
_ND1 is lower than the potential of the node ND3 by the base-emitter voltage drop V _{BE of the} transistor Q1. That is, the potential of the node ND1 becomes (V _ND1 = V _CC -2V _BE =
3.6V).

As described above, at the moment when the transistor Q1 is switched from the off state to the on state, the potential V _{ND1 of the} node _ND1 is changed from 3.2V to 3.6V, that is, the resistance element R3
Alternatively, the voltage is raised by the voltage drop ΔV _C generated in R4. Further, since the transistor Q2 is off,
Due to the capacitive coupling of the capacitive element C1, the potential of the node ND2 is also raised by V _BE . As a result, node N
In D2, when the transistor Q2 is in the ON state (V _CC -2
(V _BE = 3.6 V), and when the transistor Q2 is turned off, the potential of the node ND2 is raised by ΔV _C , and (V _CC -2V _BE + ΔV _C = 4.0 V).
become.

When the transistor Q2 is kept off, the capacitor C1 is charged by the current source I2, and the potential of the node ND2 gradually decreases. When the potential of the node ND2 becomes lower than the base potential of the transistor Q2, that is, the potential of the node ND4 by the voltage drop V _BE between the base and the emitter of the transistor Q2, the transistor Q2 is turned on again.

Therefore, the change in the potential of the node ND1 or the node ND2 due to the charging / discharging of the capacitive element C1 is 2ΔV
_C. In the above example, the potential of the node ND1 or the node ND2 is changed by charging / discharging of the capacitor C1.
It falls from 4.0V to 3.2V. Node ND1
Alternatively, when the potential of the node ND2 reaches 3.2 V, the state of the transistor Q1 or Q2 switches.

As a result, the capacitance value C ₀ of the capacitance element C1, the current value I ₀ of the current sources I1 and I2, and the resistance element R3
According to the voltage drop ΔV _{C of} R4, the charging / discharging time T ₀ of the capacitor C1 and the oscillation frequency f ₀ of the oscillation unit 10 can be obtained as follows.

[0043]

T ₀ = 2ΔV _C C ₀ / I ₀ f ₀ = 1 / (2T ₀ ) = I ₀ / (4ΔV _C C ₀ ) (4)

Next, the configuration and operation of the comparing section 20 will be described. As shown in the figure, the comparison unit 20 includes transistors Q9 and Q10, resistance elements R5 and R6, and a current source I8. Transistors Q9 and Q10 form a differential amplifier circuit. The base of transistor Q9 is connected to node ND2, the collector is connected to power supply voltage V _CC via resistor R5, the base of transistor Q10 is connected to node ND1, and the collector is power supply voltage V _CC via resistor R6. It is connected to the. further,
The emitters of the transistors Q9 and Q10 are connected,
The current source I8 is connected to the connection point.

The voltage of the nodes ND1 and ND2 is compared by the comparing section 20 thus configured, and the potential of the output node ND5 is determined according to the comparison result. Here, the resistance value of the resistance element R6 is 4 kΩ, and the current value of the current source I8 is 1
If the current is set to 00 μA, the potential of the node ND1 becomes
Transistor Q9 is off,
Transistor Q10, respectively held in the ON state, the potential of the node ND5 is held at the power supply voltage V _CC level.
Conversely, when the potential of the node ND1 is lower than the potential of the node ND2, the transistor Q9 is turned on, the transistor Q10 is held respectively in the OFF state, the voltage drop of the potential of the node ND5 power supply voltage V _CC from the resistive element R5 Only lower. That is, it is maintained at (5V−0.4V = 4.6V).

The multiplication unit 30 includes two comparison circuits 32 and 34
And a current supply circuit 36 for supplying an operation current to these comparison circuits. The resistance element R7, the transistor Q11 and the current sources I9 and I10 are provided for generating a reference voltage. Resistance element R7 and current source I
9 is connected in series between the power supply voltage V _CC and the ground potential GND. A connection point between the resistance element R7 and the current source I9 forms a node ND6. Transistor Q1
1 of a base connected to node ND6, a collector connected to the power source voltage V _CC, an emitter connected to a current source I10.

[0047] The current value of the resistance element R7 and the current source I9, a predetermined reference voltage V _ref1 is generated node ND6, node ND7, i.e., the base of the transistor Q11 than the reference voltage V _ref1 to the emitter of the transistor Q11
Only emitter voltage drop V _BE partial lower reference voltage V _ref2 is generated.

In comparison circuit 32, transistor Q1
The base of transistor 2 is connected to node ND5, the collector is connected to power supply voltage V _CC , the base of transistor Q13 is connected to node ND6, and the collector is connected to power supply voltage V _CC via resistor R8. Further, the emitters of the transistors Q12 and Q13 are connected to each other, and the connection point is connected to the collector of the transistor Q16.

In comparison circuit 34, transistor Q1
4 is connected to node ND6, the collector is connected to power supply voltage V _CC , the base of transistor Q15 is connected to node ND5, and the collector is transistor Q13.
Connected to the collector. The connection node ND9
Is connected to the output terminal T _out . Further, the emitters of the transistors Q14 and Q15 are connected to each other, and the connection point is connected to the collector of the transistor Q17.

The transistors Q16 and Q17 and the current source I11 make the current supply circuit 36 of the comparison circuits 32 and 34 available.
Is configured. The base of transistor Q16 is connected to node ND7, and the base of transistor Q17 is connected to node ND4. Transistors Q16 and Q
17 are connected to each other, and a current source I
11 are connected. The configuration of the current supply circuit 36 is not limited to the above, and for example, the base of the transistor Q17 can be connected to the node ND3.

When the potential of the node ND4 is higher than the reference voltage _Vref2 , in the current supply circuit 36, the transistor Q16 is kept off and the transistor Q17 is kept on. Therefore, the current of the current source I11 is supplied to the comparison circuit 34 via the transistor Q17. That is, in this case, the comparison circuit 32 is set to the non-operation state, and the comparison circuit 34 is set to the operation state. vice versa,
When the potential of the node ND4 is lower than the reference voltage _Vref2 ,
In the current supply circuit 36, the transistor Q16 is kept on and the transistor Q17 is kept off. Therefore, the current of the current source I11 is
The signal is supplied to the comparison circuit 32 via the line 16. In this case, the comparison circuit 32 is set to the operation state, and the comparison circuit 34 is set to the non-operation state. As described above, the comparison circuits 32 and 34 are alternately set to the operation state according to the comparison result between the potential of the node ND4 and the reference voltage _Vref2 .

The comparison circuits 32 and 34 control the node ND5
, That is, the output signal of the comparison unit 20 and the reference voltage V _ref1
Are compared, and the potential of the node ND9 is set according to the comparison result. For example, when the comparison circuit 32 is in the operating state, when the potential of the node ND5 is higher than the reference voltage _Vref1 , the transistor Q12 is kept on and the transistor Q13 is kept off, and the output terminal T _out is high level, that is, It is kept at the power supply voltage V _CC level. Conversely, when the potential of the node ND5 is lower than the reference voltage _Vref1 , the transistor Q12 is kept off and the transistor Q13 is kept on, and the output terminal _Tout is kept low. The voltage difference between the high level and the low level of the output terminal T _out corresponds to the voltage drop amount generated in the resistive element R8, determined by the resistance value and current value of the current source I11 of the resistance element R8.

As described above, when the comparison circuit 34 is in the operating state, the potential level of the output terminal _Tout is determined according to the comparison result between the potential of the node ND5 and the reference voltage _Vref1 .

[0054] FIG. 2 (d) and (e) are respectively shows the voltage waveform of the node ND5 and the output terminal T _out. As shown, the potential of the node ND5, that is, the comparison unit 2
The output signal level of 0 is determined according to the potential difference between the nodes ND1 and ND2. When the potential of the node ND1 is high, a high-level comparison result is obtained from the node ND5, and when the potential of the node ND1 is low, a low-level comparison result is obtained from the node ND5.

As a result, as shown in the figure, the output signal of the comparing section 20 becomes a square wave, and this square wave has a phase difference of π / 2 as compared with the signal of the node ND3 or the node ND4. Therefore, by alternately setting the comparison circuits 32 and 34 in the multiplier 30 to the operating state in accordance with the node ND3 or the node ND4, the output terminals T _out allow the nodes ND3 (or the node ND4) and the node ND5 to be connected. The exclusive OR of the signals is obtained. The exclusive OR signal is
As shown, the frequency has twice the frequency of the oscillation signal of the oscillation unit 10.

As described above, according to the present embodiment, the oscillation unit 10, the comparison circuit 20, and the multiplication unit 30 are provided, and the potentials of both electrodes of the capacitive element C1 in the oscillation unit 10 are compared by the comparison unit 20. A comparison signal is output according to the comparison result. In the multiplication unit 30, the comparison signal of the comparison unit 20 and the feedback signal of the oscillation unit 10, that is, the node ND3 or ND
By calculating the exclusive OR with the signal of No. 4, a signal twice the fundamental oscillation frequency of the oscillation unit 10 can be obtained. As described above, it is possible to generate an oscillation signal having a frequency higher than the fundamental oscillation frequency without making significant changes to the oscillation circuit.

The present invention is not limited to the above-described embodiment. For example, the multiplying unit 30 may be connected to an exclusive-OR circuit having another configuration, that is, a voltage signal of the node ND3 or ND4. It may be replaced with another arithmetic circuit capable of outputting an exclusive OR with the output signal of the comparing unit 20.

[0058]

According to the oscillation circuit of the present invention, there is an advantage that an oscillation signal having a frequency higher than the fundamental oscillation frequency can be generated by a simple circuit without having to largely change the circuit configuration.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of an oscillation circuit according to the present invention.

FIG. 2 is a waveform chart showing the operation of the oscillation circuit of the present invention.

FIG. 3 is a circuit diagram showing an example of a conventional emitter-coupled oscillation circuit.

FIG. 4 is a waveform chart showing an operation of a conventional oscillation circuit.

[Explanation of symbols]

10 oscillation unit, 20 comparison unit, 30 multiplier unit, 32, 3
4: comparison circuit, 36: current supply circuit, Q1, Q2, Q
3,..., Q17... Transistor, R1, R2, R3
..., R8 ... resistance elements, I1, I2, I3, ..., I11 ...
Current source, C1 ... capacitor element, T _out ... output terminal, V _CC ... power supply voltage, GND ... ground potential.

Claims (14)

[Claims] A first transistor forming a differential amplifier pair; a capacitor connected between emitters of the first and second transistors; a first element and a second element;
First and second current sources for supplying a predetermined operating current to the emitters of the first and second transistors, and outputs the signals appearing at the collectors of the first and second transistors to the first and second transistors.
An oscillation circuit provided with an oscillation section that generates an oscillation signal having a predetermined frequency by positively feeding back to the base of the transistor, and comparing the potentials of the first and second electrodes of the capacitive element. ,
An oscillation circuit having a voltage comparison circuit for generating a second oscillation signal having a predetermined phase difference with respect to the oscillation signal based on a comparison result. 2. The oscillation circuit according to claim 1, wherein said second oscillation signal has a phase difference of π / 2 with respect to said oscillation signal generated by said oscillation section. 3. The first and second transistors forming a differential amplifier pair, a capacitor connected between the emitters of the first and second transistors, and the first and second transistors.
First and second current sources for supplying a predetermined operating current to the emitters of the first and second transistors, and outputs the signals appearing at the collectors of the first and second transistors to the first and second transistors.
An oscillation circuit provided with an oscillation section that generates an oscillation signal having a predetermined frequency by positively feeding back to the base of the transistor, and comparing the potentials of the first and second electrodes of the capacitive element. ,
A voltage comparison circuit that generates a second oscillation signal having a predetermined phase difference with respect to the oscillation signal based on the comparison result; and the oscillation signal from the oscillation unit and the second oscillation signal from the voltage comparison circuit. A multiplying circuit for generating a multiplied signal of the oscillation signal according to the oscillation signal. 4. The oscillation circuit according to claim 3, wherein said second oscillation signal has a phase difference of π / 2 with respect to said oscillation signal generated by said oscillation section. 5. A first emitter follower which uses a collector voltage of the first transistor as an input signal and outputs a signal corresponding to the input signal, and a collector voltage of the second transistor as an input signal and outputs a signal corresponding to the collector voltage of the second transistor. 4. The oscillation circuit according to claim 3, further comprising a second emitter follower for outputting. 6. An output signal of said first and second emitter followers is used as a differential input signal, and these differential input signals are amplified to generate first and second feedback signals as differential signals. 6. The oscillation circuit according to claim 5, further comprising a second differential amplifier circuit. 7. A third emitter follower for inputting a signal corresponding to the first feedback signal to a base of the first transistor; and a third emitter follower for inputting a signal corresponding to the second feedback signal to the second transistor. 7. The oscillation circuit according to claim 6, further comprising a fourth emitter follower input to the base. 8. The comparison circuit includes a third transistor having a base connected to a first electrode of the capacitor and a collector connected to a load element, and a base connected to a second electrode of the capacitor. A fourth transistor having a collector connected to a load element, wherein the emitters of the third and fourth transistors are connected to each other, and a connection point is connected to a current source for supplying a predetermined operating current The oscillation circuit according to claim 3, wherein 9. The multiplying circuit according to claim 1, wherein said multiplying circuit comprises a logic circuit for obtaining an exclusive OR of the two signals in response to the oscillation signal from the oscillation section and the second oscillation signal from the comparison circuit. The oscillation circuit according to claim 3. 10. The logic circuit according to claim 1, wherein the output signal of the comparison circuit is applied to one input terminal and a predetermined reference voltage is applied to the other input terminal. The output signal of the comparison circuit is applied to
A third comparison circuit having a predetermined reference voltage applied to the other input terminal and one output terminal commonly connected to the second output terminal; a base of the first or second transistor; The second and third comparison circuits alternately output the first
The oscillation circuit according to claim 9, further comprising: a current supply circuit that supplies a second operating current. 11. The second comparison circuit includes a fifth transistor having a base to which the output signal of the comparison circuit is applied, and a sixth transistor having a base to which the reference voltage is applied. A collector of the fifth transistor is connected to a power supply voltage supply line, a load element is connected to a collector of the sixth transistor, and emitters of the fifth and sixth transistors are connected to each other; The oscillation circuit according to claim 10, wherein the first operating current is supplied to the power supply circuit by the current supply circuit. 12. The third comparison circuit includes a seventh transistor having a base to which the output signal of the comparison circuit is applied, and an eighth transistor having a base to which the reference voltage is applied. The collector of the seventh transistor is connected to a power supply voltage supply line, the collector of the eighth transistor is connected to the collector of the sixth transistor forming the second comparison circuit, and The oscillation circuit according to claim 10, wherein the emitters of the sixth transistor are connected to each other, and the connection point is supplied with the second operating current by the current supply circuit. 13. A current supply circuit comprising: a ninth transistor having a base to which a second reference voltage is applied and a collector connected to the second comparison circuit; and a base connected to the base of the first transistor. And a tenth transistor whose collector is connected to the third comparison circuit, the emitters of the ninth and tenth transistors are connected to each other, and a predetermined current is supplied to a connection point. The oscillation circuit according to claim 10, further comprising: 14. A current supply circuit comprising: a ninth transistor having a base to which a second reference voltage is applied and a collector connected to the second comparison circuit; and a base connected to the base of the second transistor. And a tenth transistor whose collector is connected to the third comparison circuit, the emitters of the ninth and tenth transistors are connected, and a predetermined current is supplied to a connection point. The oscillation circuit according to claim 10, further comprising a current source.