JPH1117341A - Frinted multilayer wiring board - Google Patents
Frinted multilayer wiring boardInfo
- Publication number
- JPH1117341A JPH1117341A JP9183243A JP18324397A JPH1117341A JP H1117341 A JPH1117341 A JP H1117341A JP 9183243 A JP9183243 A JP 9183243A JP 18324397 A JP18324397 A JP 18324397A JP H1117341 A JPH1117341 A JP H1117341A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- copper
- holes
- conductive
- conductive connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007747 plating Methods 0.000 claims abstract description 64
- 239000004020 conductor Substances 0.000 claims abstract description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 84
- 229910052802 copper Inorganic materials 0.000 claims description 69
- 239000010949 copper Substances 0.000 claims description 69
- 239000011231 conductive filler Substances 0.000 claims description 30
- 239000002245 particle Substances 0.000 claims description 28
- 239000011347 resin Substances 0.000 claims description 27
- 229920005989 resin Polymers 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 19
- 239000000615 nonconductor Substances 0.000 claims description 18
- 229920001187 thermosetting polymer Polymers 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000011162 core material Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 12
- 239000000843 powder Substances 0.000 claims description 12
- 239000011889 copper foil Substances 0.000 claims description 10
- 239000000945 filler Substances 0.000 claims description 7
- 239000003822 epoxy resin Substances 0.000 claims description 6
- 229920000647 polyepoxide Polymers 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 239000009719 polyimide resin Substances 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical class [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 claims description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 4
- FPAFDBFIGPHWGO-UHFFFAOYSA-N dioxosilane;oxomagnesium;hydrate Chemical compound O.[Mg]=O.[Mg]=O.[Mg]=O.O=[Si]=O.O=[Si]=O.O=[Si]=O.O=[Si]=O FPAFDBFIGPHWGO-UHFFFAOYSA-N 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims 1
- 238000013461 design Methods 0.000 abstract description 17
- 238000003825 pressing Methods 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 description 34
- 238000007796 conventional method Methods 0.000 description 12
- 239000000126 substance Substances 0.000 description 12
- 239000000853 adhesive Substances 0.000 description 11
- 230000001070 adhesive effect Effects 0.000 description 11
- 229910000679 solder Inorganic materials 0.000 description 11
- 238000005530 etching Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 9
- 230000001771 impaired effect Effects 0.000 description 8
- 230000007423 decrease Effects 0.000 description 7
- 238000001035 drying Methods 0.000 description 7
- 238000009713 electroplating Methods 0.000 description 7
- 238000003475 lamination Methods 0.000 description 7
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000012937 correction Methods 0.000 description 6
- 239000006071 cream Substances 0.000 description 6
- 238000005553 drilling Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000002788 crimping Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000007654 immersion Methods 0.000 description 4
- 238000012856 packing Methods 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 229910002092 carbon dioxide Inorganic materials 0.000 description 3
- 239000001569 carbon dioxide Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 101100517192 Arabidopsis thaliana NRPD1 gene Proteins 0.000 description 2
- 101150094905 SMD2 gene Proteins 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 150000002989 phenols Chemical class 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はプリント配線板の高
密度実装化及びスルーホールの小スペース化に係る構造
に関するものである。[0001] 1. Field of the Invention [0002] The present invention relates to a structure for achieving high-density mounting of a printed wiring board and reducing the space for through holes.
【０００２】[0002]
【従来の技術】近年、電子機器の軽薄短小化が急激に進
展中において、プリント配線板は、小型化，高密度実装
化すると、導通接続穴（スルーホール）の数が増加し、
設計上その配置とスペースが困難になっていた。また第
２の導通接続穴（スルーホール）５０は、コア材３４Ａ
に存在するブラインドバイアホール３８を避けて配置し
なければならず設計上の制約となっていた。以下、従来
技術の製造工程について、図５（ａ）〜（ｂ）と、図６
（ｃ）〜（ｆ）と、図７（ｇ）〜（ｈ）と、図８に基づ
き、具体的に説明する。2. Description of the Related Art In recent years, as electronic devices have been rapidly becoming lighter and thinner, the number of conductive connection holes (through holes) has increased as printed wiring boards have become smaller and more densely mounted.
The layout and space were difficult by design. The second conductive connection hole (through-hole) 50 is formed by the core material 34A.
Has to be arranged so as to avoid the blind via hole 38 existing in the above, which is a design restriction. Hereinafter, the manufacturing process of the conventional technique will be described with reference to FIGS.
A detailed description will be given based on (c) to (f), FIGS. 7 (g) to (h), and FIG.
【０００３】先ず、図５（ａ）に示すように、銅箔３１
・３２と絶縁基板３３からなるコア材３４Ａである。[0003] First, as shown in FIG.
A core material 34A composed of 32 and an insulating substrate 33;
【０００４】次いで、図５（ｂ）は、図５（ａ）のコア
材３４Ａに第１の貫通孔３５をマイクロドリルを用い
て、穿孔する。[0004] Next, in FIG. 5B, a first through hole 35 is formed in the core material 34A of FIG. 5A by using a micro drill.
【０００５】次いで、図６（ｃ）に示すように、図５
（ｂ）に化学めっきと電気銅めっきを併用施し、第１の
銅めっき層３６・３７を形成し、表裏導体接続の導通接
続穴３８（スルーホール）が得られる。[0005] Next, as shown in FIG.
In (b), chemical plating and electrolytic copper plating are performed in combination to form first copper plating layers 36 and 37, and a conductive connection hole 38 (through hole) for front and back conductor connection is obtained.
【０００６】次いで、図６（ｄ）は、図６（ｃ）の導通
接続穴３８内に熱硬化性の絶縁ペースト４０をスクリー
ン版の印刷スキージを用いて、充填し、仮乾燥、平坦化
して、約１７０℃、４０分間乾燥炉を用い本硬化する。Next, FIG. 6 (d) shows that the thermosetting insulating paste 40 is filled in the conductive connection hole 38 of FIG. 6 (c) by using a screen printing squeegee, temporarily dried and flattened. Full curing using a drying oven at about 170 ° C. for 40 minutes.
【０００７】次いで、図６（ｅ）に示すように、図６
（ｄ）の本硬化した絶縁ペースト４０表裏面に片面銅張
積層基材３９Ａ・３９Ｂを熱プレスを用い加熱、加圧に
より、積層圧着４５・４６し多層の銅張積層板３４を構
成する。Next, as shown in FIG.
(D) The single-sided copper-clad laminated base materials 39A and 39B are laminated and pressed 45 and 46 on the front and back surfaces of the fully cured insulating paste 40 by using a hot press and heated to form a multilayer copper-clad laminate 34.
【０００８】次いで、図６（ｆ）は、図６（ｅ）の多層
の銅張積層板３４に、マイクロドリルを用い、第１の導
通接続穴３８の径（ｄ1）よりも小さい径（ｄ2）で第２
の貫通孔４７を穿孔する。Next, FIG. 6F shows a diameter (d 1 ) smaller than the diameter (d 1 ) of the first conductive connection hole 38 using a micro drill on the multilayer copper-clad laminate 34 of FIG. 6E. d 2 ) second
Is formed.
【０００９】次いで、図７（ｇ）に示すように、図６
（ｆ）の第２の貫通孔４７内壁に、化学めっきと電気銅
めっきを併用施し、第２の銅めっき層４８・４９を形成
し、表裏導体を接続する第２の導通接続穴５０（スルー
ホール）を形成する。Next, as shown in FIG.
2F, chemical plating and copper electroplating are simultaneously applied to the inner wall of the second through hole 47 to form second copper plating layers 48 and 49, and the second conductive connection hole 50 (through hole) for connecting the front and back conductors. Holes).
【００１０】更に、図７（ｈ）は、公知のエッチング製
造技術を用いて、電極パターン及び第２のスルーホール
ランド層５２・５３を形成でき得る従来技術の多層プリ
ント配線板５９である。FIG. 7 (h) shows a prior art multilayer printed wiring board 59 in which an electrode pattern and second through-hole land layers 52 and 53 can be formed using a known etching manufacturing technique.
【００１１】次に、図８は、図７（ｈ）の第２のスルー
ホールランド層５２上に表面実装部品（ＳＭＤ）５６を
載せ半田５４を用い、面付半田付した従来技術の模式断
面図であり、かつこの第２のスルーホールランド層５２
・５３は、ランド層領域５５として、幅広くスペースを
占有している状態を示すもので高密度実装化が難しい従
来技術に係る多層プリント配線板５９である。Next, FIG. 8 is a schematic sectional view of a prior art in which a surface mount component (SMD) 56 is mounted on the second through-hole land layer 52 of FIG. FIG.
Reference numeral 53 denotes a multilayer printed wiring board 59 according to the prior art, which indicates a state in which a large space is occupied as the land layer region 55 and high density mounting is difficult.
【００１２】[0012]
【発明が解決しようとする課題】しかしながら、上述の
従来技術では、高密度実装化及びスルーホールの小スペ
ース化等の構造において、以下のような問題点を有して
いた。However, the above-mentioned prior art has the following problems in a structure for high-density mounting and a small through-hole space.
【００１３】その第１としては、第２のスルーホールラ
ンド層５２・５３形成のために、表面実装部品５６用の
ランド層領域５５（図８参照のこと。）を幅広く確保す
る必要が生じ、小スペース化構造が難しく問題となって
いた。First, in order to form the second through-hole land layers 52 and 53, it is necessary to secure a wide land layer region 55 (see FIG. 8) for the surface mount component 56. It was difficult to reduce the space, which was a problem.
【００１４】その第２としては、高密度実装化におい
て、第２のスルーホール５０の小径化であるが第２の貫
通孔４７の孔径が約０．２〜０．３mmの範囲、銅張積層
板の厚み約２．０〜５．０mmの範囲でドリル孔明け、銅
めっき及び電極パターン、形成の製造技術において、実
用上限界であるため特別に工程を追加することにより工
数増加となり、また、表裏導通接続穴５０の電気的な接
続信頼性とにおいて問題となっていた。Secondly, in high-density mounting, the diameter of the second through hole 50 is reduced, but the diameter of the second through hole 47 is in the range of about 0.2 to 0.3 mm. In the production technology of drilling, copper plating and electrode pattern, formation in the range of the thickness of the board of about 2.0 to 5.0 mm, the man-hour is increased by adding a special process because it is a practical limit. There has been a problem in the electrical connection reliability of the front and back conductive connection holes 50.
【００１５】この発明は、上述の事情を鑑みてなされた
ものであり、その目的とするところは、スルーホールの
小スペース化及び高密度実装化に優れる多層プリント配
線板２７を提供することにある。The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a multilayer printed wiring board 27 which is excellent in reducing the space of through holes and achieving high-density mounting. .
【００１６】[0016]
【課題を解決するための手段】この発明の多層プリント
配線板２７は、内層のコア材４Ａに形成された導通接続
穴８（スルーホール）内に不導体入り絶縁性ペースト１
０を充填、形成し、この表裏面に片面銅張積層基材４Ｂ
・４Ｃを熱プレスを用い、加熱加圧し積層圧着１５・１
６して、多層の銅張積層材４を構成でき、次いで前記導
通接続穴８のｄ1よりも小さい径ｄ2の同芯円状に第２の
貫通孔１７を穿孔し、この孔１７内に耐熱導電性ペース
ト１８を充填して形成した貫通導電接続穴２６の表裏面
に第２の銅めっき１９・２０を施し、公知のエッチング
製造技術を用い、この穴２６上にランド層２１・２２を
形成でき、A multilayer printed wiring board 27 according to the present invention comprises an insulating paste 1 containing a non-conductor in a conductive connection hole 8 (through hole) formed in an inner core material 4A.
0, and a single-sided copper-clad laminated base material 4B
・ 4C is heated and pressurized using a hot press, and laminating and pressing 15 ・ 1
6, a multilayer copper-clad laminate 4 can be formed, and then a second through hole 17 is formed in a concentric shape with a diameter d 2 smaller than d 1 of the conductive connection hole 8. A second copper plating 19/20 is applied to the front and back surfaces of the through conductive connection holes 26 formed by filling the heat resistant conductive paste 18 with the heat resistant conductive paste 18, and the land layers 21/22 are formed on the holes 26 by a known etching manufacturing technique. Can form
【００１７】また前記内層に存在するブラインドバイア
ホール８に関係なく貫通導電接続穴２６を形成可能なた
め、設計の自由度向上化、小スペース化及び高密度実装
化しようとするものである。Further, since the through conductive connection hole 26 can be formed irrespective of the blind via hole 8 existing in the inner layer, it is intended to improve the degree of freedom of design, to reduce the space, and to achieve high-density mounting.
【００１８】[0018]
【発明の実施の形態】本発明の多層プリント配線板２７
において、内層のコア材４Ａに第１の貫通孔５を穿孔
し、第１の銅めっき層６・７を形成して、導通接続穴８
が得られ、この穴８に絶縁樹脂と不導体フィラーからな
る不導体入り絶縁性ペースト１０を充填、形成し、前記
導通接続穴８の径ｄ1よりも小さい径ｄ2で同芯円状に第
２の貫通孔１７をレーザー光を用い穿孔し、この孔１７
内に耐熱熱硬化性樹脂と導体フィラーからなる耐熱導電
性ペースト１８を充填し、形成した貫通導電接続穴２６
の表裏面に、第２の銅めっき層１９・２０を施し、この
穴２６上に表面実装部品２３用ランド層２１・２２を公
知のエッチング製造技術を用い形成できるので、従来技
術において、内層に存在するブラインドバイアホール３
８による第２のスルーホール５０形成の設計、自由度で
問題となり、また前記表面実装部品５６のランド層領域
５５が幅広く面積を占有する問題があり、これらの問題
点を本発明の多層プリント配線板２７は、充分に解決で
きるものである。DESCRIPTION OF THE PREFERRED EMBODIMENTS Multilayer printed wiring board 27 of the present invention
, A first through hole 5 is formed in an inner core material 4A to form first copper plating layers 6 and 7, and a conductive connection hole 8 is formed.
The hole 8 is filled with a non-conductor-containing insulating paste 10 made of an insulating resin and a non-conductive filler, and is formed into a concentric circle with a diameter d 2 smaller than the diameter d 1 of the conductive connection hole 8. The second through hole 17 is pierced using a laser beam,
Is filled with a heat-resistant conductive paste 18 composed of a heat-resistant thermosetting resin and a conductive filler, and formed through conductive connection holes 26.
The second copper plating layers 19 and 20 are formed on the front and back surfaces of the substrate, and the land layers 21 and 22 for the surface mount component 23 can be formed on the holes 26 by using a known etching manufacturing technique. Existing blind via hole 3
8 and the degree of freedom in the formation of the second through hole 50, and the land layer region 55 of the surface mount component 56 occupies a wide area, and these problems are solved by the multilayer printed wiring of the present invention. The plate 27 can be sufficiently solved.
【００１９】[0019]
【実施例】以下、本発明の実施例を示す、図１，図２
（ａ）〜（ｄ），図３（ｅ）〜（ｈ），図４（ｉ）に基
づいて、説明する。1 and 2 show an embodiment of the present invention.
A description will be given based on (a) to (d), FIGS. 3 (e) to (h), and FIG. 4 (i).
【００２０】[0020]
【実施例１】先ず、図２（ａ）は、銅箔１・２（厚１８
μｍ）と絶縁基板３（ＦＲ−４）からなるコア材４Ａで
ある。[Embodiment 1] First, FIG. 2A shows copper foils 1 and 2 (thickness 18).
μm) and an insulating substrate 3 (FR-4).
【００２１】次いで、図２（ｂ）は、コア材４Ａに選択
的に第１の貫通孔５をレーザー光及びドリルを使い穿孔
した。Next, in FIG. 2B, a first through hole 5 was selectively formed in the core material 4A using a laser beam and a drill.
【００２２】次いで、図２（ｃ）は、図２（ｂ）の第１
の貫通孔５の内壁に化学めっきと電気銅めっきを併用施
して、めっき厚２０．０〜２５μｍの範囲の第１の銅め
っき層６・７を形成した。Next, FIG. 2 (c) shows the first of FIG. 2 (b).
The first copper plating layers 6 and 7 having a plating thickness in the range of 20.0 to 25 μm were formed on the inner wall of the through hole 5 by using both chemical plating and electrolytic copper plating.
【００２３】次いで、図２（ｄ）に示すように、第１の
貫通孔５の孔内に印刷スクリーン版（９５０×９５０m
m）を用い、スキージを使い、不導体入り絶縁性ペース
ト１０を充填８０℃で仮乾燥し、これを１０kg／cm2の
加圧を行いペースト１０の充填密度をあげた。しかる後
に、この表裏面をベルト研磨機を使い平坦化後、乾燥炉
を用い本乾燥（１６０℃，５０分間）した。Next, as shown in FIG. 2D, a printing screen plate (950 × 950 m) is provided in the first through hole 5.
m), using a squeegee, fill the insulating paste 10 with a non-conductor and temporarily dry it at 80 ° C., and apply a pressure of 10 kg / cm 2 to increase the packing density of the paste 10. Thereafter, the front and back surfaces were flattened using a belt polishing machine, and then main-dried (160 ° C., 50 minutes) using a drying furnace.
【００２４】上記の不導体入り絶縁性ペースト１０は、
絶縁樹脂と不導体フィラーからなり、この絶縁樹脂と
は、例えば変性エポキシ樹脂，変性フェノール系樹脂，
変性ポリイミド樹脂（日立化成工業製商品名ＨＩ−Ｌ）
等であり、基板用途により、これらから選ばれる少なく
とも一つでよい。The insulating paste 10 containing a non-conductor is
It consists of an insulating resin and a non-conductive filler. The insulating resin is, for example, a modified epoxy resin, a modified phenol resin,
Modified polyimide resin (trade name HI-L, manufactured by Hitachi Chemical)
And at least one selected from these depending on the use of the substrate.
【００２５】また、上記の不導体フィラーとは、例え
ば、シリカ粉，タルク粉，ガラス粉末等であり、これら
から選ばれる少なくとも一つでよく、この平均粒径は、
５．０〜５０μｍの範囲とする。より好適な平均粒径
は、５．０〜３０μｍの範囲がよい。この粒径の形状は
球状とする。この粒径は５０μｍ越えると充填、印刷性
を阻害する。The non-conductive filler is, for example, silica powder, talc powder, glass powder, etc., and may be at least one selected from the foregoing.
The range is 5.0 to 50 μm. A more preferable average particle size is in the range of 5.0 to 30 μm. The shape of this particle size is spherical. If the particle size exceeds 50 μm, the filling and printability are impaired.
【００２６】また、上記の不導体入り絶縁性ペースト中
に含有する、不導体フィラー（シリカ粉）の量は、５０
〜９０wt％の範囲とし、残りが絶縁樹脂であり、より好
適な不導体フィラーの含有量は、８０〜９０wt％の範囲
である。また、上記の不導体フィラーの含有量が９０wt
％を越えると樹脂と不導体フィラーの密着性に悪影響を
及ぼし、５０wt％未満では、印刷充填性、経済性に不具
合が生じ、いずれも適してない。The amount of the non-conductive filler (silica powder) contained in the non-conductive insulating paste is 50%.
The content of the non-conductive filler is in the range of 80 to 90 wt%. In addition, the content of the non-conductive filler is 90 wt.
%, The adhesion between the resin and the non-conductive filler is adversely affected, and if it is less than 50% by weight, print filling property and economical efficiency are disadvantageous, and neither is suitable.
【００２７】次いで、図３（ｅ）に示すように、図２
（ｄ）コア材４Ａの表裏上に片面銅張積層基材４Ｂ・４
Ｃ（ＦＲ−４）を重ねて、熱プレスにより、加熱加圧
（温度１８０℃、圧力５０〜９０kg／cm2）を行い、積
層圧着１５・１６により、多層の銅張積層板４（ＦＲ−
４）を構成した。Next, as shown in FIG.
(D) Single-sided copper-clad laminated base materials 4B and 4 on the front and back of core material 4A
C (FR-4) is superposed, heated and pressurized (temperature 180 ° C., pressure 50 to 90 kg / cm 2 ) by a hot press, and a multilayer copper-clad laminate 4 (FR-
4) was constituted.
【００２８】次いで、図３（ｆ）に示すように、図３
（ｅ）の４に選択的に導通接続穴８の径ｄ1よりも小さ
い径ｄ2で同芯円状に第２の貫通孔１７をレーザー光及
びマイクロダイアモンドドリルを用い自動機で穿孔し
た。また、このレーザー光とは、例えば、公知の炭酸ガ
スレーザー，ＹＡＧレーザー，エキシマレーザー等であ
り、基材種類により上記のいずれか一つ選んで穿孔して
もよい。Next, as shown in FIG.
In (e) 4, the second through-hole 17 was concentrically formed with a diameter d 2 smaller than the diameter d 1 of the conductive connection hole 8 by a laser beam and a micro diamond drill by an automatic machine. The laser light is, for example, a known carbon dioxide gas laser, a YAG laser, an excimer laser, or the like, and any one of the above may be selected depending on the type of the base material and the perforation may be performed.
【００２９】また、この孔１７径は、０．０４〜０．４
mmの範囲で、より好適な孔１７径は０．１〜０．３mmの
範囲であり、上記の孔１７の内壁粗さを１０〜４０μｍ
の範囲で、より好適な孔１７内壁粗さは、２０〜４０μ
ｍの範囲で、この孔１７の内壁粗さが１０μｍ未満にな
ると耐熱導電性ペースト１８が孔１７の内壁に付着する
密着性を阻害することになり、孔１７の内壁粗さが４０
μｍを越えると第２の貫通孔１７の位置精度に不具合が
生じ、いずれも適しない。The diameter of the hole 17 is 0.04 to 0.4.
mm, the more preferable hole 17 diameter is in the range of 0.1 to 0.3 mm, and the inner wall roughness of the hole 17 is 10 to 40 μm.
The more preferable inner wall roughness of the hole 17 is 20 to 40 μm.
If the inner wall roughness of the hole 17 is less than 10 μm in the range of m, the adhesion of the heat-resistant conductive paste 18 to the inner wall of the hole 17 is impaired, and the inner wall roughness of the hole 17 becomes 40 μm.
If it exceeds μm, the positional accuracy of the second through-holes 17 will be inferior, and neither is suitable.
【００３０】次いで、図３（ｇ）に示すように、図３
（ｆ）の第２の貫通孔１７の孔内に印刷スクリーン版を
用い、スキージを使い、耐熱導電性ペースト１８を充填
し仮乾燥（８０℃）を行い、更に、この表裏孔２６上下
面にステンレス板にて１０〜５０kg／cm2加圧を行い上
記１８の充填密度を向上させ、しかる後、ベルト研磨機
を使い、１８の表面を平坦化後乾燥炉を用い、本乾燥
（１６０℃、６０分間）した。Next, as shown in FIG.
(F) Using a printing screen plate in the hole of the second through-hole 17, filling the heat-resistant conductive paste 18 with a squeegee and performing preliminary drying (80 ° C.). The pressure is increased by 10 to 50 kg / cm 2 with a stainless steel plate to improve the packing density of the above item 18. Thereafter, using a belt polishing machine, the surface of the item 18 is flattened, and then a drying oven is used. 60 minutes).
【００３１】上記の耐熱導電性ペースト１８とは、耐熱
熱硬化性樹脂と導体フィラーからなり、この耐熱熱硬化
性樹脂とは例えば、変性エポキシ樹脂，変性フェノール
系樹脂，変性ポリイミド樹脂（日立化成工業製，商品名
ＨＩ−Ｌ）で、これらから選ばれる少なくとも一つであ
ると耐熱面からより実用性に優れたものとなる。The heat-resistant conductive paste 18 comprises a heat-resistant thermosetting resin and a conductive filler. Examples of the heat-resistant thermosetting resin include a modified epoxy resin, a modified phenolic resin, and a modified polyimide resin (Hitachi Chemical Industries, Ltd.). Manufactured by HI-L), and if at least one selected from these is used, it becomes more practical in terms of heat resistance.
【００３２】また上記の導体フィラーとは、例えばパラ
ジウム粉，銅粉，ニッケル粉等で、これらの中の少なく
とも一つでよい。この平均粒径は、０．２〜５０μｍの
範囲で、より好適な粒径は１０〜３０μｍの範囲であり
上記の粒径５０μｍ越えると印刷性が阻害される。ま
た、この粒径の形状は球形状とする。The above-mentioned conductor filler is, for example, palladium powder, copper powder, nickel powder or the like, and at least one of them may be used. The average particle size is in the range of 0.2 to 50 μm, and the more preferable particle size is in the range of 10 to 30 μm. If the average particle size exceeds 50 μm, printability is impaired. The shape of the particle size is spherical.
【００３３】また、上記の導体フィラーの含有量は、５
０〜９６wt％の範囲で残りが耐熱熱硬化性樹脂となる。
より好ましい含有量は、６０〜９６wt％で、更に好適な
含有量は、８５〜９６wt％であると電気伝導性を高く保
持できる。The content of the conductor filler is 5
In the range of 0 to 96 wt%, the remainder is heat-resistant thermosetting resin.
The more preferable content is 60 to 96 wt%, and the more preferable content is 85 to 96 wt%, so that high electric conductivity can be maintained.
【００３４】また、導体フィラーの含有量が５０wt％未
満では化学めっきの析出性の劣化と十分な導電性が得ら
れなく、９６wt％を越えると耐熱熱硬化性樹脂と銅めっ
きの密着性が低下する悪影響を及ぼし、いずれも適して
ない。If the content of the conductive filler is less than 50 wt%, the deposition property of the chemical plating deteriorates and sufficient conductivity cannot be obtained, and if it exceeds 96 wt%, the adhesion between the heat-resistant thermosetting resin and the copper plating decreases. All of them are unsuitable.
【００３５】更に、導体フィラーの粒径における電気的
な接続性であるがこの平均粒径が５０μｍを越えると導
電性微粉間の接点が不足し導電性が低下し、０．２μｍ
未満では接触抵抗が増加し、導電性が低下し、いずれも
適してない。Further, regarding the electrical connectivity in terms of the particle size of the conductive filler, if the average particle size exceeds 50 μm, the contact between the conductive fine powders becomes insufficient and the conductivity decreases, and the conductivity decreases.
If it is less than 1, the contact resistance increases, the conductivity decreases, and neither is suitable.
【００３６】次いで、図３（ｈ）に示すように、図３
（ｇ）の表裏面に化学めっきと電気銅めっきを併用し、
厚さ２０μｍの第２の銅めっき層１９・２０を形成し
た。Next, as shown in FIG.
(G) Using both chemical plating and electrolytic copper plating on the front and back surfaces,
Second copper plating layers 19 and 20 having a thickness of 20 μm were formed.
【００３７】次いで、図４（ｉ）に示すように、公知の
写真法のエッチング製造技術によって貫通導電接続穴２
６上部が平坦なるランド層２１・２２と高密度なパター
ンが形成できた。Next, as shown in FIG. 4 (i), the through-holes 2 are formed by a known photolithographic etching manufacturing technique.
6 High-density patterns with land layers 21 and 22 having a flat upper part were formed.
【００３８】従って、上述の構成によるコア材４Ａに存
在する不導体入り絶縁性ペースト１０を充填された第１
の導通接続穴（スルーホール）８内に同芯円状で穴８径
ｄ1よりも小さい径ｄ2になる貫通導電接続穴２６を形成
できるため、ランド層２１・２２の小スペース化と設計
の自由度がより向上し、更に高密度の実装化が可能とな
る、本発明の多層プリント配線板２７を得ることができ
る。Accordingly, the first material filled with the non-conductor-containing insulating paste 10 existing in the core material 4A having the above-described configuration is used.
For possible conductive connection hole (through hole) through conducting connecting hole 26 has a decreasing diameter d 2 than the hole 8 diameter d 1 in the concentric circle within 8 formation, small space of the land layer 21 and 22 and the design The multi-layer printed wiring board 27 of the present invention can be obtained in which the degree of freedom is further improved and the mounting at a higher density is possible.
【００３９】次いで、図１に示すように、第１の導通接
続穴８の径ｄ1よりも小さい第２の貫通孔１７を同芯円
状に穿孔し、この第２の貫通孔１７の内壁に耐熱導電性
ペースト１８を充填、形成、しかる後に、第２の銅めっ
き層１９・２０を施し、公知のエッチング技術により、
電極パターンと貫通導電接続孔２６上のランド層２１・
２２を形成し、このランド層領域２５をより狭く構成で
き、このランド層２１上に表面実装部品２３（ＳＭＤ）
をクリーム半田２４を用い、接着した状態を示す本発明
の模式構造図である。Next, as shown in FIG. 1, a second through hole 17 smaller than the diameter d 1 of the first conductive connection hole 8 is formed concentrically, and an inner wall of the second through hole 17 is formed. Is filled with a heat-resistant conductive paste 18, and thereafter, the second copper plating layers 19 and 20 are applied.
Land layer 21 on electrode pattern and through conductive connection hole 26
22, the land layer region 25 can be configured to be narrower, and the surface mount component 23 (SMD) is formed on the land layer 21.
FIG. 2 is a schematic structural view of the present invention, showing a state where they are adhered using cream solder 24.
【００４０】次いで、以上、実施例の電食性、穴２
６上のランド層１９・２０と耐熱導電性ペースト層１８
の密着性と、接続信頼性を評価し、その結果を（表
１）を下記に記載する。Next, as described above, the electrolytic corrosion property, hole 2
6 and land layers 19 and 20 and heat-resistant conductive paste layer 18
Was evaluated for adhesion and connection reliability, and the results are shown in Table 1 below.
【００４１】表１に接続信頼性の評価を示す。Table 1 shows the evaluation of connection reliability.
【表１】 穴間にＤＣ５０Ｖを印加し、８５℃，８５％ＲＨで
１０００時間放置した後の絶縁抵抗値。 ２６０℃半田浴に２０秒浸漬、１０秒放置を３回く
り返した後穴（２６）断面を光学的に倍率４００倍にて
観察した。 ホットオイル試験（２６０℃オイル５秒浸漬、常温
水中５秒、浸漬を１サイクルとする）で第２の銅めっき
後抵抗値変化率１０％以上、上昇したサイクル数を不合
格とした。 供試数：各２０ピース[Table 1] Insulation resistance value after applying DC 50 V between the holes and leaving at 85 ° C. and 85% RH for 1000 hours. After being immersed in a 260 ° C. solder bath for 20 seconds and left for 10 seconds three times, the cross section of the hole (26) was optically observed at a magnification of 400 ×. In the hot oil test (immersion in oil at 260 ° C. for 5 seconds, in water at room temperature for 5 seconds, and immersion as one cycle), the rate of change in resistance value after the second copper plating was 10% or more, and the number of cycles that increased was rejected. Number of test: 20 pieces each
【００４２】表１から明らかなように、本発明の実施例
による多層プリント配線板２７は、従来技術にかかる多
層プリント配線板５９に比べ電気的な接続信頼性、密着
性等について、有意差のない実施例の構造である。As is clear from Table 1, the multilayer printed wiring board 27 according to the embodiment of the present invention has a significant difference in electrical connection reliability, adhesion and the like as compared with the multilayer printed wiring board 59 according to the prior art. There is no embodiment structure.
【００４３】なお、以上の説明では、第２の貫通孔１７
の内に耐熱導電性ペースト１８を充填、形成した貫通導
電接続穴２６の穴の上に、ランド層２１・２２を構成す
る例をとって説明したが、従来の技術の第２のスルーホ
ール５０の穴内に耐熱導電性ペースト１８を充填、形成
して、しかる後に第２のスルーホール５０の穴上に表面
実装部品２３を高密度実装化できるランド層２１・２２
の構成に適用することが可能である。In the above description, the second through hole 17
In the above description, the land layers 21 and 22 are formed on the through conductive connection holes 26 formed by filling and forming the heat-resistant conductive paste 18. Are filled and formed with heat-resistant conductive paste 18 and then land layers 21 and 22 are provided, on which the surface mount components 23 can be densely mounted on the holes of the second through holes 50.
It is possible to apply to the configuration of
【００４４】[0044]
（１）本発明によれば、コア材４Ａに存在する不導体入
り絶縁性ペースト１０を充填された第１の導通接続穴８
内に同芯円状に第１の導通接続穴８の径ｄ1よりも小さ
い径ｄ2の貫通導電接続穴２６を形成し穴２６上にラン
ド層２１・２２が形成できるため貫通導電接続穴２６の
ランド層領域２５の小スペース化と設計の自由度がより
向上でき、産業上寄与する効果は極めて大きい（図１参
照のこと。）。 （２）本発明によれば、第２の貫通孔１７の内壁に第２
の銅めっき層４８・４９を形成しなく、かつ、ＳＭＤ２
３用配線ランド層５２・５３を形成しないために、工程
短縮と材料費の低減が可能であり産業上寄与する効果は
大である（図１参照のこと。）。(1) According to the present invention, the first conductive connection hole 8 filled with the non-conductor-containing insulating paste 10 present in the core material 4A.
Through conductive connection hole for the first conductive connection hole land layer 21 and 22 through conductive connection hole 26 of smaller diameter d 2 than the diameter d 1 formed on the hole 26 of 8 coaxially circle can be formed within It is possible to further reduce the space in the land layer region 25 and improve the degree of freedom in design, and the effect of contributing to the industry is extremely large (see FIG. 1). (2) According to the present invention, the second through hole 17
No copper plating layers 48 and 49 are formed and SMD2
Since the third wiring land layers 52 and 53 are not formed, the process can be shortened and the material cost can be reduced, and the effect of contributing to the industry is great (see FIG. 1).
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明は一実施例の小スペース化したランド層
に表面実装部品を搭載（ＳＭＴ）した状態を示す模式断
面構造図。FIG. 1 is a schematic cross-sectional structural view showing a state in which a surface mount component is mounted (SMT) on a land layer having a reduced space according to an embodiment of the present invention.
【図２】（ａ）〜（ｄ）は、本発明の製造工程を示す断
面図。FIGS. 2A to 2D are cross-sectional views illustrating a manufacturing process of the present invention.
【図３】（ｅ）〜（ｈ）は、本発明の製造工程を示す断
面図。FIGS. 3 (e) to 3 (h) are cross-sectional views illustrating a manufacturing process of the present invention.
【図４】（ｉ）は、本発明の製造工程を示す断面図。FIG. 4 (i) is a cross-sectional view showing a manufacturing step of the present invention.
【図５】（ａ）〜（ｂ）は、従来技術の製造工程を示す
断面図。FIGS. 5A and 5B are cross-sectional views showing a manufacturing process of a conventional technique.
【図６】（ｃ）〜（ｆ）は、従来技術の製造工程を示す
断面図。FIGS. 6 (c) to 6 (f) are cross-sectional views showing a conventional manufacturing process.
【図７】（ｇ）〜（ｈ）は、従来技術の製造工程を示す
断面図。FIGS. 7 (g) to 7 (h) are cross-sectional views showing a manufacturing process of a conventional technique.
【図８】従来技術に係るプリント配線板に表面実装部品
を半田付した状態の領域を示す模式断面構造図。FIG. 8 is a schematic cross-sectional structure diagram showing a region where a surface mount component is soldered to a printed wiring board according to a conventional technique.
１，２…銅箔 ３…絶縁基板 ４…多層の銅張積層板 ４Ａ…コア材（ＦＲ−４） ４Ｂ，４Ｃ…片面銅張積層
基材 ５…第１の貫通孔 ６，７…第１の銅めっき層 ８…導通接続穴（スルーホール） １０…不導体入り絶
縁性ペースト １５，１６…積層圧着 １７…第２の貫通孔 １８…耐
熱導電性ペースト １９，２０…第２の銅めっき層 ２１，２２…穴上のラ
ンド層 ２３…表面実装部品 ２４…クリーム半田 ２５…ラン
ド層領域 ２６…貫通導電接続穴 ２７…本発明の多層プリント配
線板 ３１，３２…銅箔 ３３…絶縁基板 ３４…多層の銅張
積層板 ３４Ａ…コア材 ３５…第１の貫通孔 ３６，３７…第
１の銅めっき層 ３８…第１の導通接続穴（スルーホール） ３９Ａ，３９Ｂ…片面銅張積層基材 ４０…絶縁ペース
ト ４５，４６…積層圧着 ４７…第２の貫通孔 ４８，４
９…第２の銅めっき層 ５０…第２の導通接続穴（スルーホール） ５２，５３…第２のスルーホールランド層 ５４…半田
５５…ランド層領域 ５６…表面実装部品 ５９…従来の技術に係る多層プリ
ント配線板1, 2, copper foil 3, insulating board 4, multilayer copper-clad laminate 4A, core material (FR-4) 4B, 4C, single-sided copper-clad laminate 5, 5-first through hole 6, 7, ... first Copper plating layer 8: Conductive connection hole (through hole) 10: Insulating paste containing non-conductor 15, 16: Lamination crimping 17: Second through hole 18: Heat-resistant conductive paste 19, 20: Second copper plating layer 21, 22 ... land layer on the hole 23 ... surface mount component 24 ... cream solder 25 ... land layer region 26 ... penetrating conductive connection hole 27 ... multilayer printed wiring board of the present invention 31, 32 ... copper foil 33 ... insulating substrate 34 ... Multilayer copper-clad laminate 34A core material 35 first through hole 36, 37 first copper plating layer 38 first conductive connection hole (through hole) 39A, 39B single-sided copper-clad laminate 40 ... Insulating paste 45,46 ... Lamination pressure bonding 47 ... No. Of the through-hole 48,4
9: second copper plating layer 50: second conductive connection hole (through-hole) 52, 53: second through-hole land layer 54: solder 55: land layer region 56: surface mount component 59: conventional technology Such a multilayer printed wiring board
【手続補正書】[Procedure amendment]
【提出日】平成９年８月２９日[Submission date] August 29, 1997
【手続補正１】[Procedure amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】全文[Correction target item name] Full text
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【書類名】 明細書[Document Name] Statement
【発明の名称】 多層プリント配線板[Title of the Invention] Multilayer printed wiring board
【特許請求の範囲】[Claims]
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００２】[0002]
【従来の技術】近年、電子機器の軽薄短小化が急激に進
展中において、プリント配線板は、小型化，高密度実装
化すると、導通接続穴（スルーホール）の数が増加し、
設計上その配置とスペースが困難になっていた。また第
２の導通接続穴（スルーホール）５０は、３９Ａ，３９
Ｂに存在するブラインドバイアホールを避けて配置しな
ければならず設計上の制約となっていた。以下、従来技
術の製造工程について、図５（ａ）〜（ｂ）と、図６
（ｃ）〜（ｆ）と、図７（ｇ）〜（ｈ）と、図８に基づ
き、具体的に説明する。2. Description of the Related Art In recent years, as electronic devices have been rapidly becoming lighter and thinner, the number of conductive connection holes (through holes) has increased as printed wiring boards have become smaller and more densely mounted.
The layout and space were difficult by design. The second conductive connection holes (through holes) 50 are 39A, 39
B has to be arranged so as to avoid the blind via hole existing in B, which is a design constraint. Hereinafter, the manufacturing process of the conventional technique will be described with reference to FIGS.
A detailed description will be given based on (c) to (f), FIGS. 7 (g) to (h), and FIG.
【０００３】先ず、図５（ａ）に示すように、銅箔３１
・３２と絶縁基板３３からなる内層銅張積層板３４Ａで
ある。[0003] First, as shown in FIG.
An inner-layer copper-clad laminate 34 </ b> A composed of 32 and an insulating substrate 33.
【０００４】次いで、図５（ｂ）は、図５（ａ）の内層
銅張積層板３４Ａに第１の貫通孔３５をマイクロドリル
を用いて、穿孔する。Next, FIG. 5B shows an inner layer of FIG.
A first through hole 35 is formed in the copper-clad laminate 34A using a micro drill.
【０００７】次いで、図６（ｅ）に示すように、図６
（ｄ）の本硬化した絶縁ペースト４０表裏面に接着剤付
片面銅張積層基板３９Ａ・３９Ｂを熱プレスを用い加
熱、加圧により、積層圧着４５・４６し多層の銅張積層
板３４を構成する。Next, as shown in FIG.
(D) Fully cured insulating paste 40 with adhesive on front and back
The single-sided copper-clad laminated substrates 39A and 39B are laminated and pressure-bonded 45 and 46 by heating and pressing using a hot press to form a multilayer copper-clad laminate 34.
【００１４】その第２としては、高密度実装化におい
て、第２のスルーホール５０の小径化であるが第２の貫
通孔４７の孔径が約０．２〜０．３ｍｍの範囲、銅張積
層板の厚み約２．０〜５．０ｍｍの範囲でドリル孔明
け、銅めっき及び電極パターン、形成の製造技術におい
て、実用上限界であるため、特別に工程を追加すること
により、工数増加の原因になり、更に表裏導通接続穴５
０内の電気的な接続信頼性においても問題となってい
た。Secondly, in high-density mounting, the diameter of the second through hole 50 is reduced, but the diameter of the second through hole 47 is in the range of about 0.2 to 0.3 mm. drill drilling in the range of about the thickness of the plate 2.0 to 5.0 mm, the copper plating and the electrode pattern, in the formation of production technology, since it is practical limit, by adding a special process, the cause of man-hours increase It becomes, further the front and back conductive connecting hole 5
Even if electrical connection reliability smell in the 0 has been a problem.
【００１６】[0016]
【課題を解決するための手段】この発明の多層プリント
配線板２７は、内層銅張積層板４Ａに形成された導通接
続穴８（スルーホール）内に不導体入り絶縁性ペースト
１０を充填、形成し、この表裏面に接着剤付片面銅張積
層基板４Ｂ・４Ｃを熱プレスを用い、加熱加圧し積層圧
着１５・１６して、多層の銅張積層材４を構成でき、次
いで前記導通接続穴８の径ｄ１よりも小さい径ｄ２の同
芯円状に第２の貫通孔１７を穿孔し、この孔１７内に耐
熱導電性ペースト１８を充填して形成した貫通導電接続
穴２６の表裏面にダイレクト電気銅めっきを用い第２の
銅めっき１９・２０を施し、公知のフォトエッチング製
造技術を用い、この穴２６上にランド層２１・２２を形
成でき、In the multilayer printed wiring board 27 of the present invention, the conductive paste 8 (through hole) formed in the inner copper clad laminate 4A is filled with the insulating paste 10 containing a nonconductor. One sided copper clad laminate with adhesive on the front and back
Using the layer substrate 4B, 4C hot pressing, heating and pressing the laminated crimp 15, 16 to, can be configured clad laminate 4 multilayer, then the diameter d 1 smaller diameter d 2 than the conductive connection hole 8 puncturing the second through-hole 17 coaxially circular, use physician of the second direct copper electroplating on the front and back surfaces of the through conductive connection hole 26 formed by filling the heat conductive paste 18 into the hole 17 plated with copper 19, 20, using a known Fotoe etching fabrication technology, it can form a land layer 21 and 22 on the hole 26,
【００１７】また前記接着剤付片面銅張積層板４Ｂ・４
Ｃに存在するブラインドバイアホールに関係なく貫通導
電接続穴２６を形成可能なため、設計の自由度向上化、
小スペース化及び高密度実装化しようとするものであ
る。[0017] The single-sided copper-clad laminate 4B · 4 with before Symbol adhesive
Since the through conductive connection hole 26 can be formed irrespective of the blind via hole existing in C, the degree of freedom in design can be improved.
It is intended to reduce the space and increase the mounting density.
【００１８】[0018]
【発明の実施の形態】本発明の多層プリント配線板２７
において、内層銅張積層板４Ａに第１の貫通孔５を穿孔
し、ダイレクト電気銅めっきを用い、第１の銅めっき層
６・７を形成して、導通接続穴８が得られ、この穴８に
絶縁樹脂と不導体フィラーからなる不導体入り絶縁性ペ
ースト１０を充填、形成し、前記導通接続穴８の径ｄ１
よりも小さい径ｄ２で同芯円状に第２の貫通孔１７をレ
ーザー加工及びドリルを用い穿孔し、この孔１７内に耐
熱熱硬化性樹脂と導体フィラーからなる耐熱導電性ペー
スト１８を充填し、形成した貫通導電接続穴２６上の表
裏面に、ダイレクト電気銅めっきを用い、第２の銅めっ
き層１９・２０を施し、この穴２６上に表面実装部品２
３用ランド層２１・２２を公知のエッチング製造技術を
用い形成できるので、従来技術において、４Ｂ・４Ｃに
存在するブラインドバイアホールによる第２のスルーホ
ール５０形成の設計、自由度で問題となり、また前記表
面実装部品５６のランド層領域５５が幅広く面積を占有
する間題があり、これらの間題点を本発明の多層プリン
ト配線板２７は、充分に解決できるものである。DESCRIPTION OF THE PREFERRED EMBODIMENTS Multilayer printed wiring board 27 of the present invention
In (1), a first through-hole 5 is formed in the inner layer copper-clad laminate 4A, and first copper plating layers 6 and 7 are formed using direct electrolytic copper plating to obtain conductive connection holes 8. 8 is filled and formed with an insulating paste 10 containing a non-conductor comprising an insulating resin and a non-conductive filler, and the diameter d 1 of the conductive connection hole 8 is formed.
Les the second through-hole 17 coaxially circular with a small diameter d 2 than
Drilled with Za processing and drilling, in the front and back surfaces of the hole 17 was filled with heat conductive paste 18 made of a heat-thermosetting resin and the conductive filler, the formed on the through conductive connection hole 26, direct electrolytic copper plating , And second copper plating layers 19 and 20 are applied.
Since the 3 lands layer 21 and 22 can be formed using known etching fabrication technology, in the prior art, the 4B-4C
The second through hole 50 formed in the design according to the blind via hole that is present, a problem with flexibility, also has between problem to occupy the wide area land layer region 55 of the surface mounting component 56, these between problems point The multilayer printed wiring board 27 of the present invention can sufficiently solve the problem.
【００２０】[0020]
【実施例１】先ず、図２（ａ）は、銅箔１・２（厚１８
μｍ）と絶縁基板３（ＦＲ−４）からなる内層銅張積層
板４Ａであり、例えば、４Ａは低誘電率４．０材，ＭＣ
Ｌ−Ｅ−６７（ＬＤ）等である。 [Embodiment 1] First, FIG. 2A shows copper foils 1 and 2 (thickness 18).
[mu] m) and the insulating substrate 3 (FR-4) Tona Ru inner layer copper-clad laminate
Plate 4A , for example, 4A is a low dielectric constant 4.0 material, MC
LE-67 (LD) and the like.
【００２１】次いで、図２（ｂ）は、内層銅張積層板４
Ａに選択的に第１の貫通孔５をレーザー光及びドリルを
使い穿孔した。Next, FIG. 2B shows the inner copper-clad laminate 4
A was selectively drilled in the first through hole 5 using laser light and a drill.
【００２２】次いで、図２（ｃ）は、図２（ｂ）の第１
の貫通孔５の内壁にダイレクト電気銅めっきを用い、銅
めっき厚２０．０〜２５μｍの範囲の第１の銅めっき層
６・７を形成した。Next, FIG. 2 (c) shows the first of FIG. 2 (b).
With direct copper electroplating on the inner wall of the through-hole 5 of copper
The first copper plating layers 6.7 having a plating thickness of 20.0 to 25 μm were formed.
【００２５】また、上記の不導体フィラーとは、例え
ば、シリカ粉，タルク粉，ガラス粉末等であり、これら
から選ばれる少なくとも一つでよく、この平均粒径は、
５．０〜５０μｍの範囲とする。より好適な平均粒径
は、５．０〜３０μｍの範囲がよい。この粒径の形状は
球状かフレーク状とする。この粒径は５０μｍ越えると
充填、印刷性を阻害する。The non-conductive filler is, for example, silica powder, talc powder, glass powder, etc., and may be at least one selected from the foregoing.
The range is 5.0 to 50 μm. A more preferable average particle size is in the range of 5.0 to 30 μm. The shape of the particle size is spherical or flake . If the particle size exceeds 50 μm, the filling and printability are impaired.
【００２７】次いで、図３（ｅ）に示すように、図２
（ｄ）内層銅張積層板４Ａの表裏上に接着剤付片面銅張
積層基板４Ｂ・４Ｃ（ＦＲ−４）を重ねて、熱プレスに
より、加熱加圧（温度１８０℃、圧力５０〜９０ｋｇ／
ｃｍ２）を行い、積層圧着１５・１６により、多層の銅
張積層板４（ＦＲ−４）を構成した。Next, as shown in FIG.
(D) Single- sided copper-clad with adhesive on the front and back of inner layer copper-clad laminate 4A
The laminated substrates 4B and 4C (FR-4) are stacked and heated and pressurized (temperature 180 ° C, pressure 50 to 90 kg /
cm 2 ), and a multilayer copper-clad laminate 4 (FR-4) was formed by lamination and pressure bonding 15 and 16.
【００２８】次いで、図３（ｆ）に示すように、図３
（ｅ）の４に選択的に導通接続穴８の径ｄ１よりも小さ
い径ｄ２で同芯円状に第２の貫通孔１７をレーザー光及
びマイクロドリルを用い自動機で穿孔した。また、この
レーザー光とは、例えば、公知の炭酸ガスレーザー，Ｙ
ＡＧレーザー，エキシマレーザー等であり、基材種類に
より上記のいずれか一つ選んで穿孔してもよい。Next, as shown in FIG.
In (e) 4, the second through-hole 17 was concentrically formed with a diameter d 2 smaller than the diameter d 1 of the conductive connection hole 8 by a laser beam and a micro drill by an automatic machine. The laser light is, for example, a known carbon dioxide gas laser, Y
An AG laser, an excimer laser, or the like may be used, and any one of the above may be selected and perforated depending on the type of the base material.
【００３２】また上記の導体フィラーとは、例えばパラ
ジウム粉，銅粉，ニッケル粉等で、これらの中の少なく
とも一つでよい。この平均粒径は、０．２〜５０μｍの
範囲で、より好適な粒径は１０〜３０μｍの範囲であり
上記の粒径５０μｍ越えると印刷性が阻害される。ま
た、この粒径の形状は球形状かフレーク状とする。The above-mentioned conductor filler is, for example, palladium powder, copper powder, nickel powder or the like, and at least one of them may be used. The average particle size is in the range of 0.2 to 50 μm, and the more preferable particle size is in the range of 10 to 30 μm. If the average particle size exceeds 50 μm, printability is impaired. The shape of the particle size is spherical or flake .
【００３６】次いで、図３（ｈ）に示すように、図３
（ｇ）の表裏面にダイレクト電気銅めっきを用い、銅厚
さ２０μｍの第２の銅めっき層１９・２０を形成した。Next, as shown in FIG.
(G) Direct copper electroplating on both sides
It is to form a second copper plating layer 19, 20 of the 20 [mu] m.
【００３９】次いで、図１に示すように、第１の導通接
続穴８の径ｄ１よりも小さい第２の貫通孔１７を同芯円
状に穿孔し、この第２の貫通孔１７の内壁に耐熱導電性
ペースト１８を充填、形成、しかる後に、第２の銅めっ
き層１９・２０を施し、公知のエッチング技術により、
電極パターンと貫通導電接続孔２６上のランド層２１・
２２を形成し、このランド層領城２５をより狭く構成で
き、このランド層２１上に表面実装部品２３（ＳＭＤ）
をクリーム半田２４を用い、半田付した状態を示す本発
明の模式構造図である。Next, as shown in FIG. 1, a second through hole 17 smaller than the diameter d1 of the first conductive connection hole 8 is formed in a concentric circle, and an inner wall of the second through hole 17 is formed. Is filled with a heat-resistant conductive paste 18, and thereafter, the second copper plating layers 19 and 20 are applied.
Land layer 21 on electrode pattern and through conductive connection hole 26
22, the land layer castle 25 can be configured to be narrower, and the surface mount component 23 (SMD) is formed on the land layer 21.
FIG. 2 is a schematic structural view of the present invention showing a state where the soldering is performed using cream solder 24.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明は一実施例の小スペース化したランド層
に表面実装部品を搭載（ＳＭＴ）した状態を示す模式断
面構造図。FIG. 1 is a schematic cross-sectional structural view showing a state in which a surface mount component is mounted (SMT) on a land layer having a reduced space according to an embodiment of the present invention.
【図２】（ａ）〜（ｄ）は、本発明の製造工程を示す断
面図。FIGS. 2A to 2D are cross-sectional views illustrating a manufacturing process of the present invention.
【図３】（ｅ）〜（ｈ）は、本発明の製造工程を示す断
面図。FIGS. 3 (e) to 3 (h) are cross-sectional views illustrating a manufacturing process of the present invention.
【図４】（ｉ）は、本発明の製造工程を示す断面図。FIG. 4 (i) is a cross-sectional view showing a manufacturing step of the present invention.
【図５】（ａ）〜（ｂ）は、従来技術の製造工程を示す
断面図。FIGS. 5A and 5B are cross-sectional views showing a manufacturing process of a conventional technique.
【図６】（ｃ）〜（ｆ）は、従来技術の製造工程を示す
断面図。FIGS. 6 (c) to 6 (f) are cross-sectional views showing a conventional manufacturing process.
【図７】（ｇ）〜（ｈ）は、従来技術の製造工程を示す
断面図。FIGS. 7 (g) to 7 (h) are cross-sectional views showing a manufacturing process of a conventional technique.
【図８】従来技術に係るプリント配線板に表面実装部品
を半田付した状態の領域を示す模式断面構造図。FIG. 8 is a schematic cross-sectional structure diagram showing a region where a surface mount component is soldered to a printed wiring board according to a conventional technique.
【符号の説明】 １，２…銅箔 ３…絶縁基板 ４…多層の銅張積層板
４Ａ…内層銅張積層板 ４Ｂ，４Ｃ…接着剤付片面銅張積層基板 ５…第１の貫
通孔 ６，７…第１の銅めっき層 ８…導通接続穴（スルーホ
ール） １０…不導体入り絶縁性ペースト １５，１６…積層圧
着 １７…第２の貫通孔 １８…耐熱導電性ペースト １９，２０…第２の銅めっき層 ２１，２２…穴上のラ
ンド層 ２３…表面実装部品 ２４…クリーム半田 ２５…ラン
ド層領域 ２６…貫通導電接続穴 ２７…本発明の多層プリント配
線板 ３１，３２…銅箔 ３３…絶縁基板 ３４…多層の銅張
積層板 ３４Ａ…内層銅張積層板 ３５…第１の貫通孔 ３６，３７…第１の銅めっき層 ３８…第１の導通接続
穴（スルーホール） ３９Ａ，３９Ｂ…接着剤付片面銅張積層基板 ４０…絶
縁ペースト ４５，４６…積層圧着 ４７…第２の貫通孔 ４８，４
９…第２の銅めっき層 ５０…第２の導通接続穴（スルーホール） ５２，５３…第２のスルーホールランド層 ５４…半田
５５…ランド層領域 ５６…表面実装部品 ５９…従来の技術に係る多層プリ
ント配線板 ─────────────────────────────────────────────────────
[Description of Signs] 1,2 ... Copper foil 3 ... Insulating substrate 4 ... Multilayer copper-clad laminate
4A: inner-layer copper-clad laminate 4B, 4C : single-sided copper-clad laminate with adhesive 5: first through hole 6, 7: first copper plating layer 8: conductive connection hole (through hole) 10: non-conductor-containing Insulating paste 15, 16 ... Lamination crimping 17 ... Second through hole 18 ... Heat resistant conductive paste 19,20 ... Second copper plating layer 21,22 ... Land layer on hole 23 ... Surface mount component 24 ... Cream solder 25 land layer area 26 through conductive connection hole 27 multilayer printed wiring board of the present invention 31, 32 copper foil 33 insulating board 34 multilayer copper clad laminate 34A inner copper clad laminate 35 first Through holes 36, 37: First copper plating layer 38: First conductive connection holes (through holes) 39A, 39B : Single- sided copper-clad laminate 40 with adhesive 40: Insulating paste 45, 46 ... Lamination crimping 47: Second Through-hole 48,4
9: second copper plating layer 50: second conductive connection hole (through-hole) 52, 53: second through-hole land layer 54: solder 55: land layer region 56: surface mount component 59: conventional technology Such a multilayer printed wiring board ───────────────────────────────────────────── ────────
【手続補正書】[Procedure amendment]
【提出日】平成９年１０月２４日[Submission date] October 24, 1997
【手続補正１】[Procedure amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】全文[Correction target item name] Full text
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【書類名】 明細書[Document Name] Statement
【発明の名称】 多層プリント配線板[Title of the Invention] Multilayer printed wiring board
【特許請求の範囲】[Claims]
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】本発明はプリント配線板の高
密度実装化及びスルーホールの小スペース化に係る構造
に関するものである。[0001] 1. Field of the Invention [0002] The present invention relates to a structure for achieving high-density mounting of a printed wiring board and reducing the space for through holes.
【０００２】[0002]
【従来の技術】近年、電子機器の軽薄短小化が急激に進
展中において、プリント配線板は、小型化，高密度実装
化すると、導通接続穴（スルーホール）の数が増加し、
設計上その配置とスペースが困難になっていた。また第
２の導通接続穴（スルーホール）５０は、３９Ａ，３９
Ｂに存在するブラインドバイアホールを避けて配置しな
ければならず設計上の制約となっていた。以下、従来技
術の製造工程について、図５（ａ）〜（ｂ）と、図６
（ｃ）〜（ｆ）と、図７（ｇ）〜（ｈ）と、図８に基づ
き、具体的に説明する。2. Description of the Related Art In recent years, as electronic devices have been rapidly becoming lighter and thinner, the number of conductive connection holes (through holes) has increased as printed wiring boards have become smaller and more densely mounted.
The layout and space were difficult by design. The second conductive connection holes (through holes) 50 are 39A, 39
Has been a constraint on the design must be arranged so as to avoid the blind by via holes that exist in B. Hereinafter, the manufacturing process of the conventional technique will be described with reference to FIGS.
A detailed description will be given based on (c) to (f), FIGS. 7 (g) to (h), and FIG.
【０００３】先ず、図５（ａ）に示すように、銅箔３１
・３２と絶縁基板３３からなる内層銅張積層板３４Ａで
ある。[0003] First, as shown in FIG.
- 32 there <br/> an insulating substrate 33 Tona Ru inner layer copper-clad laminate 34A.
【０００４】次いで、図５（ｂ）は、図５（ａ）の内層
銅張積層板３４Ａに第１の貫通孔３５をマイクロドリル
を用いて、穿孔する。Next, FIG. 5B shows an inner layer of FIG.
A first through hole 35 is formed in the copper-clad laminate 34A by using a micro drill.
【０００５】次いで、図６（ｃ）に示すように、図５
（ｂ）に化学めっきと電気銅めっきを併用施し、第１の
銅めっき層３６・３７を形成し、表裏導体接続の導通接
続穴３８（スルーホール）が得られる。[0005] Next, as shown in FIG.
In (b), chemical plating and electrolytic copper plating are performed in combination to form first copper plating layers 36 and 37, and a conductive connection hole 38 (through hole) for front and back conductor connection is obtained.
【０００６】次いで、図６（ｄ）は、図６（ｃ）の導通
接続穴３８内に熱硬化性の絶縁ペースト４０をスクリー
ン版の印刷スキージを用いて、充填し、仮乾燥、平坦化
して、約１７０℃、４０分間乾燥炉を用い本硬化する。Next, FIG. 6 (d) shows that the thermosetting insulating paste 40 is filled in the conductive connection hole 38 of FIG. 6 (c) by using a screen printing squeegee, temporarily dried and flattened. Full curing using a drying oven at about 170 ° C. for 40 minutes.
【０００７】次いで、図６（ｅ）に示すように、図６
（ｄ）の本硬化した絶縁ペースト４０表裏面に接着剤付
片面銅張積層基板３９Ａ・３９Ｂを熱プレスを用い加
熱、加圧により、積層圧着４５・４６し多層の銅張積層
板３４を構成する。Next, as shown in FIG.
(D) Fully cured insulating paste 40 with adhesive on front and back
The single-sided copper-clad laminates 39A and 39B are heated and pressed using a hot press to laminate and press-bond 45 and 46 to form a multilayer copper-clad laminate 34.
【０００８】次いで、図６（ｆ）は、図６（ｅ）の多層
の銅張積層板３４に、マイクロドリルを用い、第１の導
通接続穴３８の径（ｄ１）よりも小さい径（ｄ２）で第
２の貫通孔４７を穿孔する。Next, FIG. 6F shows a diameter (d 1 ) smaller than the diameter (d 1 ) of the first conductive connection hole 38 using a micro drill on the multilayer copper-clad laminate 34 of FIG. 6E. At d 2 ), the second through hole 47 is formed.
【０００９】次いで、図７（ｇ）に示すように、図６
（ｆ）の第２の貫通孔４７内壁に、化学めっきと電気銅
めっきを併用施し、第２の銅めっき層４８・４９を形成
し、表裏導体を接続する第２の導通接続穴５０（スルー
ホール）を形成する。Next, as shown in FIG.
2F, chemical plating and copper electroplating are simultaneously applied to the inner wall of the second through hole 47 to form second copper plating layers 48 and 49, and the second conductive connection hole 50 (through hole) for connecting the front and back conductors. Holes).
【００１０】更に、図７（ｈ）は、公知のエッチング製
造技術を用いて、電極パターン及び第２のスルーホール
ランド層５２・５３を形成でき得る従来技術の多層プリ
ント配線板５９である。FIG. 7 (h) shows a prior art multilayer printed wiring board 59 in which an electrode pattern and second through-hole land layers 52 and 53 can be formed using a known etching manufacturing technique.
【００１１】次に、図８は、図７（ｈ）の第２のスルー
ホールランド層５２上に表面実装部品（ＳＭＤ）５６を
載せ半田５４を用い、面付半田付した従来技術の模式断
面図であり、かつこの第２のスルーホールランド層５２
・５３は、ランド層領域５５として、幅広くスペースを
占有している状態を示すもので高密度実装化が難しい従
来技術に係る多層プリント配線板５９である。Next, FIG. 8 is a schematic sectional view of a prior art in which a surface mount component (SMD) 56 is mounted on the second through-hole land layer 52 of FIG. FIG.
Reference numeral 53 denotes a multilayer printed wiring board 59 according to the prior art, which indicates a state in which a large space is occupied as the land layer region 55 and high density mounting is difficult.
【００１２】[0012]
【発明が解決しようとする課題】しかしながら、上述の
従来技術では、高密度実装化及びスルーホールの小スペ
ース化等の構造において、以下のような問題点を有して
いた。However, the above-mentioned prior art has the following problems in a structure for high-density mounting and a small through-hole space.
【００１３】その第１としては、第２のスルーホールラ
ンド層５２・５３形成のために、表面実装部品５６用の
ランド層領域５５（図８参照のこと。）を幅広く確保す
る必要が生じ、小スペース化構造が難しく問題となって
いた。First, in order to form the second through-hole land layers 52 and 53, it is necessary to secure a wide land layer region 55 (see FIG. 8) for the surface mount component 56. It was difficult to reduce the space, which was a problem.
【００１４】その第２としては、高密度実装化におい
て、第２のスルーホール５０の小径化であるが第２の貫
通孔４７の孔径が約０．２〜０．３ｍｍの範囲、銅張積
層板の厚み約２．０〜５．０ｍｍの範囲でドリル孔明
け、銅めっき及び電極パターン、形成の製造技術におい
て、実用上限界であるため特別に工程を追加することに
より、工数増加の原因になり、更に表裏導通接続穴５０
内の電気的な接続信頼性において問題となっていた。Secondly, in high-density mounting, the diameter of the second through hole 50 is reduced, but the diameter of the second through hole 47 is in the range of about 0.2 to 0.3 mm. drill drilling in the range of about the thickness of the plate 2.0 to 5.0 mm, the copper plating and the electrode pattern, in the formation of production techniques, by adding a special process for a practical limit, steps up the cause of the pressure And the front and back conductive connection holes 50
It has been a problem in the gas connection reliability power of the internal.
【００１５】この発明は、上述の事情を鑑みてなされた
ものであり、その目的とするところは、スルーホールの
小スペース化及び高密度実装化に優れる多層プリント配
線板２７を提供することにある。The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a multilayer printed wiring board 27 which is excellent in reducing the space of through holes and achieving high-density mounting. .
【００１６】[0016]
【課題を解決するための手段】この発明の多層プリント
配線板２７は、内層銅張積層板４Ａに形成された導通接
続穴８（スルーホール）内に不導体入り絶縁性ペースト
１０を充填、形成し、この表裏面に接着剤付片面銅張積
層基板４Ｂ・４Ｃを熱プレスを用い、加熱加圧し積層圧
着１５・１６して、多層の銅張積層材４を構成でき、次
いで前記導通接続穴８の径ｄ１ よりも小さい径ｄ２の同
芯円状に第２の貫通孔１７を穿孔し、この孔１７内に耐
熱導電性ペースト１８を充填して形成した貫通導電接続
穴２６の表裏面にダイレクト電気銅めっきを用い第２の
銅めっき１９・２０を施し、公知のフォトエッチング製
造技術を用い、この穴２６上にランド層２１・２２を形
成でき、In the multilayer printed wiring board 27 of the present invention, the conductive paste 8 (through hole) formed in the inner copper clad laminate 4A is filled with the non-conductive insulating paste 10 and formed. Then, on the front and back , one side copper-clad with adhesive
Using heat pressing a layer substrate 4B, 4C, heating and pressing the laminated crimp 15, 16 to, can configure a multilayer copper-clad laminate 4, then the conducting contact smaller diameter d 2 than the diameter d 1 of the connection hole 8 A second through hole 17 is formed in a concentric circle, and a heat conductive paste 18 is filled in the hole 17 to form a through conductive connection hole 26 on the front and back surfaces of the second through hole 17 using direct electrolytic copper plating. plated with copper 19, 20, using a known Fotoe etching fabrication technology, it can form a land layer 21 and 22 on the hole 26,
【００１７】また前記接着剤付片面銅張積層板４Ｂ・４
Ｃに存在するブラインドバイアホールに関係なく貫通導
電接続穴２６を形成可能なため、設計の自由度向上化、
小スペース化及び高密度実装化しようとするものであ
る。The single-sided copper-clad laminate 4B
Since the through conductive connection hole 26 can be formed irrespective of the blind via hole existing in C , the degree of freedom in design can be improved.
It is intended to reduce the space and increase the mounting density.
【００１８】[0018]
【発明の実施の形態】本発明の多層プリント配線板２７
において、内層銅張積層板４Ａに第１の貫通孔５を穿孔
し、ダイレクト電気銅めっきを用い、第１の銅めっき層
６・７を形成して、導通接続穴８が得られ、この穴８に
絶縁樹脂と不導体フィラーからなる不導体入り絶縁性ペ
ースト１０を充填、形成し、前記導通接続穴８の径ｄ１
よりも小ざい径ｄ２で同芯円状に第２の貫通孔１７をレ
ーザー加工及びドリルを用い穿孔し、この孔１７内に耐
熱熱硬化性樹脂と導体フィラーからなる耐熱導電性ペー
スト１８を充填し、形成した貫通導電接続穴２６上の表
裏面に、ダイレクト電気銅めっきを用い、第２の銅めっ
き層１９・２０を施し、この穴２６上に表面実装部品２
３用ランド層２１・２２を公知のエッチング製造技術を
用い形成できるので、従来技術において、４Ｂ・４Ｃに
存在するブラインドバイアホールによる第２のスルーホ
ール５０形成の設計、自由度で問題となり、また前記表
面実装部品５６のランド層領域５５が幅広く面積を占有
する間題があり、これらの問題点を本発明の多層プリン
ト配線板２７は、充分に解決できるものである。DESCRIPTION OF THE PREFERRED EMBODIMENTS Multilayer printed wiring board 27 of the present invention
In, drilled a first through-hole 5 in the inner layer copper-clad laminate 4A, with-out direct electrolytic copper plating, to form a first copper plating layer 6, 7, conductive connection hole 8 is obtained, the non-conductor-containing insulating paste 10 made of an insulating resin and non-conductive filler into the hole 8 filled and formed, the diameter d 1 of the conductive connecting hole 8
Les the second through-hole 17 coaxially circular small goods diameter d 2 than
Za processing and have drilling use the drilling, the front and back surfaces of the hole 17 was filled with heat conductive paste 18 made of a heat-thermosetting resin and the conductive filler, the formed on the through conductive connection hole 26, direct copper a plating, subjected to the second copper plating layer 19, 20, the surface mounting component 2 on the hole 26
Since the 3 lands layer 21 and 22 can be formed using known etching fabrication technology, in the prior art, the 4B-4C
There is a problem in the design and freedom of the formation of the second through hole 50 by the existing blind via hole, and there is a problem that the land layer region 55 of the surface mount component 56 occupies a wide area. The multilayer printed wiring board 27 of the present invention can sufficiently solve the problem.
【００１９】[0019]
【実施例】以下、本発明の実施例を示す、図１，図２
（ａ）〜（ｄ），図３（ｅ）〜（ｈ），図４（ｉ）に基
づいて、説明する。1 and 2 show an embodiment of the present invention.
A description will be given based on (a) to (d), FIGS. 3 (e) to (h), and FIG. 4 (i).
【００２０】[0020]
【実施例１】先ず、図２（ａ）は、銅箔１・２（厚１８
μｍ）と絶縁基板３（ＦＲ−４）からなる内層銅張積層
板４Ａであり、例えば、４Ａは低誘電率４．０材，ＭＣ
Ｌ−Ｅ−６７（ＬＤ）等である。[Embodiment 1] First, FIG. 2A shows copper foils 1 and 2 (thickness 18).
[mu] m) and the insulating substrate 3 (FR-4) Tona Ru inner layer copper-clad laminate
Plate 4A , for example, 4A is a low dielectric constant 4.0 material, MC
LE-67 (LD) and the like .
【００２１】次いで、図２（ｂ）は、内層銅張積層板４
Ａに選択的に第１の貫通孔５をレーザー光及びドリルを
使い穿孔した。Next, FIG. 2B shows the inner copper-clad laminate 4
A was selectively drilled in the first through hole 5 using laser light and a drill.
【００２２】次いで、図２（ｃ）は、図２（ｂ）の第１
の貫通孔５の内壁にダイレクト電気銅めっきを用い、銅
めっき厚２０．０〜２５μｍの範囲の第１の銅めっき層
６・７を形成した。Next, FIG. 2 (c) shows the first of FIG. 2 (b).
With direct copper electroplating on the inner wall of the through-hole 5 of copper
Plating thickness20. The first copper plating layers 6.7 in the range of 0 to 25 μm were formed.
【００２３】次いで、図２（ｄ）に示すように、第１の
貫通孔５の孔内に印刷スクリーン版（９５０×９５０ｍ
ｍ）を用い、スキージを使い、不導体入り絶縁性ペース
ト１０を充填８０℃で仮乾燥し、これを１０ｋｇ／ｃｍ
２の加圧を行いペースト１０の充填密度をあげた。しか
る後に、この表裏面をベルト研磨機を使い平坦化後、乾
燥炉を用い本乾燥（１６０℃，５０分間）した。Next, as shown in FIG. 2D, a printing screen plate (950 × 950 m) is provided in the first through hole 5.
m), using a squeegee, fill the insulating paste 10 with a non-conductor and temporarily dry at 80 ° C.
2 was pressed to increase the packing density of the paste 10. Thereafter, the front and back surfaces were flattened using a belt polishing machine, and then main-dried (160 ° C., 50 minutes) using a drying furnace.
【００２４】上記の不導体入り絶縁性ペースト１０は、
絶縁樹脂と不導体フィラーからなり、この絶縁樹脂と
は、例えば変性エポキシ樹脂，変性フェノール系樹脂，
変性ポリイミド樹脂（日立化成工業製商品名ＨＩ−Ｌ）
等であり、基板用途により、これらから選ばれる少なく
とも一つでよい。The insulating paste 10 containing a non-conductor is
It consists of an insulating resin and a non-conductive filler. The insulating resin is, for example, a modified epoxy resin, a modified phenol resin,
Modified polyimide resin (trade name HI-L, manufactured by Hitachi Chemical)
And at least one selected from these depending on the use of the substrate.
【００２５】また、上記の不導体フィラーとは、例え
ば、シリカ粉，タルク粉，ガラス粉末等であり、これら
から選ばれる少なくとも一つでよく、この平均粒径は、
５．０〜５０μｍの範囲とする。より好適な平均粒径
は、５．０〜３０μｍの範囲がよい。この粒径の形状は
球状かフレーク状とする。この粒径は５０μｍ越えると
充填、印刷性を阻害する。The non-conductive filler is, for example, silica powder, talc powder, glass powder, etc., and may be at least one selected from the foregoing.
The range is 5.0 to 50 μm. A more preferable average particle size is in the range of 5.0 to 30 μm. The shape of the particle size shall be the spherical or flake form. If the particle size exceeds 50 μm, the filling and printability are impaired.
【００２６】また、上記の不導体入り絶縁性ペースト中
に含有する、不導体フィラー（シリカ粉）の量は、５０
〜９０ｗｔ％の範囲とし、残りが絶縁樹脂であり、より
好適な不導体フィラーの含有量は、８０〜９０ｗｔ％の
範囲である。また、上記の不導体フィラーの含有量が９
０ｗｔ％を越えると樹脂と不導体フィラーの密着性に悪
影響を及ぼし、５０ｗｔ％未満では、印刷充填性、経済
性に不具合が生じ、いずれも適してない。The amount of the non-conductive filler (silica powder) contained in the non-conductive insulating paste is 50%.
The content of the non-conductive filler is in the range of 80 to 90 wt%. When the content of the non-conductive filler is 9
If it exceeds 0% by weight, the adhesion between the resin and the non-conductive filler is adversely affected, and if it is less than 50% by weight, there is a problem in print filling property and economic efficiency, and neither is suitable.
【００２７】次いで、図３（ｅ）に示すように、図２
（ｄ）内層銅張積層板４Ａの表裏上に接着剤付片面銅張
積層基板４Ｂ・４Ｃ（ＦＲ−４）を重ねて、熱プレスに
より、加熱加圧（温度１８０℃、圧力５０〜９０ｋｇ／
ｃｍ２）を行い、積層圧着１５・１６により、多層の銅
張積層板４（ＦＲ−４）を構成した。Next, as shown in FIG.
( D) Single- sided copper-clad with an adhesive on the front and back of inner layer copper-clad laminate 4A
The laminated substrates 4B and 4C (FR-4) are stacked and heated and pressurized (temperature 180 ° C., pressure 50 to 90 kg /
cm 2 ), and a multilayer copper-clad laminate 4 (FR-4) was formed by lamination and pressure bonding 15 and 16.
【００２８】次いで、図３（ｆ）に示すように、図３
（ｅ）の４に選択的に導通接続穴８の径ｄ１よりも小さ
い径ｄ２で同芯円状に第２の貫通孔１７をレーザー光及
びマイクロドリルを用い自動機で穿孔した。また、この
レーザー光とは、例えば、公知の炭酸ガスレーザー，Ｙ
ＡＧレーザー，エキシマレーザー等であり、基材種類に
より上記のいずれか一つ選んで穿孔してもよい。Next, as shown in FIG.
(E) 4 to the second through-hole 17 with a laser beam及a small diameter d 2 than the diameter d 1 of the selectively conductive connecting hole 8 concentrically circular
It was perforated with automatic machines have use a fine micro drill. The laser light is, for example, a known carbon dioxide gas laser, Y
An AG laser, an excimer laser, or the like may be used, and any one of the above may be selected and perforated depending on the type of the base material.
【００２９】また、この孔１７径は、０．０４〜０．４
ｍｍの範囲で、より好適な孔１７径は０．１〜０．３ｍ
ｍの範囲であり、上記の孔１７の内壁粗さを１０〜４０
μｍの範囲で、より好適な孔１７内壁粗さは、２０〜４
０μｍの範囲で、この孔１７の内壁粗さが１０μｍ末満
になると耐熱導電性ペースト１８が孔１７の内壁に付着
する密着性を阻害することになり、孔１７の内壁粗さが
４０μｍを越えると第２の貫通孔１７の位置精度に不具
合が生じ、いずれも適しない。The diameter of the hole 17 is 0.04 to 0.4.
mm, the more preferable diameter of the hole 17 is 0.1 to 0.3 m.
m, and the inner wall roughness of the hole 17 is 10 to 40.
In the range of μm, more preferable inner wall roughness of the hole 17 is 20 to 4
If the inner wall roughness of the hole 17 is less than 10 μm in the range of 0 μm, the adhesion of the heat-resistant conductive paste 18 to the inner wall of the hole 17 is impaired, and the inner wall roughness of the hole 17 exceeds 40 μm. And the positional accuracy of the second through hole 17 is disadvantageous, and both are not suitable.
【００３０】次いで、図３（ｇ）に示すように、図３
（ｆ）の第２の貫通孔１７の孔内に印刷スクリーン版を
用い、スキージを使い、耐熱導電性ペースト１８を充填
し仮乾燥（８０℃）を行い、更に、この表裏孔２６上下
面にステンレス板にて１０〜５０ｋｇ／ｃｍ２加圧を行
い上記１８の充填密度を向上させ、しかる後、ベルト研
磨機を使い、１８の表面を平坦化後乾燥炉を用い、本乾
燥（１６０℃、６０分間）した。Next, as shown in FIG.
(F) Using a printing screen plate in the hole of the second through-hole 17, filling the heat-resistant conductive paste 18 with a squeegee and performing preliminary drying (80 ° C.). The pressure is increased by 10 to 50 kg / cm 2 with a stainless steel plate to improve the packing density of the above item 18; 60 minutes).
【００３１】上記の耐熱導電性ペースト１８とは、耐熱
熱硬化性樹脂と導体フィラーからなり、この耐熱熱硬化
性樹脂とは例えば、変性エポキシ樹脂，変性フェノール
系樹脂，変性ポリイミド樹脂（日立化成工業製，商品名
ＨＩ−Ｌ）で、これらから選ばれる少なくとも一つであ
ると耐熱面からより実用性に優れたものとなる。The heat-resistant conductive paste 18 comprises a heat-resistant thermosetting resin and a conductive filler. Examples of the heat-resistant thermosetting resin include a modified epoxy resin, a modified phenolic resin, and a modified polyimide resin (Hitachi Chemical Industries, Ltd.). Manufactured by HI-L), and if at least one selected from these is used, it becomes more practical in terms of heat resistance.
【００３２】また上記の導体フィラーとは、例えばパラ
ジウム粉，銅粉，ニッケル粉等で、これらの中の少なく
とも一つでよい。この平均粒径は、０．２〜５０μｍの
範囲で、より好適な粒径は１０〜３０μｍの範囲であり
上記の粒径５０μｍ越えると印刷性が阻害される。ま
た、この粒径の形状は球形状かフレーク状とする。The above-mentioned conductor filler is, for example, palladium powder, copper powder, nickel powder or the like, and at least one of them may be used. The average particle size is in the range of 0.2 to 50 μm, and the more preferable particle size is in the range of 10 to 30 μm. If the average particle size exceeds 50 μm, printability is impaired. The shape of the particle size shall be the spherical or flaky.
【００３３】また、上記の導体フィラーの含有量は、５
０〜９６ｗｔ％の範囲で残りが耐熱熱硬化性樹脂とな
る。より好ましい含有量は、６０〜９６ｗｔ％で、更に
好適な含有量は、８５〜９６ｗｔ％であると電気伝導性
を高く保持できる。The content of the conductor filler is 5
In the range of 0 to 96 wt%, the remainder is heat-resistant thermosetting resin. A more preferable content is 60 to 96 wt%, and a still more preferable content is 85 to 96 wt%, so that high electric conductivity can be maintained.
【００３４】また、導体フィラーの含有量が５０ｗｔ％
未満では化学めっきの析出性の劣化と十分な導電性が得
られなく、９６ｗｔ％を越えると耐熱熱硬化性樹脂と銅
めっきの密着性が低下する悪影響を及ぼし、いずれも適
してない。The content of the conductive filler is 50 wt%.
When the amount is less than the above, the deposition property of the chemical plating is not deteriorated and sufficient conductivity cannot be obtained. When the amount exceeds 96% by weight, the adhesiveness between the heat-resistant thermosetting resin and the copper plating is adversely affected, and neither is suitable.
【００３５】更に、導体フィラーの粒径における電気的
な接続性であるがこの平均粒径が５０μｍを越えると導
電性微粉間の接点が不足し導電性が低下し、０．２μｍ
未満では接触抵抗が増加し、導電性が低下し、いずれも
適してない。Further, regarding the electrical connectivity in terms of the particle size of the conductive filler, if the average particle size exceeds 50 μm, the contact between the conductive fine powders becomes insufficient and the conductivity decreases, and the conductivity decreases.
If it is less than 1, the contact resistance increases, the conductivity decreases, and neither is suitable.
【００３６】次いで、図３（ｈ）に示すように、図３
（ｇ）の表裏面にダイレクト電気銅めっきを用い、銅厚
さ２０μｍの第２の銅めっき層１９・２０を形成した。Next, as shown in FIG.
(G) Direct copper electroplating on both sides
It is to form a second copper plating layer 19, 20 of the 20 [mu] m.
【００３７】次いで、図４（ｉ）に示すように、公知の
写真法のエッチング製造技術によって貫通導電接続穴２
６上部が平坦なるランド層２１・２２と高密度なパター
ンが形成できた。Next, as shown in FIG. 4 (i), the through-holes 2 are formed by a known photolithographic etching manufacturing technique.
6 High-density patterns with land layers 21 and 22 having a flat upper part were formed.
【００３８】従って、上述の構成による内層銅張積層板
４Ａに存在する不導体入り絶縁性ペースト１０を充填さ
れた第１の導通接続穴（スルーホール）８内に同芯円状
で穴８径ｄ１よりも小さい径ｄ２になる貫通導電接続穴
２６を形成できるため、ランド層２１・２２の小スペー
ス化と設計の自由度がより向上し、更に高密度の実装化
が可能となる、本発明の多層プリント配線板２７を得る
ことができる。Accordingly, the first conductive connection hole (through hole) 8 filled with the non-conductor-containing insulating paste 10 present in the inner-layer copper-clad laminate 4A having the above-described configuration has a concentric circular hole 8 diameter. because it can form the through conductive connection hole 26 has a decreasing diameter d 2 than d 1, the small space and freedom of design of the land layer 21 and 22 is improved, thereby enabling higher density packaging of, The multilayer printed wiring board 27 of the present invention can be obtained.
【００３９】次いで、図１に示すように、第１の導通接
続穴８の径ｄ１よりも小さい第２の貫通孔１７を同芯円
状に穿孔し、この第２の貫通孔１７の内壁に耐熱導電性
ペースト１８を充填、形成、しかる後に、第２の銅めっ
き層１９・２０を施し、公知のエッチング技術により、
電極パターンと貫通導電接続孔２６上のランド層２１・
２２を形成し、このランド層領域２５をより狭く構成で
き、このランド層２１上に表面実装部品２３（ＳＭＤ）
をクリーム半田２４を用い、半田付した状態を示す本発
明の模式構造図である。Next, as shown in FIG. 1, a second through hole 17 smaller than the diameter d1 of the first conductive connection hole 8 is formed in a concentric circle, and an inner wall of the second through hole 17 is formed. Is filled with a heat-resistant conductive paste 18, and thereafter, the second copper plating layers 19 and 20 are applied.
Land layer 21 on electrode pattern and through conductive connection hole 26
22, the land layer region 25 can be configured to be narrower, and the surface mount component 23 (SMD) is formed on the land layer 21.
The use of a cream solder 24 is a schematic structural diagram of the invention showing a the state soldering.
【００４０】次いで、以上、実施例の電食性、穴２
６上のランド層１９・２０と耐熱導電性ペースト層１８
の密着性と、接続信頼性を評価し、その結果を（表
１）を下記に記載する。Next, as described above, the electrolytic corrosion property, hole 2
6 and land layers 19 and 20 and heat-resistant conductive paste layer 18
Was evaluated for adhesion and connection reliability, and the results are shown in Table 1 below.
【００４１】表１に接続信頼性の評価を示す。Table 1 shows the evaluation of connection reliability.
【表１】 後の絶縁抵抗値。 ２６０℃半田浴に２０秒浸漬、１０秒放置を３回く
り返した後穴（２６）断面を光学的に倍率４００倍にて
観察した。 ホットオイル試験（２６０℃オイル５秒浸漬、常温
水中５秒、浸漬を１サイクルとする）で第２の銅めっき
後抵抗値変化率１０％以上、上昇したサイクル数を不合
格とした。 供試数：各２０ピース[Table 1] Later insulation resistance value. After being immersed in a 260 ° C. solder bath for 20 seconds and left for 10 seconds three times, the cross section of the hole (26) was optically observed at a magnification of 400 ×. In the hot oil test (immersion in oil at 260 ° C. for 5 seconds, in water at room temperature for 5 seconds, and immersion as one cycle), the rate of change in resistance value after the second copper plating was 10% or more, and the number of cycles that increased was rejected. Number of test: 20 pieces each
【００４２】表１から明らかなように、本発明の実施例
による多層プリント配線板２７は、従来技術にかかる多
層プリント配線板５９に比べ電気的な接続信頼性、密着
性等について、有意差のない実施例の構造である。As is clear from Table 1, the multilayer printed wiring board 27 according to the embodiment of the present invention has a significant difference in electrical connection reliability, adhesion and the like as compared with the multilayer printed wiring board 59 according to the prior art. There is no embodiment structure.
【００４３】なお、以上の説明では、第２の貫通孔１７
の内に耐熱導電性ペースト１８を充填、形成した貫通導
電接続穴２６の穴の上に、ランド層２１・２２を構成す
る例をとって説明したが、従来の技術の第２のスルーホ
ール５０の穴内に耐熱導電性ペースト１８を充填、形成
して、しかる後に第２のスルーホール５０の穴上に表面
実装部品２３を高密度実装化できるランド層２１・２２
の構成に適用することが可能である。In the above description, the second through hole 17
In the above description, the land layers 21 and 22 are formed on the through conductive connection holes 26 formed by filling and forming the heat-resistant conductive paste 18. Are filled and formed with heat-resistant conductive paste 18 and then land layers 21 and 22 are provided, on which the surface mount components 23 can be densely mounted on the holes of the second through holes 50.
It is possible to apply to the configuration of
【００４４】[0044]
【発明の効果】 （１）本発明によれば、内層銅張積層板４Ａに存在する
不導体入り絶縁性ペースト１０を充填された第１の導通
接続穴８内に同芯円状に第１の導通接続穴８の径ｄ１よ
りも小さい径ｄ２の貫通導電接続穴２６を形成し穴２６
上にランド層２１・２２が形成できるため貫通導電接続
穴２６のランド層領域２５の小スペース化と設計の自由
度がより向上でき、産業上寄与する効果は極めて大きい
（図１参照のこと。）。 （２）本発明によれば、第２の貫通孔１７の内壁に第２
の銅めっき層４８・４９を形成しなく、かつ、ＳＭＤ２
３用配線ランド層５２・５３を形成しないために、工程
短縮と材料費の低減が可能であり産業上寄与する効果は
大である（図１参照のこと。）。(1) According to the present invention, the first conductive connection hole 8 filled with the non-conductor-containing insulating paste 10 existing in the inner layer copper-clad laminate 4A is concentrically inserted into the first conductive connection hole 8. of forming through conductive connection hole 26 of smaller diameter d 2 than the diameter d 1 of the conductive connecting hole 8 hole 26
Since the land layers 21 and 22 can be formed thereon, the space in the land layer region 25 of the through conductive connection hole 26 can be reduced and the degree of freedom in design can be further improved, and the effect of industrial contribution is extremely large (see FIG. 1). ). (2) According to the present invention, the second through hole 17
No copper plating layers 48 and 49 are formed and SMD2
Since the third wiring land layers 52 and 53 are not formed, the process can be shortened and the material cost can be reduced, and the effect of contributing to the industry is great (see FIG. 1).
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明は一実施例の小スペース化したランド層
に表面実装部品を搭載（ＳＭＴ）した状態を示す模式断
面構造図。FIG. 1 is a schematic cross-sectional structural view showing a state in which a surface mount component is mounted (SMT) on a land layer having a reduced space according to an embodiment of the present invention.
【図２】（ａ）〜（ｄ）は、本発明の製造工程を示す断
面図。FIGS. 2A to 2D are cross-sectional views illustrating a manufacturing process of the present invention.
【図３】（ｅ）〜（ｈ）は、本発明の製造工程を示す断
面図。FIGS. 3 (e) to 3 (h) are cross-sectional views illustrating a manufacturing process of the present invention.
【図４】（ｉ）は、本発明の製造工程を示す断面図。FIG. 4 (i) is a cross-sectional view showing a manufacturing step of the present invention.
【図５】（ａ）〜（ｂ）は、従来技術の製造工程を示す
断面図。FIGS. 5A and 5B are cross-sectional views showing a manufacturing process of a conventional technique.
【図６】（ｃ）〜（ｆ）は、従来技術の製造工程を示す
断面図。FIGS. 6 (c) to 6 (f) are cross-sectional views showing a conventional manufacturing process.
【図７】（ｇ）〜（ｈ）は、従来技術の製造工程を示す
断面図。FIGS. 7 (g) to 7 (h) are cross-sectional views showing a manufacturing process of a conventional technique.
【図８】従来技術に係るプリント配線板に表面実装部品
を半田付した状態の領域を示す模式断面構造図。FIG. 8 is a schematic cross-sectional structure diagram showing a region where a surface mount component is soldered to a printed wiring board according to a conventional technique.
【符号の説明】 １，２…銅箔 ３…絶縁基板 ４…多層の銅張積層板
４Ａ…内層銅張積層板 ４Ｂ，４Ｃ…接着剤付片面銅張積層基板 ５…第１の貫
通孔 ６，７…第１の銅めっき層 ８…導通接続穴（スルーホ
ール） １０…不導体入り絶縁性ペースト １５，１６…積層圧
着 １７…第２の貫通孔 １８…耐熱導電性ペースト １９，２０…第２の銅めっき層 ２１，２２…穴上のラ
ンド層 ２３…表面実装部品 ２４…クリーム半田 ２５…ラン
ド層領域 ２６…貫通導電接続穴 ２７…本発明の多層プリント配
線板 ３１，３２…銅箔 ３３…絶縁基板 ３４…多層の銅張
積層板 ３４Ａ…内層銅張積層板 ３５…第１の貫通孔 ３６，３７…第１の銅めっき層 ３８…第１の導通接続
穴（スルーホール） ３９Ａ，３９Ｂ…接着剤付片面銅張積層基板 ４０…絶
縁ペースト ４５，４６…積層圧着 ４７…第２の貫通孔 ４８，４
９…第２の銅めっき層 ５０…第２の導通接続穴（スルーホール） ５２，５３…第２のスルーホールランド層 ５４…半田
５５…ランド層領域 ５６…表面実装部品 ５９…従来の技術に係る多層プリ
ント配線板[Description of Signs] 1,2 ... Copper foil 3 ... Insulating substrate 4 ... Multilayer copper-clad laminate
4A: inner-layer copper-clad laminates 4B, 4C: single-sided copper-clad laminate with adhesive 5: first through hole 6, 7: first copper plating layer 8: conductive connection hole (through hole) 10: non-conductor-containing Insulating paste 15, 16 ... Lamination crimping 17 ... Second through hole 18 ... Heat resistant conductive paste 19,20 ... Second copper plating layer 21,22 ... Land layer on hole 23 ... Surface mount component 24 ... Cream solder 25 land layer region 26 through conductive connection hole 27 multilayer printed wiring board of the present invention 31, 32 copper foil 33 insulating substrate 34 multilayer copper clad
Laminated plate 34A: inner layer copper-clad laminate 35: first through hole 36, 37 ... first copper plating layer 38: first conductive connection hole (through hole) 39A, 39B: single-sided copper-clad laminate with adhesive Substrate 40: insulating paste 45, 46: laminated pressure bonding 47: second through hole 48, 4
9: second copper plating layer 50: second conductive connection hole (through-hole) 52, 53: second through-hole land layer 54: solder 55: land layer region 56: surface mount component 59: conventional technology Such a multilayer printed wiring board
Claims (4)
穴（８），貫通導電接続穴（２６），表面実装部品（２
３）用ランド（２１）・（２２）等を有する多層プリン
ト配線板であって、前記絶縁基板（３）と銅箔（１）・
（２）等からなるコア材（４Ａ）に選択的に第１の貫通
孔（５）を穿孔し、この孔（５）内に第１の銅めっき層
（６）・（７）を施し、しかる後導通接続穴（８）を形
成、かつこの穴（８）内に不導体入り絶縁性ペースト
（１０）を充填、構成し、この表裏面に片面銅張積層基
材（４Ｂ）・（４Ｃ）を積層圧着（１５）・（１６）
し、多層の銅張積層板（４）を構成と前記導通接続穴
（８）の径（ｄ1）よりも小さい径（ｄ2）の同芯円状の
第２の貫通孔（１７）を穿孔し、この孔（１７）内に耐
熱導電性ペースト（１８）を充填して形成した貫通導電
接続穴（２６）と、この表裏面に第２の銅めっき層（１
９）・（２０）を施し、この穴（２６）上にランド層
（２１）・（２２）を構成していることを特徴とする本
発明の多層プリント配線板（２７）。The present invention has four or more layers, and has conductive connection holes (8), through conductive connection holes (26), and surface mount components (2).
3) A multilayer printed wiring board having lands (21) and (22) for use, wherein the insulating substrate (3) and the copper foil (1)
A first through hole (5) is selectively drilled in a core material (4A) made of (2) or the like, and first copper plating layers (6) and (7) are applied in the hole (5). Thereafter, a conductive connection hole (8) is formed, and an insulating paste (10) containing a non-conductor is filled and formed in the hole (8). The single-sided copper-clad laminated base material (4B) / (4C) ) Is laminated and crimped (15) ・ (16)
Then, a multi-layer copper-clad laminate (4) is formed and a concentric second through hole (17) having a diameter (d 2 ) smaller than the diameter (d 1 ) of the conductive connection hole (8) is formed. A through conductive connection hole (26) is formed by filling the hole (17) with a heat resistant conductive paste (18), and a second copper plating layer (1
9) A multi-layer printed wiring board (27) according to the present invention, wherein the land layers (21) and (22) are formed on the holes (26).
性ペースト（１０）は、絶縁樹脂と不導体フィラーから
なり、この絶縁性樹脂は変性エポキシ樹脂，変性フェノ
ール系樹脂、及び変性ポリイミド樹脂で、これらから選
ばれる少なくとも一つであり、また上記不導体フィラー
は、シリカ粉，タルク粉，ガラス粉末でこれらから選ば
れる少なくとも一つであり、この平均粒径は５．０〜５
０μｍの範囲で、その粒径形状は球状であり、かつ不導
体フィラーの含有量は、５０〜９０重量％の範囲で残り
が絶縁樹脂で構成していることを特徴とする本発明の多
層プリント配線板（２７）。2. The insulating paste according to claim 1, wherein the insulating paste containing a nonconductor comprises an insulating resin and a nonconductive filler, and the insulating resin is a modified epoxy resin, a modified phenolic resin, and a modified polyimide resin. And the non-conductive filler is at least one selected from the group consisting of silica powder, talc powder and glass powder, and has an average particle size of 5.0 to 5
The multilayer print according to the present invention, wherein the particle size is spherical in the range of 0 μm, the content of the non-conductive filler is in the range of 50 to 90% by weight, and the remainder is composed of insulating resin. Wiring board (27).
スト（１８）は、耐熱熱硬化性樹脂と導体フィラーから
なり、この耐熱熱硬化性樹脂は、変性エポキシ樹脂，変
性フェノール系樹脂，変性ポリイミド樹脂でこれらから
選ばれる少なくとも一つでよく、また、この導体フィラ
ーは、パラジウム粉，銅粉，ニッケル粉でこれらの中の
少なくとも一つでよく、この平均粒径は、０．２〜５０
μｍの範囲でこの粒径は球状の形状であり、かつ導体フ
ィラーの含有量は、５０〜９６重量％の範囲で、残りが
耐熱熱硬化性樹脂で構成していることを特徴とする本発
明の多層プリント配線板（２７）。3. The heat-resistant conductive paste (18) according to claim 1, comprising a heat-resistant thermosetting resin and a conductive filler, wherein the heat-resistant thermosetting resin is a modified epoxy resin, a modified phenolic resin, a modified polyimide resin. The conductor filler may be at least one selected from these resins, and the conductive filler may be at least one of palladium powder, copper powder, and nickel powder.
The present invention is characterized in that the particle size is spherical in the range of μm, the content of the conductive filler is in the range of 50 to 96% by weight, and the remainder is composed of a heat-resistant thermosetting resin. Multilayer printed wiring board (27).
（１７）は、レーザー光照射を用い穿孔し、この孔（１
７）径を０．０４〜０．４mmの範囲であり、かつ第２の
貫通孔（１７）の内壁粗さを、１０〜５０μｍの範囲で
あることを特徴とする多層プリント配線板（２７）。4. The method according to claim 1, wherein the second through hole is formed by irradiating a laser beam.
7) The multilayer printed wiring board (27), wherein the diameter is in the range of 0.04 to 0.4 mm and the inner wall roughness of the second through hole (17) is in the range of 10 to 50 µm. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9183243A JPH1117341A (en) | 1997-06-25 | 1997-06-25 | Frinted multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9183243A JPH1117341A (en) | 1997-06-25 | 1997-06-25 | Frinted multilayer wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1117341A true JPH1117341A (en) | 1999-01-22 |
Family
ID=16132291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9183243A Pending JPH1117341A (en) | 1997-06-25 | 1997-06-25 | Frinted multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1117341A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001244636A (en) * | 2000-03-01 | 2001-09-07 | Ibiden Co Ltd | Printed wiring board |
| JP2002176263A (en) * | 2000-12-08 | 2002-06-21 | Ibiden Co Ltd | Printed wiring board |
| JP2002204076A (en) * | 2000-12-28 | 2002-07-19 | Ibiden Co Ltd | Multilayer printed wiring board and method of manufacture the same |
| JP2002204075A (en) * | 2000-12-28 | 2002-07-19 | Ibiden Co Ltd | Method of manufacturing multilayer printed wiring board |
| JP2002204074A (en) * | 2000-12-28 | 2002-07-19 | Ibiden Co Ltd | Multilayer printed wiring board |
| JP2002208778A (en) * | 2001-01-10 | 2002-07-26 | Ibiden Co Ltd | Multilayer printed wiring board |
| JP2002217543A (en) * | 2001-01-22 | 2002-08-02 | Ibiden Co Ltd | Multilayer printed wiring board |
| JP2002217542A (en) * | 2001-01-22 | 2002-08-02 | Ibiden Co Ltd | Multilayer printed-wiring board |
| JP2002217541A (en) * | 2001-01-22 | 2002-08-02 | Ibiden Co Ltd | Multilayer printed wiring board |
| CN102186305A (en) * | 2011-05-06 | 2011-09-14 | 沈李豪 | Printed wiring board, multilayer printed wiring board and manufacturing method thereof |
| US8093506B2 (en) | 2006-12-21 | 2012-01-10 | Ngk Spark Plug Co., Ltd. | Multilayer wiring board and power supply structure to be embedded in multilayer wiring board |
| CN103687279A (en) * | 2013-12-02 | 2014-03-26 | 广州美维电子有限公司 | Printed circuit board and manufacturing method for same |
-
1997
- 1997-06-25 JP JP9183243A patent/JPH1117341A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001244636A (en) * | 2000-03-01 | 2001-09-07 | Ibiden Co Ltd | Printed wiring board |
| JP2002176263A (en) * | 2000-12-08 | 2002-06-21 | Ibiden Co Ltd | Printed wiring board |
| JP2002204076A (en) * | 2000-12-28 | 2002-07-19 | Ibiden Co Ltd | Multilayer printed wiring board and method of manufacture the same |
| JP2002204075A (en) * | 2000-12-28 | 2002-07-19 | Ibiden Co Ltd | Method of manufacturing multilayer printed wiring board |
| JP2002204074A (en) * | 2000-12-28 | 2002-07-19 | Ibiden Co Ltd | Multilayer printed wiring board |
| JP2002208778A (en) * | 2001-01-10 | 2002-07-26 | Ibiden Co Ltd | Multilayer printed wiring board |
| JP2002217543A (en) * | 2001-01-22 | 2002-08-02 | Ibiden Co Ltd | Multilayer printed wiring board |
| JP2002217542A (en) * | 2001-01-22 | 2002-08-02 | Ibiden Co Ltd | Multilayer printed-wiring board |
| JP2002217541A (en) * | 2001-01-22 | 2002-08-02 | Ibiden Co Ltd | Multilayer printed wiring board |
| US8093506B2 (en) | 2006-12-21 | 2012-01-10 | Ngk Spark Plug Co., Ltd. | Multilayer wiring board and power supply structure to be embedded in multilayer wiring board |
| CN102186305A (en) * | 2011-05-06 | 2011-09-14 | 沈李豪 | Printed wiring board, multilayer printed wiring board and manufacturing method thereof |
| CN103687279A (en) * | 2013-12-02 | 2014-03-26 | 广州美维电子有限公司 | Printed circuit board and manufacturing method for same |
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