JPH11176183A - Electrically rewritable non-volatile semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage that can store parallel writing data quickly and can be electrically rewritten. SOLUTION: A non-volatile semiconductor storage is provided with a memory cell for storing data, word and bit lines connected to the memory cell, and a threshold voltage change means for changing the threshold voltage of the memory cell to three kinds or more. The threshold voltage change means has variable voltage circuits 1a-1h for a row line for applying one kind of voltage to the above word line for one kind of threshold voltage, and variable voltage generation circuits 2a-2h for applying one kind of voltage to the above bit line for one kind of the threshold voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a flash EEPROM.
The present invention relates to an electrically rewritable nonvolatile semiconductor memory device such as an OM, and more particularly to an electrically rewritable nonvolatile semiconductor memory device with a reduced writing time.

[0002]

2. Description of the Related Art An electrically rewritable non-volatile semiconductor memory device is an EEPROM (Electrical Memory).
ly Erasable Programmable
Read Only Memory) and FlashE
There is a so-called EPROM. FIG. 4 is a sectional view showing a conventional memory cell. Conventional memory cells are MO
It has an SFET structure, and a drain 52 and a source 53 made of an n-type impurity diffusion layer are formed on the surface of a p-type silicon substrate 51, and a channel region 54 is formed between them. On the channel region 54, a tunnel insulating film 55 made of a SiO ₂ film is formed, on which a floating gate 56, an interlayer insulating film 57, and a control gate 58 are sequentially formed. Then, the protective insulating film 59 covering them
Is provided. Further, a bit line 60 is connected to the drain 52, and a source line 61 is connected to the source 53.
Is connected. On the p-type silicon substrate 51, an element isolation film 62 for isolating each element is formed.

At the time of writing data to the memory cell thus formed, for example, the substrate 51 is grounded, the control gate 58 has 12 V, the drain 52 has 5 V, and the source 5 has
A voltage of 0 V is applied to 3. At this time, the control gate 5
The potential of floating gate 56 rises due to capacitive coupling between floating gate 8 and floating gate 56, and a channel region 53 is formed between drain 52 and source 53. In addition, high control gain
5 and the voltage of the drain 52, the drain 5
2, hot electrons having high energy are generated, and the hot electrons are generated in the p-type silicon substrate 51.
Is injected into the floating gate 56 over the potential barrier between the gate insulating film 55 and the gate insulating film 55. For example, the potential barrier of electrons is 3.
2 eV. The electrons injected into the floating gate 56 in this manner are retained even after the drain 52 and the control gate 56 are released because the floating gate 56 is surrounded by the insulating film having a low conductivity. It is held in a floating gate 56. Therefore, the memory cell is held in a state where the threshold voltage is increased.

On the other hand, at the time of data erasing operation, for example,
When the control gate 56 is grounded and a voltage of 12 V is applied to the source 53, electrons are extracted from the floating gate 56 and the threshold voltage decreases.

Conventionally, a memory cell has two
One bit has been configured with different types of threshold voltages. However, recently, in order to efficiently increase the capacity of a semiconductor memory device, it is required that one memory cell hold data of two or more bits. When this is realized by the device, it can be realized by giving the memory cells three or more types of threshold voltages. A nonvolatile semiconductor memory device having memory cells having three or more threshold voltages is disclosed in
No. 267,285 and JP-A-7-29382.

FIG. 5 is a block diagram showing a configuration of a conventional nonvolatile semiconductor memory device described in Japanese Patent Application Laid-Open No. 6-267285. In the conventional nonvolatile semiconductor memory device described in Japanese Patent Application Laid-Open No. 6-267285, eight memory cell arrays 13a to 13h each having a plurality of memory cells as described above are provided. One I / O terminal (not shown) is assigned to each of the memory cell arrays 13a to 13h. A word line 19 is connected to the control gates of the memory cells constituting each of the memory cell arrays 13a to 13h.
Are connected to the row decoder 14. The row decoder 14 is connected to the variable voltage generation circuit 11. The variable voltage generation circuit 11 can apply three kinds of voltages, for example, 10 V, 11 V, or 12 V to the word line 19. Also,
The drains of the memory cells constituting each of the memory cell arrays 13a to 13h are commonly connected to bit lines (not shown), and are connected to the column decoders 15a to 15h, respectively. The column decoders 15a to 15h are connected to the write circuits 16a to 16h, respectively, and the write circuits 6a to 6h are connected to the column line pulse generation circuit 12. The column line pulse generation circuit 12 can apply a voltage of, for example, 8.5 V to each bit line.

Further, the variable voltage generation circuit 11 and the column line pulse generation circuit 12 are connected to a write data detection circuit 17. The write data detecting circuit 17 receives the input write data I
N, “11”, “1”
It has a function of detecting and selecting which parallel write data is to be written among 0, 01 and 00. The row decoder 14 and all the column decoders 15a to 15a are also provided.
5h is connected to an address buffer 18 to which an address input signal is input. The address input signal input to the address buffer 18 is applied to the row decoder 14 and the column decoder 1.
5a to 15h, and thereby the word line 19
Then, an arbitrary memory cell is selected by selecting the bit line.

In the conventional nonvolatile semiconductor memory device configured as described above, at the time of writing data, three types of 10 V, 11 V or 12 V are supplied from the variable voltage generation circuit 11 to the word line 19 selected by the row decoder 14. Is applied stepwise. Then, when a desired voltage is applied to the control gate of the desired memory cell, a voltage of 8.5 V is applied to the bit line connected to the drain of the memory cell. Thereby, the threshold voltage of the memory cell changes. FIG. 6 is a schematic graph showing the distribution of the number of bits by taking the number of bits on the horizontal axis and the threshold voltage on the vertical axis. When electrons are not injected into the control gate, the threshold voltage of the memory cell is distributed in a region of less than 4 V to about 3.
There is a peak at 3V. This state is referred to as parallel write data "1".
1 "is stored. When a voltage of 10 V is applied to the control gate, the threshold voltage of the memory cell is distributed over a region of more than 4 V and less than 5.5 V to about 4.8.
V has a peak. This state is referred to as parallel write data "10".
Is stored. In addition, 11
When a voltage of V is applied, the threshold voltage of the memory cell is distributed over a region of more than 5.5 V and less than 7 V, and has a peak at about 6.3 V. This state is a state in which the parallel write data “01” is stored. Then, 12V is applied to the control gate.
Is applied, the threshold voltage of the memory cell becomes 7
There is a peak at about 7.8 V distributed in the region exceeding V.
This state is a state where the parallel write data “00” is stored. Thus, by defining the parallel write data for each threshold voltage, four types of values can be stored in one memory cell.

FIG. 7 is a timing chart showing the operation of the nonvolatile semiconductor memory device described in Japanese Patent Application Laid-Open No. 6-267285. For example, when the parallel write data of “01” is stored, 0 V to 10 V, 11
V and 12V are supplied stepwise, and when a voltage of 11V is supplied to the word line, 8.5 is supplied to the bit line.
A voltage of V is supplied. As a result, the threshold voltage of the memory cell increases to about 6.3 V, and as shown in FIG.
The parallel write data “01” is stored.

On the other hand, in the nonvolatile semiconductor memory device described in Japanese Patent Application Laid-Open No. 7-29382, a voltage is applied to a word line in order to optimize a writing time in accordance with each parallel writing data. Voltage can be switched, and voltage applied to the bit line can be switched. FIGS. 8A to 8G are timing charts showing the operation of a conventional nonvolatile semiconductor memory device capable of switching the word line applied voltage. In a semiconductor memory device in which the voltage applied to a word line can be switched, the threshold voltage changes as the voltage applied to the word line changes. By defining write data for each threshold voltage, 4
The type value can be stored in one memory cell. FIG.
As shown in (a), when only data "10" is stored, for example, a voltage of 10 V is applied to the word line, and at the same time, a voltage of 8.5 V is applied to the bit line. Further, as shown in FIG. 8B, when only data “01” is stored, for example, 11 V
, And at the same time, a voltage of 8.5 V is applied to the bit line. As shown in FIG. 8C, when only data “00” is stored, for example, a voltage of 12 V is applied to the word line, and at the same time, a voltage of 8.5 V is applied to the bit line. You.

When data "10" and "01" are stored, as shown in FIG. 8D, a voltage of 10 V or 11 V is applied to the word line in a stepwise manner, and the bit line is applied to the bit line. A voltage of 8.5 V is applied in a pulsed manner. Similarly,
When data “10” and “00” are stored, as shown in FIG. 8E, a voltage of 10 V or 12 V is applied to the word line in a stepwise manner, and a voltage of 8.5 V is applied to the bit line. Is applied in a pulse form. Further, when data “01” and “00” are stored, as shown in FIG. 8F, a voltage of 11 V or 12 V is applied to the word line in a stepwise manner, and 8.5 V is applied to the bit line. Is applied in a pulse form. Then, the data “10”, “01” and “00”
Is stored, as shown in FIG. 8 (g), a voltage of 10 V, 11 V or 12 V is applied to the word line in a stepwise manner, and a voltage of 8.5 V is applied to the bit line in a pulse form. You. The circuit configuration of this conventional nonvolatile semiconductor memory device is the same as that shown in FIG.

On the other hand, in a semiconductor memory device in which the voltage applied to the bit line can be switched, the threshold voltage changes as the voltage applied to the bit line changes. By defining write data for each threshold voltage, four types of values can be stored in one memory cell. FIG. 9 is a block diagram showing the configuration of a conventional nonvolatile semiconductor memory device described in Japanese Patent Application Laid-Open No. 7-29382. In the conventional example shown in FIG. 9, the same members as those in the conventional example shown in FIG. 9 are denoted by the same reference numerals, and detailed description thereof will be omitted. In this conventional example, the row decoder 14
Write voltage generating circuit 3 between write data detecting circuit 11 and
1 is connected. The write voltage generation circuit 31 can apply one type of voltage other than 0V to the word line 19, for example, 11V. Further, each of the write circuits 16a to 16h
Is connected to a column line variable voltage generating circuit 32,
The column line variable voltage generating circuit 32 is
It is connected to the. The column line variable voltage generation circuit 32 can simultaneously supply different voltages for each memory cell array.

FIGS. 10A to 10G are timing charts showing the operation of a conventional nonvolatile semiconductor memory device capable of switching the bit line applied voltage. As shown in FIG. 10A, when only data “10” is stored,
A voltage of 11 V is applied to the word line, and at the same time, for example, a voltage of 7 V is applied to the bit line. FIG.
As shown in 0 (b), when only data “01” is stored, a voltage of 11 V is applied to the word line, and at the same time, a voltage of 8 V, for example, is applied to the bit line. As shown in FIG. 10C, when only data "00" is stored, a voltage of 11 V is applied to the word line, and at the same time, for example, a voltage of 9 V is applied to the bit line.

When data "10" and "01" are stored, as shown in FIG. 10D, a voltage of 11 V is applied to the word line, and 7 V or 8 V is applied to the bit line.
Are applied simultaneously. Similarly, when data “10” and “00” are stored, as shown in FIG. 10E, a voltage of 11 V is applied to the word line, and a voltage of 7 V or 9 V is simultaneously applied to the bit line. Applied. Further, when data “01” and “00” are stored,
As shown by 0 (f), a voltage of 11 V is applied to the word line, and a voltage of 8 V or 9 V is applied to the bit line at the same time. Then, the data “10”, “01” and “00”
Is stored, as shown in FIG. 10 (g), a voltage of 11V is applied to the word line, and 7V,
8V or 9V voltage is applied simultaneously.

[0015]

However, if the threshold voltage of the above-mentioned conventional nonvolatile semiconductor memory device is controlled to a plurality of values, there is a problem that a long write time is required.

In Japanese Patent Application Laid-Open No. 6-267285, if one memory cell is to have four values, three voltages of 10 V, 11 V or 12 V must be applied to the word line without fail. Therefore, the writing time is long. In particular, in a flash EEPROM having multiple values, 1
As the number of bits given to one memory cell increases, the writing time becomes significantly longer.

Further, Japanese Patent Application Laid-Open No. 7-29382 discloses a method in which a word line voltage or a bit line voltage of a memory cell can be switched, a verify operation is performed after a write voltage is applied, and three or more types of memory cells are verified. A threshold voltage is provided. In the structure in which the voltage applied to the word line can be switched, as in Japanese Patent Application Laid-Open No. Hei 6-267285, if there are n types of parallel write data, the word line voltage is switched n times to write. Have to do. For this reason, the writing time is extremely long. Further, in a structure in which the voltage applied to the bit line can be switched, different bit line voltages can be applied simultaneously according to the parallel write data, so that the word line voltage can be switched. Although the writing time is shorter than the writing speed, the writing speed is not sufficient.

The present invention has been made in view of the above problems, and has as its object to provide an electrically rewritable nonvolatile semiconductor memory device capable of storing parallel write data at high speed. .

[0019]

According to the present invention, there is provided an electrically rewritable nonvolatile semiconductor memory device comprising: a memory cell for storing data; a word line and a bit line connected to the memory cell; Threshold voltage changing means for changing the threshold voltage of the cell to three or more types, wherein the threshold voltage changing means applies one type of voltage to one type of threshold voltage in the word A first voltage applying means for applying a voltage to the bit line; and a second voltage applying means for applying one type of voltage to the bit line for one type of threshold voltage.

According to the present invention, the threshold voltage of the memory cell is set to a desired value according to the parallel write data.
A predetermined voltage is simultaneously applied to a word line and a bit line of a memory cell in which data is stored, and the data is stored in the memory cell. For example, there are y kinds of parallel write data (y ≧
3) In some cases, a predetermined voltage among the (y-1) types of voltages is applied to the word line of the memory cell storing data by the first voltage applying means for each memory cell. At the same time, a predetermined voltage among the voltages that change in (y-1) types is simultaneously applied to the bit line for each memory cell by the second voltage applying means. For this reason, the most optimal voltage is simultaneously applied to each memory cell in which data is stored in accordance with the respective write data, so that the write time is significantly reduced.

[0021] The memory cell array may include a plurality of memory cell arrays, and each of the memory cell arrays may include the first voltage supply means and the second voltage supply means.

Further, data can be simultaneously stored in the plurality of memory cells.

[0023] The threshold voltage may rise or fall when data stored in the memory cell changes.

The memory cell has a channel region and a floating gate, and the threshold voltage is increased by generating hot electrons in the channel region and injecting electrons into the floating gate. Can be.

The memory cell has a floating gate, and is formed by a Farrer-Nordheim tunneling method (FN method).
Charge is injected into the floating gate by
The threshold voltage may rise or fall.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an electrically rewritable nonvolatile semiconductor memory device according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a configuration of an electrically rewritable nonvolatile semiconductor device according to an embodiment of the present invention. In this embodiment,
A plurality of, for example, eight memory cell arrays 3a to 3h including MOSFET memory cells using normal hot electrons are provided. One I / O terminal (not shown) is assigned to each of the memory cell arrays 3a to 3h.

The control gates of the memory cells constituting each of the memory cell arrays 3a to 3h have word lines 9a to 9h.
Are connected, and the word lines 9a to 9h are connected to the row decoders 4a to 4h, respectively. Each row decoder 4a
4h to 4h are connected to the row line variable voltage generating circuits 1a to 1h, respectively. Variable voltage generating circuits 1a to 1 for each row line
h can apply three types of voltages, that is, a first voltage, a second voltage, or a third voltage to each of the word lines 9a to 9h.
Note that the value of the first voltage, the second voltage, or the third voltage is:
For example, they are smaller in this order. In addition, bit lines (not shown) are connected to drains of the memory cells constituting each of the memory cell arrays 3a to 3h, and the bit lines are connected to column decoders 5a to 5h. And
Each of the column decoders 5a to 5h has a write circuit 6a to 6h, respectively.
, And the write circuits 6a to 6h are connected to the column line variable voltage generation circuits 2a to 2h, respectively. Each column line variable voltage generating circuit 2a to 2h has a fourth
, A fifth voltage, or a sixth voltage can be applied. The values of the fourth voltage, the fifth voltage, and the sixth voltage are, for example, smaller in this order.

Further, all the row line variable voltage generating circuits 1a
To 1h and the column line variable voltage generation circuits 2a to 2h are connected to the write data detection circuit 7. The write data detecting circuit 7 receives the input write data IN, and selects "11", "10", "01" and "00" in any of the memory cell arrays.
Has a function of detecting and selecting which parallel write data is to be written. All the row decoders 4a to 4h and the column decoders 5a to 5h are connected to an address buffer 8 to which an address input signal is input. The address input signal input to the address buffer 8 is transmitted to the row decoders 4a to 4h and the column decoders 5a to 5h, whereby a predetermined word line and bit line are selected and the memory at the intersection is selected. The cell is selected. In this way, the optimum write voltage is applied from the row line variable voltage generating circuits 1a to 1h to any of the word lines 9a to 9h of the selected memory cell, and the memory selected according to the parallel write data. Column line variable voltage generator 2 for the bit line of the cell array
The optimum write voltage is applied simultaneously from a to 2h.

Next, the operation of the nonvolatile semiconductor memory device according to this embodiment having the above-described configuration will be described.
In this embodiment, as described above, 2-bit data (four values) can be stored in one memory cell. First, the input write data IN is applied to the write data detection circuit 7.
, The write data detecting circuit 7 detects which parallel write data among "11", "10", "01" and "00" is written in which memory cell array. Selected.

Then, based on the selected parallel write data, an optimum write voltage is applied to the memory cells of the selected memory cell arrays 3a to 3h. FIG. 2 is a timing chart showing the operation of the nonvolatile semiconductor memory device according to the embodiment. In this embodiment, the word lines 9a to 9h
When the first voltage is applied to any of the bit lines of the memory cell array to which the word line is connected,
Is applied, and the write data "10" is stored in the memory cell located at these intersections. Word line 9
When the second voltage is applied to any of a to 9h,
The fifth voltage is applied to the bit line of the memory cell connected to the word line, and the write data “01” is stored in the memory cell located at the intersection between these. Further, when the third voltage is applied to any of the word lines 9a to 9h, the sixth voltage is applied to the bit line of the memory cell to which the word line is connected, and the memory located at the intersection of these is applied. Write data “00” is stored in the cell. On the other hand, when no voltage is applied to any of the word lines 9a to 9h, no voltage is applied to the bit line of the memory cell connected to that word line. Indicates that write data “11” is stored. The memory cells storing the respective write data are determined by an address input signal input to the address buffer 8. Then, similarly to the conventional example, as shown in FIG.
Is stored, the threshold voltage becomes less than 4 V, and when the write data “10” is stored, the threshold voltage becomes more than 4 V and less than 5.5 V, and the write data “01” becomes When stored, the threshold voltage is 5.5
When the voltage exceeds V and becomes less than 7 V, and the write data “00” is stored, the threshold voltage exceeds 7 V.

In a memory cell in a certain memory cell array,
For example, when the write data "10" is stored, the first voltage is applied to the word line from the row line variable voltage generation circuit connected to the selected memory cell array, and at the same time, A fourth voltage is applied to the bit line from the column line variable voltage generation circuit via the write circuit. Then, verification is performed to determine whether the write data "10" has been stored. In this verification, the threshold voltage exceeds 4 V to 5.5 V
If it is less than, it is considered a pass, otherwise it is considered a fail. If it is determined as pass, the process proceeds to the next step. If it is determined as fail, the write voltage is applied again to the control gate and drain of the same memory cell. When write data “01” is stored,
The second voltage is applied to the word line from the row line variable voltage generating circuit connected to the selected memory cell, and at the same time, the column line variable voltage generating circuit is connected to the bit line via the writing circuit. And a fifth voltage is applied. Then, verification is performed. If the threshold voltage exceeds 5.5 V and is less than 7 V, it is regarded as a pass. Otherwise, it is regarded as a fail. When the write data "00" is stored, the third voltage is applied to the word line from the row line variable voltage generating circuit, and at the same time, the column line variable voltage is generated to the bit line. A sixth voltage is applied from the circuit via the writing circuit. Then, verification is performed. If the voltage exceeds the threshold voltage of 7 V, it is regarded as a pass. Otherwise, it is regarded as a fail.

In this embodiment, as shown in FIG.
For each of the memory cells 3a to 3h, the row line variable voltage applying circuits 1a to 1h and the column line variable voltage applying circuits 2a to 2h
h is connected and the optimum write voltage is simultaneously applied to each memory cell, so that "10",
Even when “01” or “00” is mixed, the writing speed is extremely high as compared with the conventional nonvolatile semiconductor memory device.

Next, "10" and "0" are added to the parallel write data.
A description will be given of the write time when 1 or 00 is mixed in. Here, in this embodiment, it is necessary to write "10", "01" or "00" to the write data. It is assumed that the time is 50 μs and the time required for the verification is 1 μs, and the horizontal axis indicates time, and the vertical axis indicates the threshold voltage of the memory cell. 7 is a graph showing a situation where a threshold voltage rises in a storage device, where "10" is written in write data;
The time required to write “01” or “00” is 50
Assuming μs, the writing of each write data is completed from the state where no voltage is applied to the memory cell, its threshold voltage is less than 4 V, and write data “11” is written. The threshold voltage simply increases until 50 μs
Over time the increase saturates. In this state, each write data is stored in the memory cell. In this embodiment, even if three types of write data "10", "01" or "00" are mixed in the parallel write data, the optimum write voltage for each memory cell is obtained. Are applied at the same time,
No matter how parallel write data is mixed, writing is completed in 50 μs.

Next, under the above assumption, a description will be given in comparison with a conventional nonvolatile semiconductor memory device. Table 1 is a table showing write times in various combinations of parallel write data. In Table 1, Conventional Example 2 is disclosed in JP-A-6-267.
285 shows the write time in the nonvolatile semiconductor memory device described in Japanese Patent Laid-Open No. 285/285.
FIG. 1 shows a write time in a nonvolatile semiconductor memory device in which a bit line voltage is switchable described in Japanese Patent Application Laid-Open Publication No. H10-26095.

[0035]

[Table 1]

For example, when "10" and "00" coexist as parallel write data, as described above, in this embodiment, one-step writing and one-time verification are required, so that 51 .mu.s is consumed. It is. On the other hand, Conventional Example 2 (Japanese Unexamined Patent Application Publication No.
-267285), a three-stage voltage of 50 is applied to the word line.
Since it is applied every .mu.s, 50 .mu.s as a write time until each write data is brought into a state of a desired threshold voltage.
× 3 steps and 1 μs × 2 times as two times for verifying the write data “10” and verifying the write data “00” are required.
s is spent. Further, among the nonvolatile semiconductor memory devices described in Japanese Patent Application Laid-Open No. 7-29382, those in which the word line voltage can be switched require a write time of 152 μs as in Conventional Example 2. In the conventional example 3 (Japanese Patent Laid-Open No. 7-29382) in which the bit line voltage can be switched, only a constant write voltage is applied to the word line as described above.
Therefore, the time required to store one type of write data is longer than that of the present embodiment. In FIG. 11, the horizontal axis indicates time, and the vertical axis indicates the threshold voltage of a memory cell. Assuming the rise of the threshold voltage in the conventional nonvolatile semiconductor memory device described in Japanese Patent Laid-Open No. 7-29382. It is a graph which shows the situation of. In the nonvolatile semiconductor memory device described in Japanese Patent Application Laid-Open No. 7-29382 in which the bit line voltage is variable, the voltage applied to the word line is constant for all write data. Compared with the example, the write time of the write data is longer, for example, 70 μs. When "10" and "00" coexist as parallel write data, one-step writing and one-time verification are required. Spent.

As shown in Table 1, it is clear that the parallel writing time of the first embodiment of the present invention is extremely short regardless of the combination of the parallel writing data.

The present invention is also applicable to a case where four or more values are stored in one memory cell, for example, n bits (n ≧ 2) of data are stored in one memory cell. In this case, a plurality of write voltages may be provided. The write voltage has various values depending on the characteristics of the memory cell.

Further, in this embodiment, the memory cell in which hot electrons are used at the time of writing has been described. However, a memory using the FN method which uses a Farrer-Nordheim tunnel current (FN current) at the time of writing. It can be applied to cells.

Further, in this embodiment, the case where writing is performed by raising the threshold voltage has been described. However, the present invention can be applied to the case where writing is performed by lowering the threshold voltage. it can. As a method of lowering the threshold voltage, for example, a positive charge may be injected into the floating gate by the FN method.

Further, in this embodiment, eight memory cell arrays are provided in parallel, but the present invention is not limited to this. It can be increased or decreased according to the capacity of the nonvolatile semiconductor memory device.

[0042]

As described in detail above, according to the present invention,
Each of a word line and a bit line of a memory cell whose threshold voltage changes to three or more types of nonvolatile semiconductor memory devices,
Since an optimum voltage can be applied according to the threshold voltage, the threshold voltages of a plurality of memory cells can be simultaneously optimized. With this, EEPRO
In M and Flash EEPROMs, the parallel writing time can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an electrically rewritable nonvolatile semiconductor device according to an embodiment of the present invention.

FIG. 2 is a timing chart illustrating an operation of the nonvolatile semiconductor memory device according to the embodiment.

FIG. 3 is a graph showing an assumption of a rise in threshold voltage in the nonvolatile semiconductor memory device according to the embodiment.

FIG. 4 is a cross-sectional view showing a conventional memory cell.

FIG. 5 is a block diagram showing a configuration of a conventional nonvolatile semiconductor memory device described in JP-A-6-267285.

FIG. 6 is a schematic graph showing the distribution of the number of bits.

FIG. 7 is a timing chart showing the operation of the nonvolatile semiconductor memory device described in JP-A-6-267285.

FIG. 8 is a timing chart showing an operation of a conventional nonvolatile semiconductor memory device capable of switching a word line applied voltage.

FIG. 9 is a block diagram showing a configuration of a conventional nonvolatile semiconductor memory device described in JP-A-7-29382.

FIG. 10 is a timing chart showing an operation of a conventional nonvolatile semiconductor memory device capable of switching a bit line applied voltage.

FIG. 11 is a graph showing a situation in which a threshold voltage rise in a conventional nonvolatile semiconductor memory device described in Japanese Patent Application Laid-Open No. 7-29382 is assumed.

[Explanation of symbols]

 1a, 1b, 1h; row line variable voltage generation circuits 2a, 2b, 2h; column line variable voltage generation circuits 3a, 3b, 3h; memory cell arrays 4a, 4b, 4h; row decoders 5a, 5b, 5h; 6a, 6b, 6h; write circuit 7, write data detection circuit 8, address buffer 9a, 9b, 9h; word line IN; input write data

Claims (7)

[Claims] 1. A memory cell for storing data, word lines and bit lines connected to the memory cell, and threshold voltage changing means for changing the threshold voltage of the memory cell to three or more types. The threshold voltage changing means includes first voltage applying means for applying one kind of voltage to the word line with respect to one kind of threshold voltage; And a second voltage applying means for applying one kind of voltage to the bit line. 2. The semiconductor device according to claim 1, further comprising a plurality of memory cell arrays each including a plurality of said memory cells, wherein said memory cell array includes said first voltage applying means and said second voltage applying means. 2. The electrically rewritable nonvolatile semiconductor memory device according to 1. 3. The electrically rewritable nonvolatile semiconductor memory device according to claim 2, wherein data is simultaneously stored in a plurality of said memory cells. 4. The electrically rewritable nonvolatile memory according to claim 1, wherein the threshold voltage increases when data stored in the memory cell changes. Semiconductor memory device. 5. The electrically rewritable nonvolatile memory according to claim 1, wherein the threshold voltage decreases when data stored in the memory cell changes. Semiconductor memory device. 6. The memory cell has a channel region and a floating gate. Hot electrons are generated in the channel region and electrons are injected into the floating gate, so that the threshold voltage increases. The electrically rewritable nonvolatile semiconductor memory device according to claim 4, wherein: 7. The memory cell has a floating gate, and the threshold voltage is changed by injecting electric charges into the floating gate by a Farrer-Nordheim tunneling method (FN method). A feature according to claim 4 or claim 5.
3. The electrically rewritable nonvolatile semiconductor memory device according to 1.