JPH1118009A - Solid-state imaging device - Google Patents

Abstract

(57) [Problem] To provide a square pixel capable of simultaneously reading out all pixels based on a pixel structure suitable for an interlace method used in a CCD image sensor for television, and to provide a CCD image sensor for multimedia in a short term. Provided is a solid-state imaging device that can be developed between devices. A unit pixel includes a photodiode 101.
, A vertical CCD register 102, an element isolation region 1 for separating them, and a read gate region 2 for reading signal charges from the photodiode 101 to the vertical CCD register 102. Vertical CCD
The register 102 is provided with vertical transfer electrodes 3 and 4. The vertical transfer electrode 4 also functions as a read gate electrode. Here, the feature is that the aspect ratio of the pixel is 1: 2, and the other configuration is the same as that of the conventional pixel. Also, the driving method is the same as the conventional one.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD type two-dimensional solid-state imaging device, and more particularly, to a solid-state imaging device having a pixel configuration for developing both television and multimedia devices in a short period of time. .

[0002]

2. Description of the Related Art A conventional technique will be described below with reference to FIGS.

FIG. 5 shows a general interline transfer type solid-state imaging device.

This solid-state imaging device comprises a plurality of photodiodes 101 for photoelectric conversion and a photodiode 1
01, a vertical CCD register 102 for receiving and transferring the charge from the vertical CCD register 102, a horizontal CCD register 103 for receiving and transferring the charge from the vertical CCD register 102,
The charge detection unit 104 includes a charge detection unit 104 that detects charges transferred by the CD register 103 and an output amplifier 105 that outputs an electric signal corresponding to the charges detected by the charge detection unit 104. Here, the portion surrounded by the two-dot chain line is the unit pixel 106.

FIG. 6 is a schematic diagram for explaining the interlace method.

Many of the solid-state imaging devices developed so far correspond to an interlace system (also called an interlaced scanning system) in order to be adapted for television use. Here, it is assumed that each horizontal line corresponds to each row of the photodiode. 1 frame (screen) is 2
The first field is composed of odd-numbered horizontal lines, and the second field is composed of even-numbered horizontal lines. The technique of suppressing the screen flicker called flicker by doubling the number of screens by skipping scanning every other line in this manner is generally used in television.

FIG. 7 is a pixel arrangement diagram of a solid-state imaging device conforming to the HDTV format.

[0008] The aspect ratio (aspect ratio) of the effective imaging area 111 is 9:16. 2/3 compatible with HDTV system
In the case of a 1.3-million pixel CCD image sensor, the number of effective pixels is 1258 (H) × 1035 (V), and the unit pixel size is 7.6 μm (H) × 5.2 μm (V). As described above, the unit pixel of the solid-state imaging device conforming to the television format is generally not a square pixel,
The aspect ratio differs depending on the optical format and the number of pixels.

FIG. 8 is a schematic plan view for explaining a configuration of a unit pixel of a conventional solid-state imaging device suitable for the interlaced system.

The unit pixel includes a photodiode 101,
It comprises a vertical CCD register 102, an element isolation region 121 for separating them, and a read gate region 122 for reading signal charges from the photodiode 101 to the vertical CCD register 102. Vertical C
The CD register 102 has vertical transfer electrodes 123 and 124
Is provided. The vertical transfer electrode 124 also functions as a read gate electrode. Also, the vertical transfer electrode 1
Although 23 and 124 are depicted as being formed only on the vertical CCD register 102, they actually extend between the vertically adjacent photodiodes 101. It is common. Note that a light-shielding film (not shown) for shielding the vertical CCD register 102 from light is provided above the vertical transfer electrodes 123 and 124 via an insulating film.

FIG. 9 is a sectional view showing the correspondence between the electrodes of the vertical CCD register and the driving pulses in the solid-state imaging device having the unit pixels shown in FIG.

Here, a case is shown in which the vertical CCD register is driven by four-phase pulses (φV1 to φV4).
Vertical transfer electrodes 123 and 124 are provided on the surface of the semiconductor substrate 131 via an insulating film 132. As shown in FIG. 8, two vertical transfer electrodes 123 and 124 are provided for one pixel.
Are included, one transfer stage is constituted by four vertical transfer electrodes corresponding to two pixels.

FIG. 10 is a diagram for explaining a charge transfer operation in a four-phase driven vertical CCD register. FIG. 10A is a timing chart of transfer pulses applied to each vertical transfer electrode, and FIG. 12) is a channel potential diagram under each vertical transfer electrode corresponding to each of the times t1 to t9 in FIG. Here, the channel potential is positive on the lower side of the drawing. In order to simplify the description, the transfer of only one packet of signal charges will be described.

At time t1, signal charges are accumulated in the channel below the vertical transfer electrode to which φV3 and φV4, to which the transfer pulse is at a high level, are applied. Time t2
Then, φV1 further becomes a high level, and the signal charge becomes 3
It is stored in the channel below the electrode. At time t3, φV3 goes low, and signal charges are accumulated in the channel below the two electrodes to which φV4 and φV1 are applied. That is, in the transition from time t1 to t3, the position of the signal charge has moved by one electrode. Hereinafter, similarly, the electrodes move by four electrodes (corresponding to one transfer stage) from time t1 to t9. By this repetitive operation, signal charges are transferred to the vertical CCD register 102.

As can be seen from the transfer form shown in FIG.
In the pixels of the type shown in (1), the signals of all the pixels cannot be read and transferred simultaneously and independently. Normally, signal charges of two pixels adjacent in the vertical direction are transferred to the vertical CCD register 1
02 is added and output. As a result, although the resolution in the vertical direction is deteriorated as compared with the case where all pixels are read out independently, the signal amount is doubled, so that an image with a good S / N is obtained. In addition, the combination of two pixels in the vertical direction for each field is shifted by one pixel and added, thereby supporting the interlace method.

On the other hand, a non-interlace type (also called a progressive scanning type or a progressive scanning type) solid-state imaging device is preferable for adapting to an image input device for a multimedia device which has been actively developed in recent years. This is because still images are often handled in multimedia applications, and higher resolution is required.

FIG. 11 is a schematic diagram for explaining the non-interlace method.

Here, each horizontal line corresponds to each row of the photodiode. One frame (screen) is composed of all the horizontal lines scanned sequentially, so that high-resolution image quality can be obtained. Furthermore, in processing an image such as a rotation process, a square pixel that can omit a pixel aspect ratio correction circuit is preferable.

FIG. 12 is a pixel array diagram of a solid-state imaging device conforming to the SXGA format.

The aspect ratio of the effective imaging area 141 is 4:
5 SXGA compatible 2/3 inch 1.3 million pixels C
In the case of a CD image sensor, the number of effective pixels is 1280
(H) × 1024 (V), unit pixel size is 6.7 μm
(H) × 6.7 μm (V). As described above, square pixels are mainly used as unit pixels of a solid-state imaging device suitable for multimedia use.

FIG. 13 is a schematic plan view for explaining a configuration of a unit pixel of a solid-state imaging device suitable for a non-interlace system.

The unit pixel includes a photodiode 101,
It comprises a vertical CCD register 102, an element isolation region 151 for separating them, and a read gate region 152 for reading signal charges from the photodiode 101 to the vertical CCD register 102. Vertical CCD
The register 102 is provided with vertical transfer electrodes 153 to 156. The vertical transfer electrode 155 also functions as a read gate electrode. Also, the vertical transfer electrode 153
156 are depicted as being formed only on the vertical CCD register 102, but actually extend between the vertically adjacent photodiodes 101, and are shared by pixels in the same horizontal row. It has become. Note that the vertical transfer electrodes 153 to 156 have a vertical C
A light shielding film (not shown) for shielding the CD register 102 from light is provided.

FIG. 14 is a diagram showing the correspondence between the electrodes of the vertical CCD register and the driving pulses in the solid-state imaging device having the unit pixels shown in FIG.

Here, a case is shown in which the vertical CCD register is driven by four-phase pulses (φV1 to φV4).
Vertical transfer electrodes 153 to 156 are provided on the surface of the semiconductor substrate 161 via an insulating film 162. As shown in FIG. 13, four vertical transfer electrodes 153 to 15 are provided for one pixel.
6 is included, and this constitutes one transfer stage. In this manner, by associating one transfer stage with one pixel, signals of all pixels can be read and transferred simultaneously and independently. Simultaneous readout of all pixels is a necessary function for adapting to the non-interlace method.

[0025]

As described above, the configuration of a pixel suitable for a television system and the configuration of a pixel suitable for a multimedia application are different from each other. It is not an exaggeration to say that in developing a CCD image sensor, most of the time spent optimizing the characteristics of pixels is spent. Therefore, there is a problem that it takes about twice as long to develop both of the above two types of CCD image sensors.

As one method for solving this problem, there is a method disclosed in Japanese Patent Application Laid-Open No. 7-143410. This method uses pixels suitable for multimedia applications.
By arranging them in a television format (for example, an aspect ratio of 9:16 for HDTV, and an aspect ratio of 3: 4 for NTSC), the development period of two types of CCD easy sensors is shortened.

However, since this method is based on square pixels capable of simultaneously reading out all pixels, each signal charge is equivalent to one photodiode when interlaced driving is performed, and sufficient S / N can be obtained. There is no problem. In a four-phase driven vertical CCD register, in order to add signal charges of two photodiodes adjacent in the vertical direction in the vertical CCD register, it is necessary to increase the number of drive pulses to at least five or more. This is not preferable because the number and the number of drive circuits increase.

As a method of adding the signal charges of two photodiodes adjacent in the vertical direction without increasing the types of driving pulses, there is a method of adding the signal charges by a horizontal CCD register. Hereinafter, this method will be described.

FIG. 15 shows the relationship between the vertical CCD register and the horizontal C register.
FIG. 5 is a diagram for explaining a charge transfer operation to a CD register. FIG. 15A is a timing chart of a transfer pulse applied to each transfer electrode in a horizontal blanking period. FIG. 15B shows each time t1 in FIG.
It is a channel electric potential diagram of each electrode lower part corresponding to -t9. Here, the channel potential is positive on the lower side of the drawing.
Note that, for simplicity of description, a state of transfer of only the signal charges A and B of two photodiodes adjacent in the vertical direction will be described.

At time t1, signal charges A and B are accumulated in the channel below the vertical transfer electrode to which φV3 and φV4, to which the transfer pulse is at a high level, respectively, are applied. At time t2, φV1 further goes to the high level, and the signal charge A is transferred toward the lower portion of the horizontal transfer electrode to which φV1 at the high level is applied. The transfer of the signal charge B is the same as the normal vertical transfer described with reference to FIG. Then, at time t
At 5, the signal .phi.V1 goes low, and the signal charge A is almost completely transferred to the lower part of the horizontal transfer electrode. Similarly, the signal charge B is transferred to the lower part of the horizontal transfer electrode by the vertical transfer pulse group in the second cycle in the horizontal blanking period.
At this time, since the signal charge A stays below the horizontal transfer electrode, the signal charge A and the signal charge B are eventually added as shown at time t9.

However, there is a problem in the addition of signal charges in such a horizontal CCD 103 register. That is, a vertical transfer pulse group of about two cycles must be inserted within the horizontal blanking period limited by the television standard. When a local transfer failure from the vertical CCD register 102 to the horizontal CCD register 103 occurs, a black line is generated in a vertical direction on a reproduced image, and the image quality is significantly deteriorated. In order to suppress the local transfer failure, it is necessary to secure as long a period P as possible from when the transfer pulse applied to the vertical final electrode becomes low level to when horizontal transfer starts. However, when two vertical transfer pulse groups are inserted, it is apparent that the period P is significantly reduced, and therefore, there is a problem that black line defects are extremely likely to occur.

[0032]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a square pixel capable of simultaneously reading out all pixels based on a pixel structure suitable for an interlace system used in a CCD image sensor for television, and to provide a CCD for multimedia. An object of the present invention is to provide a solid-state imaging device capable of developing an image sensor in a short time.

[0033]

That is, in the solid-state imaging device of the present invention, a unit pixel including a plurality of photodiodes for performing photoelectric conversion and a vertical CCD register for receiving and transferring electric charges from these photodiodes is formed in a two-dimensional form. An image pickup area arranged in the vertical CCD register, a horizontal CCD register for receiving and transferring charges from the vertical CCD register, a charge detection unit for detecting charges from the horizontal CCD register,
An output amplifier that outputs an electric signal corresponding to the electric charge detected by the electric charge detection unit. The aspect ratio of the dimensions of the unit pixel is 1: 2. At this time, one transfer stage of the vertical CCD register may be constituted by vertical transfer electrodes for two pixels of the unit pixel.

Further, the solid-state imaging device according to the present invention has an imaging area in which unit pixels including a plurality of photodiodes for performing photoelectric conversion and a vertical CCD register for receiving and transferring charges from these photodiodes are two-dimensionally arranged. When,
A horizontal CCD register for receiving and transferring the charge from the vertical CCD register; a charge detection unit for detecting the charge from the horizontal CCD register; and an output for outputting an electric signal corresponding to the charge detected by the charge detection unit And an amplifier. The unit pixel is a square pixel in which two pixels having an aspect ratio of 1: 2, including a vertical transfer electrode corresponding to a half transfer stage of the vertical CCD register, are arranged in the vertical direction. I have.

According to the present invention, except that the aspect ratio is 1: 2, since the pixel configuration is the same as the conventional one suitable for the interlacing method, the signal charges of two pixels adjacent in the vertical direction are transferred to the vertical CCD. It can be easily added by a register. Therefore, the problem of black line failure does not occur. A pixel having an aspect ratio of 1: 2 and two pixels arranged in the vertical direction is regarded as a unit pixel, and becomes a square pixel. In the square pixel, a vertical pixel register corresponding to one transfer stage of a vertical CCD register is provided. Since the transfer electrodes are included, all pixels can be read simultaneously and can be compatible with the non-interlace method.

That is, the basic configuration of the pixel is divided into two types of CCDs, an interlaced type and a non-interlaced type.
Since the image sensor can be used in common, two types of devices for television and multimedia can be developed in a period substantially equivalent to developing one type of device.

[0037]

FIG. 1 is a schematic plan view for explaining a configuration of a unit pixel in a solid-state imaging device suitable for an interlace system according to a first embodiment of the present invention.

The unit pixel includes a photodiode 101,
A vertical CCD register 102, an element isolation region 1 for isolating them, and a vertical C
And a read gate region 2 for reading signal charges into the CD register 102. The vertical CCD register 102 is provided with vertical transfer electrodes 3 and 4. The vertical transfer electrode 4 also functions as a read gate electrode. The vertical transfer electrodes 3 and 4 are vertical CCDs.
Although illustrated as being formed only on the register 102, the photodiodes 10 vertically adjacent to each other are actually illustrated.
1 and are common to the pixels in the same horizontal row. Note that, above the vertical transfer electrodes 3 and 4,
A light shielding film (not shown) for shielding the vertical CCD register 102 from light through an insulating film is provided. here,
The aspect ratio of the pixel is 1: 2,
Other configurations are the same as those of the conventional pixel shown in FIG. Also, the driving method is the same as the conventional one.

FIG. 2 shows a pixel according to the first embodiment of the present invention as H
FIG. 2 is a pixel array diagram of a solid-state imaging device adapted to the DTV format.

The aspect ratio (aspect ratio) of the effective image pickup area 11 is 9:16. For example, if the unit pixel size is 10.
By setting 4 μm (H) × 5.2 μm (V) and the number of effective pixels to 923 (H) × 1035 (V), HDTV
A 2/3 inch 1 million pixel CCD image sensor corresponding to the system can be constructed.

FIG. 3 is a schematic plan view for explaining a configuration of a unit pixel in a solid-state imaging device suitable for a non-interlace system according to a second embodiment of the present invention.

Here, the unit pixel is formed by arranging two pixels corresponding to the interlace system shown in FIG. 1 in the vertical direction, and is characterized in that it is a square pixel having an aspect ratio of 1: 1. is there. The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. Since four square transfer electrodes are included in the square pixels, one pixel corresponds to one transfer stage, and signals of all pixels can be read and transferred simultaneously and independently. Therefore, it can be applied to the non-interlace method. It should be noted that the signal amount per pixel of the square pixel is such that the signals of the two photodiodes 101 correspond to the vertical CCD register 1.
02 corresponds to the value added. It goes without saying that the addition of the signals of the two photodiodes 101 can be performed in the same manner as the vertical two-pixel addition performed by the conventional interlace method.

FIG. 4 is a pixel arrangement diagram of a solid-state imaging device in which square pixels according to the second embodiment of the present invention are adapted to the VGA format.

The aspect ratio (aspect ratio) of the effective image pickup area 21 is 3: 4. For example, if the unit pixel size is 10.4
μm (H) × 10.4 μm (V) and the number of effective pixels to be 640 (H) × 480 (V), so that approximately 1 / 2-inch 300,000 pixel CC compatible with the VGA format
A D image sensor can be configured. That is, by using unit pixels suitable for the interlace method shown in FIG.
Since the square pixel shown in FIG.
It is possible to develop two types of CCD image sensors for television and for multimedia in a short time.

[0045]

According to the present invention, the following effects can be obtained. The aspect ratio of the pixel corresponding to the interlace method including the vertical transfer electrode corresponding to the 1/2 transfer stage of the vertical CCD register is set to 1: 2. On the other hand, a unit pixel is formed by arranging two pixels corresponding to the interlace method in the vertical direction to form a square pixel, and within the square pixel, a vertical transfer electrode corresponding to one transfer stage of a vertical CCD register is provided. Is included, so that all pixels can be read simultaneously, and it is possible to support a non-interlace method. In other words, the basic configuration of pixels can be shared by two types of CCD image sensors, the interlaced type and the non-interlaced type, so that for a television and a multi-type in a period substantially equivalent to developing one type of device. 2 for media
Different types of devices can be developed.

[Brief description of the drawings]

FIG. 1 is a schematic plan view illustrating a configuration of a unit pixel in a solid-state imaging device suitable for an interlaced system according to a first embodiment of the present invention.

FIG. 2 is a pixel array diagram of a solid-state imaging device in which pixels according to the first embodiment of the present invention are adapted to the HDTV format.

FIG. 3 is a schematic plan view illustrating a configuration of a unit pixel in a solid-state imaging device suitable for a non-interlaced system according to a second embodiment of the present invention.

FIG. 4 is a pixel array diagram of a solid-state imaging device according to a second embodiment of the present invention in which square pixels are adapted to a VGA format.

FIG. 5 is a block diagram showing a general interline CCD solid-state imaging device.

FIG. 6 is a schematic diagram for explaining an interlace method.

FIG. 7 is a pixel array diagram of a solid-state imaging device conforming to the HDTV format.

FIG. 8 is a schematic plan view illustrating a configuration of a unit pixel of a conventional solid-state imaging device suitable for an interlaced system.

9 is a cross-sectional view illustrating correspondence between electrodes of a vertical CCD register and drive pulses in the solid-state imaging device having the unit pixels illustrated in FIG.

10A and 10B are diagrams for explaining a charge transfer operation in a four-phase driven vertical CCD register. FIG. 10A is a timing chart of transfer pulses applied to each vertical transfer electrode, and FIG. Each time t1 in FIG.
It is a channel electric potential diagram of the lower part of each vertical transfer electrode corresponding to -t9.

FIG. 11 is a schematic diagram for explaining a non-interlace method.

FIG. 12 is a pixel array diagram of a solid-state imaging device conforming to the VGA format.

FIG. 13 is a schematic plan view illustrating a configuration of a unit pixel of a solid-state imaging device suitable for a non-interlace method.

14 is a cross-sectional view showing the correspondence between electrodes of a vertical CCD register and drive pulses in the solid-state imaging device having the unit pixels shown in FIG.

FIG. 15 is a diagram for explaining a charge transfer operation from a vertical CCD register to a horizontal CCD register;
15A is a timing chart of a transfer pulse applied to each transfer electrode in a horizontal blanking period, and FIG. 15B is a channel potential diagram under each electrode corresponding to each time t1 to t9 in FIG. It is.

[Explanation of symbols]

1, 121, 151 element isolation region 2, 122, 152 read gate region 3, 4, 123, 124, 153 to 156 vertical transfer electrode 101 photodiode 102 vertical CCD register 103 horizontal CCD register 104 charge detection unit 105 output amplifier 106 unit Pixels 111, 141 Effective imaging area 131, 161 Semiconductor substrate 132 Insulating film

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[Procedure amendment]

[Submission date] September 7, 1998

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

[Title of the Invention] Solid-state imaging device

[Claims]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD type two-dimensional solid-state imaging device, and more particularly, to a solid-state imaging device having a pixel configuration for developing both television and multimedia devices in a short period of time. .

[0002]

2. Description of the Related Art A conventional technique will be described below with reference to FIGS.

FIG. 5 shows a general interline transfer type solid-state imaging device.

This solid-state imaging device comprises a plurality of photodiodes 101 for photoelectric conversion and a photodiode 1
01, a vertical CCD register 102 for receiving and transferring the charge from the vertical CCD register 102, a horizontal CCD register 103 for receiving and transferring the charge from the vertical CCD register 102,
The charge detection unit 104 includes a charge detection unit 104 that detects charges transferred by the CD register 103 and an output amplifier 105 that outputs an electric signal corresponding to the charges detected by the charge detection unit 104. Here, the portion surrounded by the two-dot chain line is the unit pixel 106.

FIG. 6 is a schematic diagram for explaining the interlace method.

Many of the solid-state imaging devices developed so far correspond to an interlace system (also called an interlaced scanning system) in order to be adapted for television use. Here, it is assumed that each horizontal line corresponds to each row of the photodiode. 1 frame (screen) is 2
The first field is composed of odd-numbered horizontal lines, and the second field is composed of even-numbered horizontal lines. The technique of suppressing the screen flicker called flicker by doubling the number of screens by skipping scanning every other line in this manner is generally used in television.

FIG. 7 is a pixel arrangement diagram of a solid-state imaging device conforming to the HDTV format.

[0008] The aspect ratio (aspect ratio) of the effective imaging area 111 is 9:16. 2/3 compatible with HDTV system
In the case of a 1.3-million pixel CCD image sensor, the number of effective pixels is 1258 (H) × 1035 (V), and the unit pixel size is 7.6 μm (H) × 5.2 μm (V). As described above, the unit pixel of the solid-state imaging device conforming to the television format is generally not a square pixel,
The aspect ratio differs depending on the optical format and the number of pixels.

FIG. 8 is a schematic plan view for explaining a configuration of a unit pixel of a conventional solid-state imaging device suitable for the interlaced system.

The unit pixel includes a photodiode 101,
A vertical CCD register 102 and a photodiode 101
An element isolation region 121 for isolating the vertical CCD register 102 from the vertical CCD register 102;
And a read gate region 122 for reading signal charges into the D register 102. The vertical CCD register 102 is provided with vertical transfer electrodes 123 and 124. The vertical transfer electrode 124 also functions as a read gate electrode. Also, the vertical transfer electrodes 123,
Although 124 is depicted as being formed only on the vertical CCD register 102, it actually extends between the photodiodes 101 adjacent vertically above and below in the drawing , and is shared by pixels in the same horizontal row. It has become. Note that a light-shielding film (not shown) for shielding the vertical CCD register 102 from light is provided above the vertical transfer electrodes 123 and 124 via an insulating film.

FIG. 9 is a sectional view showing the correspondence between the electrodes of the vertical CCD register and the driving pulses in the solid-state imaging device having the unit pixels shown in FIG.

Here, a case is shown in which the vertical CCD register is driven by four-phase pulses (φV1 to φV4).
Vertical transfer electrodes 123 and 124 are provided on the surface of the semiconductor substrate 131 via an insulating film 132. As shown in FIG. 8, two vertical transfer electrodes 123 and 124 are provided for one pixel.
Are included, one transfer stage is constituted by four vertical transfer electrodes corresponding to two pixels. Because the four-phase pulse
This is because it is driven by.

FIG. 10 is a diagram for explaining a charge transfer operation in a four-phase driven vertical CCD register. FIG. 10A is a timing chart of transfer pulses applied to each vertical transfer electrode, and FIG. 12) is a channel potential diagram under each vertical transfer electrode corresponding to each of the times t1 to t9 in FIG. Here, the channel potential is positive on the lower side of the drawing. In order to simplify the description, the transfer of only one packet of signal charges will be described.

At time t1, signal charges are accumulated in the channel below the vertical transfer electrode to which φV3 and φV4, to which the transfer pulse is at a high level, are applied. Time t2
Then, φV1 further becomes a high level, and the signal charge becomes 3
It is stored in the channel below the electrode. At time t3, φV3 goes low, and signal charges are accumulated in the channel below the two electrodes to which φV4 and φV1 are applied. That is, in the transition from time t1 to t3, the position of the signal charge has moved by one electrode. Hereinafter, similarly, the signal charges move by four electrodes (corresponding to one transfer stage) from time t1 to time t9. This repeated operation, the signal charges are transferred in the vertical CCD register 102.

As can be seen from the transfer form shown in FIG.
In the pixels of the type shown in (1), the signals of all the pixels cannot be read and transferred simultaneously and independently. Normally, signal charges of two pixels adjacent in the vertical direction are transferred to the vertical CCD register 1
02 is added and output. As a result, although the resolution in the vertical direction is deteriorated as compared with the case where all pixels are read out independently, the signal amount is doubled, so that an image with a good S / N is obtained. In addition, the combination of two pixels in the vertical direction for each field is shifted by one pixel and added, thereby supporting the interlace method.

On the other hand, a non-interlace type (also called a progressive scanning type or a progressive scanning type) solid-state imaging device is preferable for adapting to an image input device in a multimedia device which has been actively developed in recent years. This is because still images are often handled in multimedia applications, and higher resolution is required.

FIG. 11 is a schematic diagram for explaining the non-interlace method.

Here, each horizontal line corresponds to each row of the photodiode. One frame (screen) is composed of all the horizontal lines scanned sequentially, so that high-resolution image quality can be obtained. Furthermore, in processing an image such as a rotation process, a square pixel that can omit a pixel aspect ratio correction circuit is preferable.

FIG. 12 is a pixel array diagram of a solid-state imaging device conforming to the SXGA format.

The aspect ratio of the effective imaging area 141 is 4:
5 SXGA compatible 2/3 inch 1.3 million pixels C
In the case of a CD image sensor, the number of effective pixels is 1280
(H) × 1024 (V), unit pixel size is 6.7 μm
(H) × 6.7 μm (V). As described above, square pixels are mainly used as unit pixels of a solid-state imaging device suitable for multimedia use.

FIG. 13 is a schematic plan view for explaining a configuration of a unit pixel of a solid-state imaging device suitable for a non-interlace system.

The unit pixel includes a photodiode 101,
A vertical CCD register 102 and a photodiode 101
An element isolation region 151 for isolating the vertical CCD register 102 from the vertical CCD register 102;
And a read gate region 152 for reading signal charges into the D register 102. The vertical CCD register 102 is provided with vertical transfer electrodes 153 to 156. The vertical transfer electrode 155 also functions as a read gate electrode. Also, the vertical transfer electrodes 153 to 15
Although 6 is depicted as being formed only on the vertical CCD register 102, it actually extends between the photodiodes 101 that are vertically adjacent to each other in the drawing , and is common to pixels in the same horizontal row. It has become. Note that the vertical transfer electrodes 153 to 156 have a vertical CC
A light shielding film (not shown) for shielding the D register 102 from light is provided.

FIG. 14 is a sectional view showing the correspondence between the electrodes of the vertical CCD register and the driving pulses in the solid-state imaging device having the unit pixels shown in FIG.

Here, a case is shown in which the vertical CCD register is driven by four-phase pulses (φV1 to φV4).
Vertical transfer electrodes 153 to 156 are provided on the surface of the semiconductor substrate 161 via an insulating film 162. As shown in FIG. 13, four vertical transfer electrodes 153 to 15 are provided for one pixel.
6 is included, and this constitutes one transfer stage. In this manner, by associating one transfer stage with one pixel, signals of all pixels can be read and transferred simultaneously and independently. Simultaneous readout of all pixels is a necessary function for adapting to the non-interlace method.

[0025]

As described above, the configuration of a pixel suitable for a television system and the configuration of a pixel suitable for a multimedia application are different from each other. It is not an exaggeration to say that in developing a CCD image sensor, most of the time spent optimizing the characteristics of pixels is spent. Therefore, there is a problem that it takes about twice as long to develop both of the above two types of CCD image sensors if it is simply calculated .

As one method for solving this problem, there is a method disclosed in Japanese Patent Application Laid-Open No. 7-143410. This method uses pixels suitable for multimedia applications.
By arranging them in a television format (for example, an aspect ratio of 9:16 for HDTV, and an aspect ratio of 3: 4 for NTSC), the development period of two types of CCD easy sensors is shortened.

However, since this method is based on square pixels capable of simultaneously reading out all pixels, each signal charge is equivalent to one photodiode when interlaced driving is performed, and sufficient S / N can be obtained. There is no problem. In a four-phase drive vertical CCD register, the number of drive pulses must be increased to at least five or more in order to add signal charges of two photodiodes adjacent in the vertical direction in the vertical CCD register. This is not preferable because the number and the number of drive circuits increase.

As a method of adding the signal charges of two photodiodes adjacent in the vertical direction without increasing the types of driving pulses, there is a method of adding the signal charges by a horizontal CCD register. Hereinafter, this method will be described.

FIG. 15 shows the relationship between the vertical CCD register and the horizontal C register.
FIG. 5 is a diagram for explaining a charge transfer operation to a CD register. FIG. 15A is a timing chart of a transfer pulse applied to each transfer electrode in a horizontal blanking period. FIG. 15B shows each time t1 in FIG.
It is a channel electric potential diagram of each electrode lower part corresponding to -t9. Here, the channel potential is positive on the lower side of the drawing.
Note that, for simplicity of description, a state of transfer of only the signal charges A and B of two photodiodes adjacent in the vertical direction will be described.

At time t1, signal charges A and B are accumulated in channels below the vertical transfer electrodes to which φV3 and φV4 whose transfer pulse is at a high level are applied , respectively. At time t2, φV1 further goes to the high level, and the signal charge A is transferred toward the lower portion of the horizontal transfer electrode to which φV1 at the high level is applied.
The transfer of the signal charge B is the same as the normal vertical transfer described with reference to FIG. Thereafter, at time t5, φV1 becomes low level, and the signal charge A is almost completely transferred to the lower portion of the horizontal transfer electrode. Similarly,
The signal charge B is transferred to the lower part of the horizontal transfer electrode by the vertical transfer pulse group in the second cycle in the horizontal blanking period. At this time, since the signal charge A remains below the horizontal transfer electrode, as shown at time t9, as a result, the signal charge A
And the signal charge B are added.

However, such a horizontal CCD register 1
There is a problem with the addition of the signal charges at 03 . That is, a vertical transfer pulse group of about two cycles must be inserted within the horizontal blanking period limited by the television standard. When a local transfer failure from the vertical CCD register 102 to the horizontal CCD register 103 occurs, a black line is generated in a vertical direction on a reproduced image, and the image quality is significantly deteriorated. To suppress the local transfer failure, transfer pulses applied to the final vertical electrodes the period P from becoming to the low level before starting the horizontal transfer, it is necessary to ensure as long as possible. However, when two vertical transfer pulse groups are inserted, it is apparent that the period P is significantly reduced, and therefore, there is a problem that black line defects are extremely likely to occur.

[0032]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a square pixel capable of simultaneously reading out all pixels based on a pixel structure suitable for an interlace system used in a CCD image sensor for television, and to provide a CCD for multimedia. An object of the present invention is to provide a solid-state imaging device capable of developing an image sensor in a short time.

[0033]

That SUMMARY OF THE INVENTION The solid-state imaging device of the present invention, the vertical transfers receive charge from that converts photoelectrically off photodiode and the full <br/> photodiode C
An imaging area in which unit pixels including a CD register are two-dimensionally arranged; a horizontal CCD register for receiving and transferring charges from the vertical CCD register; a charge detection unit for detecting charges from the horizontal CCD register; An output amplifier that outputs an electric signal corresponding to the electric charge detected by the electric charge detection unit. Then, the unit pixel
Vertical Horizontal ratio of 1: 2 der is, a one-pixel one of the unit pixels
To support the interlaced system
Non-interlaced with two vertical pixels as one pixel
It corresponds to the method . At this time, one transfer stage of the vertical CCD register may be constituted by vertical transfer electrodes for two pixels of the unit pixel.

Further, the solid-state imaging device of the present invention, the unit pixel including the vertical CCD registers for transferring receive charge from full photodiode and the photodiode you photoelectric conversion <br/> are arranged two-dimensionally Imaging area and the vertical C
Horizontal CC that receives and transfers charge from CD register
It includes a D register, a charge detecting section for detecting charges from the horizontal CCD register, and an output amplifier for outputting an electric signal corresponding to the charges detected by the charge detecting section. Then, the unit pixel aspect ratio including vertical transfer electrode corresponding to 1/2 transfer stage of said vertical CCD registers l: a pixel is 2, Ri square pixel der that two vertically arranged, the Interlacing one pixel as one pixel
And two pixels in the vertical direction
It is characterized in that one pixel corresponds to the non-interlace method .

According to the present invention, except that the aspect ratio is 1: 2, since the pixel configuration is the same as the conventional one suitable for the interlacing method, the signal charges of two pixels adjacent in the vertical direction are transferred to the vertical CCD. It can be easily added by a register. Therefore, the problem of black line failure does not occur. A pixel having an aspect ratio of 1: 2 and two pixels arranged in the vertical direction is regarded as a unit pixel, and becomes a square pixel. In the square pixel, a vertical pixel register corresponding to one transfer stage of a vertical CCD register is provided. Since the transfer electrodes are included, all pixels can be read simultaneously and can be compatible with the non-interlace method.

That is, the basic configuration of the pixel is divided into two types of CCDs, an interlaced type and a non-interlaced type.
Since the image sensor can be used in common, two types of devices for television and multimedia can be developed in a period substantially equivalent to developing one type of device.

[0037]

FIG. 1 is a schematic plan view for explaining a configuration of a unit pixel in a solid-state imaging device suitable for an interlace system according to a first embodiment of the present invention.

The unit pixel includes a photodiode 101,
A vertical CCD register 102 and a photodiode 101
And a vertical CCD register 102, and a read gate area 2 for reading signal charges from the photodiode 101 to the vertical CCD register 102. Vertical CCD register 1
02 is provided with vertical transfer electrodes 3 and 4. The vertical transfer electrode 4 also functions as a read gate electrode. Although the vertical transfer electrodes 3 and 4 are depicted as being formed only on the vertical CCD register 102,
In practice it extends also between the photodiode 101 adjacent the drawings vertically, are common in the pixels to the same horizontal row. Note that a light-shielding film (not shown) for shielding the vertical CCD register 102 from light is provided above the vertical transfer electrodes 3 and 4 via an insulating film. Here, the feature is that the aspect ratio of the pixel is 1: 2, and the other configuration is the same as that of the conventional pixel shown in FIG. Also, the driving method is the same as the conventional one.

FIG. 2 shows a pixel according to the first embodiment of the present invention as H
FIG. 2 is a pixel array diagram of a solid-state imaging device adapted to the DTV format.

The aspect ratio (aspect ratio) of the effective image pickup area 11 is 9:16. For example, if the unit pixel size is 10.
By setting 4 μm (H) × 5.2 μm (V) and the number of effective pixels to 923 (H) × 1035 (V), HDTV
A 2/3 inch 1 million pixel CCD image sensor corresponding to the system can be constructed.

FIG. 3 is a schematic plan view for explaining a configuration of a unit pixel in a solid-state imaging device suitable for a non-interlace system according to a second embodiment of the present invention.

Here, the unit pixel is formed by arranging two pixels corresponding to the interlace system shown in FIG. 1 in the vertical direction, and is characterized in that it is a square pixel having an aspect ratio of 1: 1. is there. The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. Since four square transfer electrodes are included in the square pixels, one pixel corresponds to one transfer stage, and signals of all pixels can be read and transferred simultaneously and independently. Therefore, it can be applied to the non-interlace method. It should be noted that the signal amount per pixel of the square pixel is such that the signals of the two photodiodes 101 correspond to the vertical CCD register 1.
02 corresponds to the value added. It goes without saying that the addition of the signals of the two photodiodes 101 can be performed in the same manner as the vertical two-pixel addition performed by the conventional interlace method.

FIG. 4 is a pixel arrangement diagram of a solid-state imaging device in which square pixels according to the second embodiment of the present invention are adapted to the VGA format.

The aspect ratio (aspect ratio) of the effective image pickup area 21 is 3: 4. For example, if the unit pixel size is 10.4
μm (H) × 10.4 μm (V) and the number of effective pixels to be 640 (H) × 480 (V), so that approximately 1 / 2-inch 300,000 pixel CC compatible with the VGA format
A D image sensor can be configured. That is, by using unit pixels suitable for the interlace method shown in FIG.
Since the square pixel shown in FIG.
It is possible to develop two types of CCD image sensors for television and for multimedia in a short time.

[0045]

According to the present invention, the following effects can be obtained. The aspect ratio of the pixel corresponding to the interlace method including the vertical transfer electrode corresponding to the 1/2 transfer stage of the vertical CCD register is set to 1: 2. On the other hand, a unit pixel is formed by arranging two pixels corresponding to the interlace method in the vertical direction to form a square pixel, and within the square pixel, a vertical transfer electrode corresponding to one transfer stage of a vertical CCD register is provided. Is included, so that all pixels can be read simultaneously, and it is possible to support a non-interlace method. In other words, the basic configuration of pixels can be shared by two types of CCD image sensors, the interlaced type and the non-interlaced type, so that for a television and a multi-type in a period substantially equivalent to developing one type of device. 2 for media
Different types of devices can be developed.

[Brief description of the drawings]

FIG. 1 is a schematic plan view illustrating a configuration of a unit pixel in a solid-state imaging device suitable for an interlaced system according to a first embodiment of the present invention.

FIG. 2 is a pixel array diagram of a solid-state imaging device in which pixels according to the first embodiment of the present invention are adapted to the HDTV format.

FIG. 3 is a schematic plan view illustrating a configuration of a unit pixel in a solid-state imaging device suitable for a non-interlaced system according to a second embodiment of the present invention.

FIG. 4 is a pixel array diagram of a solid-state imaging device according to a second embodiment of the present invention in which square pixels are adapted to a VGA format.

FIG. 5 is a block diagram showing a general interline CCD solid-state imaging device.

FIG. 6 is a schematic diagram for explaining an interlace method.

FIG. 7 is a pixel array diagram of a solid-state imaging device conforming to the HDTV format.

FIG. 8 is a schematic plan view illustrating a configuration of a unit pixel of a conventional solid-state imaging device suitable for an interlaced system.

9 is a cross-sectional view illustrating correspondence between electrodes of a vertical CCD register and drive pulses in the solid-state imaging device having the unit pixels illustrated in FIG.

10A and 10B are diagrams for explaining a charge transfer operation in a four-phase driven vertical CCD register. FIG. 10A is a timing chart of transfer pulses applied to each vertical transfer electrode, and FIG. Each time t1 in FIG.
It is a channel electric potential diagram of the lower part of each vertical transfer electrode corresponding to -t9.

FIG. 11 is a schematic diagram for explaining a non-interlace method.

FIG. 12 is a pixel array diagram of a solid-state imaging device conforming to the VGA format.

FIG. 13 is a schematic plan view illustrating a configuration of a unit pixel of a solid-state imaging device suitable for a non-interlace method.

14 is a cross-sectional view showing the correspondence between electrodes of a vertical CCD register and drive pulses in the solid-state imaging device having the unit pixels shown in FIG.

FIG. 15 is a diagram for explaining a charge transfer operation from a vertical CCD register to a horizontal CCD register;
15A is a timing chart of a transfer pulse applied to each transfer electrode in a horizontal blanking period, and FIG. 15B is a channel potential diagram under each electrode corresponding to each time t1 to t9 in FIG. It is.

[Description of Signs] 1, 121, 151 Element isolation region 2, 122, 152 Read gate region 3, 4, 123, 124, 153 to 156 Vertical transfer electrode 101 Photodiode 102 Vertical CCD register 103 Horizontal CCD register 104 Charge detector 105 output amplifier 106 unit pixel 111, 141 effective imaging area 131, 161 semiconductor substrate 132 insulating film

Claims (3)

[Claims] 1. An imaging area in which unit pixels including a plurality of photodiodes for photoelectric conversion and a vertical CCD register for receiving and transferring electric charges from these photodiodes are two-dimensionally arranged; A solid-state image sensor comprising: a horizontal CCD register for receiving and transferring charges; a charge detection unit for detecting charges from the horizontal CCD register; and an output amplifier for outputting an electric signal corresponding to the charges detected by the charge detection unit. The solid-state imaging device according to claim 1, wherein an aspect ratio of a dimension of the unit pixel is 1: 2. 2. An imaging area in which unit pixels including a plurality of photodiodes for photoelectric conversion and a vertical CCD register for receiving and transferring electric charges from these photodiodes are two-dimensionally arranged. A solid-state image sensor comprising: a horizontal CCD register for receiving and transferring charges; a charge detection unit for detecting charges from the horizontal CCD register; and an output amplifier for outputting an electric signal corresponding to the charges detected by the charge detection unit. In the image pickup apparatus, one transfer stage of the vertical CCD register is a unit pixel of 2
A solid-state imaging device comprising vertical transfer electrodes for pixels, wherein the aspect ratio of the dimensions of the unit pixel is 1: 2. 3. An imaging area in which unit pixels including a plurality of photodiodes for performing photoelectric conversion and a vertical CCD register for receiving and transferring electric charges from these photodiodes are two-dimensionally arranged. A solid-state image sensor comprising: a horizontal CCD register for receiving and transferring charges; a charge detection unit for detecting charges from the horizontal CCD register; and an output amplifier for outputting an electric signal corresponding to the charges detected by the charge detection unit. In the imaging apparatus, the unit pixel is a square pixel in which two pixels having an aspect ratio of 1: 2 including a vertical transfer electrode corresponding to a half transfer stage of the vertical CCD register are arranged in a vertical direction. Characteristic solid-state imaging device.