JPH11204549A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH11204549A JPH11204549A JP10004697A JP469798A JPH11204549A JP H11204549 A JPH11204549 A JP H11204549A JP 10004697 A JP10004697 A JP 10004697A JP 469798 A JP469798 A JP 469798A JP H11204549 A JPH11204549 A JP H11204549A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- integrated circuit
- circuit chip
- semiconductor integrated
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【0001】[0001]
【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、より詳しくは半導体集積回路チップを配線基
板のおもて面に実装し、さらに半導体集積回路チップを
樹脂封止し、そのうえ配線基板のうら面にマザーボード
と接続するためのハンダボール端子を備えるプラスチッ
ク・ボール・グリッド・アレイの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to mounting a semiconductor integrated circuit chip on a front surface of a wiring board, further sealing the semiconductor integrated circuit chip with a resin, and furthermore, The present invention relates to a method of manufacturing a plastic ball grid array having solder ball terminals for connecting to a motherboard on the back surface.
【0002】[0002]
【従来の技術】一般的に、半導体集積回路チップは半導
体パッケージに封止して使用する。この半導体パッケー
ジの役割は半導体集積回路チップの各電極とマザーボー
ドとの電気的接続と、半導体集積回路チップの放熱と保
護などである。2. Description of the Related Art Generally, a semiconductor integrated circuit chip is used by being sealed in a semiconductor package. The role of this semiconductor package is to electrically connect each electrode of the semiconductor integrated circuit chip to the motherboard, and to radiate and protect the semiconductor integrated circuit chip.
【0003】この半導体パッケージの一種であるプラス
チック・ボール・グリッド・アレイ(以下PBGAと記
載する)は樹脂成分を主たる構成材料とする配線基板上
に半導体集積回路チップを実装し、マザーボードと接続
するためのハンダボール端子を有し、さらに半導体集積
回路チップの周囲を樹脂封止した構造をもつ。[0003] A plastic ball grid array (hereinafter referred to as PBGA), which is a type of semiconductor package, is used to mount a semiconductor integrated circuit chip on a wiring board mainly composed of a resin component and connect it to a motherboard. And has a structure in which the periphery of the semiconductor integrated circuit chip is resin-sealed.
【0004】このPBGAは半導体パッケージの小型化
と電気特性と実装歩留まりの点で他に比べて有利な構造
を備えており、携帯型電話やポケットベルや携帯型電子
計算機などの分野で採用されている。The PBGA has a structure that is more advantageous than others in terms of miniaturization of semiconductor packages, electrical characteristics, and mounting yield, and has been adopted in fields such as portable telephones, pagers, and portable computers. I have.
【0005】以下、図面に基づいて従来の技術における
PBGAの製造工程について説明する。図1は従来のP
BGA12の構造を示す断面図であり、図2は樹脂基板
1上の銅パターンを示す平面図である。[0005] A process for manufacturing a PBGA according to the prior art will be described below with reference to the drawings. FIG. 1 shows a conventional P
FIG. 2 is a cross-sectional view illustrating the structure of the BGA 12, and FIG. 2 is a plan view illustrating a copper pattern on the resin substrate 1.
【0006】図1に示す樹脂基板1は、その平面形状が
ほぼ四角形で、板厚が0.3mm程度の樹脂材料からな
る。樹脂基板1の材料としてはエポキシ樹脂やポリイミ
ド樹脂などの樹脂材料があげられるが、望ましくはガラ
ス繊維を含浸した熱硬化性のエポキシ樹脂である。The resin substrate 1 shown in FIG. 1 has a substantially square planar shape and is made of a resin material having a thickness of about 0.3 mm. Examples of the material of the resin substrate 1 include a resin material such as an epoxy resin and a polyimide resin, and preferably a thermosetting epoxy resin impregnated with glass fiber.
【0007】この樹脂基板1の熱硬化性エポキシ樹脂が
半硬化状態のうちに、おもて面とうら面とに厚さ18μ
m程度の銅箔を貼る。While the thermosetting epoxy resin of the resin substrate 1 is in a semi-cured state, the front and back surfaces have a thickness of 18 μm.
Paste copper foil of about m.
【0008】つぎに銅箔を貼った樹脂基板1のおもて面
とうら面とを加圧しながら同時に加熱し熱硬化性エポキ
シ樹脂の硬化を完了させることで樹脂基板1のおもて面
とうら面に銅箔を固着する。Next, the front surface and the back surface of the resin substrate 1 on which the copper foil is adhered are simultaneously heated while applying pressure to complete the curing of the thermosetting epoxy resin. Fix the copper foil on the back side.
【0009】その後、複数のスルーホール2を切削ドリ
ルなどの穴あけ手段により設ける。さらにスルーホール
2の壁面を含む樹脂基板1表面を洗浄し、樹脂基板1の
全面に無電界メッキ処理および電解メッキ処理により銅
メッキ層を設ける。このメッキ層はスルーホール2内面
まで施す。Thereafter, a plurality of through holes 2 are provided by a drilling means such as a cutting drill. Further, the surface of the resin substrate 1 including the wall surfaces of the through holes 2 is cleaned, and a copper plating layer is provided on the entire surface of the resin substrate 1 by electroless plating and electrolytic plating. This plating layer is applied up to the inner surface of the through hole 2.
【0010】前述のように、おもて面とうら面に銅のう
す膜層を設けた樹脂基板1にエッチングマスクとエッチ
ング液を用いてエッチング処理を行う。このエッチング
処理により、図2に示すように樹脂基板1のおもて面に
半導体集積回路チップ7の各電極と電気的に接続するた
めの基板電極3と電気的経路を銅パターンとして設け
る。As described above, an etching process is performed on the resin substrate 1 having the copper thin film layer provided on the front and back surfaces using an etching mask and an etching solution. By this etching process, as shown in FIG. 2, a substrate electrode 3 for electrically connecting to each electrode of the semiconductor integrated circuit chip 7 and an electric path are provided as a copper pattern on the front surface of the resin substrate 1.
【0011】図2に示すように、基板電極3は、後の工
程で固着する半導体集積回路チップ7の外周を取り囲む
ようにして設ける。As shown in FIG. 2, the substrate electrode 3 is provided so as to surround the outer periphery of the semiconductor integrated circuit chip 7 to be fixed in a later step.
【0012】さらに、このエッチング処理により、樹脂
基板1のおもて面に基板電極3とスルーホール2を電気
的に接続するための電気的経路を銅パターンとして設け
る。Further, by this etching process, an electric path for electrically connecting the substrate electrode 3 and the through hole 2 is provided on the front surface of the resin substrate 1 as a copper pattern.
【0013】さらに、このエッチング処理により、樹脂
基板1のうら面にハンダボール端子11をハンダ付けす
るためのパッド電極4を銅パターンとして設ける。その
うえ樹脂基板1のうら面にパッド電極4とスルーホール
2を電気的に接続するための図示しない電気的経路を銅
パターンとして設ける。Further, by this etching process, a pad electrode 4 for soldering the solder ball terminals 11 is provided on the back surface of the resin substrate 1 as a copper pattern. In addition, an electrical path (not shown) for electrically connecting the pad electrode 4 and the through hole 2 is provided on the back surface of the resin substrate 1 as a copper pattern.
【0014】つぎに、前述のようにエッチング処理して
銅パターンを設けた樹脂基板1のおもて面とうら面に、
電気的経路を保護するための樹脂絶縁膜5を設ける。樹
脂絶縁膜5の材料としてはアクリル変成エポキシなどの
感光性樹脂組成物があげられる。Next, the resin substrate 1 provided with the copper pattern by the etching process as described above is placed on the front and back surfaces.
A resin insulating film 5 for protecting an electric path is provided. Examples of the material of the resin insulating film 5 include a photosensitive resin composition such as an acrylic modified epoxy.
【0015】樹脂絶縁膜5の材料として感光性樹脂組成
物を用いた場合は、露光現像処理を行うことで、樹脂基
板1のおもて面の基板電極3の部分は露出し、その他の
銅パターンは被服するように樹脂絶縁膜5を設ける。When a photosensitive resin composition is used as the material of the resin insulating film 5, the substrate electrode 3 on the front surface of the resin substrate 1 is exposed by performing exposure and development treatments, and other copper The resin insulating film 5 is provided so as to cover the pattern.
【0016】また、樹脂基板1のうら面も露光現像処理
を行うことで、パッド電極4の部分は露出し、その他の
銅パターンは被服するように樹脂絶縁膜5を設ける。The back surface of the resin substrate 1 is also exposed and developed, so that the pad electrode 4 is exposed, and a resin insulating film 5 is provided so as to cover other copper patterns.
【0017】以上説明したように、図1に示す配線基板
6はおもて面に基板電極3と樹脂絶縁膜5を有してい
る。さらに配線基板6はうら面にパッド電極4と樹脂絶
縁膜5を有している。また配線基板6はおもて面の基板
電極3とうら面のパッド電極4とをスルーホール2と銅
パターンからなる電気的経路とを介して電気的に接続し
ている。As described above, the wiring substrate 6 shown in FIG. 1 has the substrate electrode 3 and the resin insulating film 5 on the front surface. Further, the wiring board 6 has the pad electrode 4 and the resin insulating film 5 on the back surface. Further, the wiring board 6 electrically connects the substrate electrode 3 on the front surface and the pad electrode 4 on the back surface via the through hole 2 and an electric path formed of a copper pattern.
【0018】つぎに、配線基板6のおもて面とうら面の
樹脂絶縁膜5から露出している銅パターンの表面に、2
μmから5μm程度のニッケル(Ni)メッキ層を設
け、その上層に0.5μm程度の導通性の優れる金(A
u)メッキ層を設ける。Next, the surface of the copper pattern exposed from the resin insulating film 5 on the front and back surfaces of the wiring board 6 is
A nickel (Ni) plating layer of about 5 μm to 5 μm is provided, and a gold (A)
u) providing a plating layer;
【0019】その後、半導体集積回路チップ7を熱硬化
性の樹脂組成物からなる接着剤8を加熱硬化すること
で、配線基板6のほぼ中央に固着する。接着剤8の材料
としては熱硬化性のエポキシ樹脂組成物があげられる。Thereafter, the semiconductor integrated circuit chip 7 is fixed to the center of the wiring substrate 6 by heating and curing an adhesive 8 made of a thermosetting resin composition. Examples of the material of the adhesive 8 include a thermosetting epoxy resin composition.
【0020】つぎに、半導体集積回路チップ7の各電極
と基板電極3を接続ワイヤー9を用いて電気的に接続す
る。接続ワイヤー9の材料として望ましいのは導通性の
優れる金(Au)ワイヤーである。Next, each electrode of the semiconductor integrated circuit chip 7 and the substrate electrode 3 are electrically connected by using the connection wire 9. Desirable as a material of the connection wire 9 is a gold (Au) wire having excellent conductivity.
【0021】その後、半導体集積回路チップ7の遮光と
保護を行うために、半導体集積回路チップ7と接続ワイ
ヤー9を熱硬化性の封止樹脂10を用いたトランスファ
ー・モールド成型方法により樹脂封止する。Thereafter, in order to shield and protect the semiconductor integrated circuit chip 7, the semiconductor integrated circuit chip 7 and the connection wires 9 are resin-sealed by a transfer molding method using a thermosetting sealing resin 10. .
【0022】つぎに配線基板6うら面のパッド電極4に
ハンダボールを供給し、加熱炉で加熱することにより、
ハンダボール端子11を設ける。このハンダボール端子
11は図示しないマザーボードの電極と電気的に接続す
るために用いる。図1に示す従来技術のPBGA12は
以上説明したような製造工程によって製造する。なお、
PBGA12は、半導体集積回路チップ7の各電極とハ
ンダボール端子11とを接続ワイヤー9と配線基板6を
介して電気的に接続している。Next, a solder ball is supplied to the pad electrode 4 on the back surface of the wiring board 6 and heated in a heating furnace.
A solder ball terminal 11 is provided. The solder ball terminals 11 are used to electrically connect to electrodes of a motherboard (not shown). The conventional PBGA 12 shown in FIG. 1 is manufactured by the manufacturing process described above. In addition,
The PBGA 12 electrically connects each electrode of the semiconductor integrated circuit chip 7 and the solder ball terminal 11 via the connection wire 9 and the wiring board 6.
【0023】[0023]
【発明が解決しようとする課題】従来技術のPBGA1
2は半導体パッケージの小型化と電気特性と実装歩留ま
りの点で、他に比べて有利な構造を備えている。The prior art PBGA1
2 has a structure that is more advantageous than others in terms of miniaturization of semiconductor packages, electrical characteristics, and mounting yield.
【0024】このPBGA12はハンダの融点以上に全
体加熱することによって、ハンダボール端子11を溶融
し、マザーボードの電極と電気的に接続する。このリフ
ローハンダ付けの際にPBGA12の接着剤8と配線基
板6を接着した部分で発生する剥離が問題となってい
る。The PBGA 12 is entirely heated to a temperature equal to or higher than the melting point of the solder, thereby melting the solder ball terminals 11 and electrically connecting them to the electrodes of the motherboard. At the time of this reflow soldering, peeling occurring at a portion where the adhesive 8 of the PBGA 12 and the wiring board 6 are bonded is a problem.
【0025】従来技術の製造方法では、接着剤8を用い
て半導体集積回路チップ7を配線基板6に固着する行程
で、配線基板6の表面に吸着した水分が接着剤8の硬化
温度の150℃程度に加熱されることで気化し、配線基
板6と接着剤8の界面に気泡が残る。In the manufacturing method of the prior art, in the step of fixing the semiconductor integrated circuit chip 7 to the wiring board 6 using the adhesive 8, the moisture adsorbed on the surface of the wiring board 6 is reduced to the curing temperature of the adhesive 8 of 150 ° C. By being heated to such an extent, it is vaporized and bubbles remain at the interface between the wiring board 6 and the adhesive 8.
【0026】前述のPBGA12完成後、マザーボード
に実装するリフローハンダ付け行程で、この配線基板6
と接着剤8の界面の気泡にPBGA12内の水分が気化
膨張して吹き出すことで配線基板6と接着剤8の界面に
剥離が発生する。After the above-described PBGA 12 is completed, the wiring board 6 is mounted in a reflow soldering process of mounting the wiring board 6 on a motherboard.
The moisture in the PBGA 12 is vaporized and expanded and blows out to the bubbles at the interface between the adhesive 8 and the adhesive 8, so that the interface between the wiring board 6 and the adhesive 8 is separated.
【0027】また、PBGA12のような表面実装型の
半導体パッケージは、熱膨張係数や弾性率などの材料特
性が異なる種々の材料を積層した構造からなる。とくに
熱膨張係数の材料間の差のため、リフローハンダ付けの
行程でPBGA12本体の温度が200℃以上に達する
と、積層した各材料の界面にせん断力が生じ、界面の密
着力が弱い場合は剥離が起きる。A surface-mount type semiconductor package such as the PBGA 12 has a structure in which various materials having different material characteristics such as a coefficient of thermal expansion and an elastic modulus are laminated. In particular, when the temperature of the PBGA12 body reaches 200 ° C. or more during the reflow soldering process due to the difference in thermal expansion coefficient between materials, a shear force is generated at the interface between the laminated materials, and when the adhesive force at the interface is weak, Peeling occurs.
【0028】前述のように、配線基板6と接着剤8の界
面に気泡があると、接着剤8の有効接着面積が減少し、
結果として界面の密着力が弱くなる。したがって、前述
のリフローハンダ付けの行程で配線基板6と接着剤8の
界面でせん断力による剥離が起きる。As described above, if air bubbles are present at the interface between the wiring board 6 and the adhesive 8, the effective bonding area of the adhesive 8 decreases,
As a result, the adhesion at the interface becomes weak. Therefore, in the above-described reflow soldering process, separation due to shearing force occurs at the interface between the wiring board 6 and the adhesive 8.
【0029】また、配線基板6と接着剤8の界面に気泡
が無い箇所でも、配線基板6と接着剤8の間に吸着水分
の層が介在するため密着力が弱くなる。したがって、前
述のリフローハンダ付けの行程で配線基板6と接着剤8
の吸着水分の層を介した接着面でせん断力による剥離が
起きる。Further, even in a place where there is no air bubble at the interface between the wiring board 6 and the adhesive 8, the adhesion force is weak because a layer of adsorbed moisture is interposed between the wiring board 6 and the adhesive 8. Therefore, the wiring board 6 and the adhesive 8 can be used in the reflow soldering process described above.
Peeling occurs due to shearing force on the bonding surface through the layer of adsorbed moisture.
【0030】この半導体集積回路チップ12下部の剥離
により、配線基板6がマザーボード側に膨れ実装が不可
能になったり、PBGA12内部の電気的経路が断線す
るなどの故障が発生し、半導体装置の信頼性を損なう致
命的な問題がある。The peeling of the lower portion of the semiconductor integrated circuit chip 12 causes the wiring board 6 to swell toward the motherboard, making it impossible to mount, or causing a failure such as disconnection of the electric path inside the PBGA 12, resulting in reliability of the semiconductor device. There is a fatal problem that impairs sex.
【0031】(発明の目的)そこで本発明の目的は、上
記課題を解決して、半導体集積回路チップの剥離が無
く、耐湿性に優れた半導体装置の製造方法を提供するこ
とである。(Object of the Invention) Accordingly, an object of the present invention is to solve the above-mentioned problems and to provide a method of manufacturing a semiconductor device which is free from peeling of a semiconductor integrated circuit chip and has excellent moisture resistance.
【0032】[0032]
【課題を解決するための手段】上記目的を達成するた
め、本発明においては、下記記載の半導体装置の製造方
法を採用する。In order to achieve the above object, the present invention employs the following method of manufacturing a semiconductor device.
【0033】本発明の半導体装置の製造方法は、樹脂成
分を主たる構成材料とする配線基板の表面に付着した水
分を除去する行程と、この配線基板に半導体集積回路チ
ップを接着剤を用いて固着する行程と、半導体集積回路
チップの各電極と配線基板に設ける基板電極とを導電性
のワイヤーで接続する行程と、半導体集積回路チップと
接続ワイヤーと基板電極を樹脂封止する行程と、配線基
板のうら面にマザーボードと接続するためのハンダボー
ルを設ける行程とを有することを特徴とする。According to the method of manufacturing a semiconductor device of the present invention, there is provided a process for removing moisture adhering to the surface of a wiring board whose main component is a resin component, and fixing a semiconductor integrated circuit chip to the wiring board using an adhesive. A step of connecting each electrode of the semiconductor integrated circuit chip to a substrate electrode provided on the wiring board with a conductive wire; a step of resin-sealing the semiconductor integrated circuit chip, the connection wire, and the substrate electrode; Providing a solder ball for connecting to the motherboard on the back surface.
【0034】本発明の半導体装置の製造方法において
は、樹脂成分を主たる構成材料とする配線基板の表面に
付着した水分を加熱除去する行程と、この配線基板に半
導体集積回路チップを接着剤を用いて固着する行程と、
半導体集積回路チップの各電極と配線基板に設ける基板
電極とを導電性のワイヤーで接続する行程と、半導体集
積回路チップと接続ワイヤーと基板電極を樹脂封止する
行程と、配線基板のうら面にマザーボードと接続するた
めのハンダボールを設ける行程とを有することを特徴と
する。In the method of manufacturing a semiconductor device according to the present invention, a step of heating and removing moisture adhering to the surface of a wiring board containing a resin component as a main constituent material, and using an adhesive to attach a semiconductor integrated circuit chip to the wiring board. And the process of sticking
A process of connecting each electrode of the semiconductor integrated circuit chip to a substrate electrode provided on the wiring board with a conductive wire, a process of resin-sealing the semiconductor integrated circuit chip, the connection wire, and the substrate electrode with a resin, Providing a solder ball for connecting to the motherboard.
【0035】本発明の半導体装置の製造方法において
は、樹脂成分を主たる構成材料とする配線基板の表面に
付着した水分を除去する行程と、この行程の終了後60
分以内に前記配線基板に半導体集積回路チップを接着剤
を用いて固着する行程と、半導体集積回路チップの各電
極と配線基板に設ける基板電極とを導電性のワイヤーで
接続する行程と、半導体集積回路チップと接続ワイヤー
と基板電極を樹脂封止する行程と、配線基板のうら面に
マザーボードと接続するためのハンダボールを設ける行
程とを有することを特徴とする。In the method of manufacturing a semiconductor device according to the present invention, a step of removing moisture adhering to the surface of the wiring board mainly composed of a resin component, and a step 60 after the end of this step.
Fixing the semiconductor integrated circuit chip to the wiring substrate using an adhesive within a minute; connecting each electrode of the semiconductor integrated circuit chip to a substrate electrode provided on the wiring substrate with a conductive wire; The method includes a step of resin-sealing the circuit chip, the connection wires, and the substrate electrodes, and a step of providing solder balls for connecting to the motherboard on the back surface of the wiring board.
【0036】本発明の半導体装置の製造方法は、樹脂成
分を主たる構成材料とする配線基板の表面に付着した水
分を加熱除去する行程と、この行程の終了後60分以内
に前記配線基板に半導体集積回路チップを接着剤を用い
て固着する行程と、半導体集積回路チップの各電極と配
線基板に設ける基板電極とを導電性のワイヤーで接続す
る行程と、半導体集積回路チップと接続ワイヤーと基板
電極を樹脂封止する行程と、配線基板のうら面にマザー
ボードと接続するためのハンダボールを設ける行程を有
することを特徴とする。The method of manufacturing a semiconductor device according to the present invention includes a step of heating and removing moisture adhering to the surface of a wiring board containing a resin component as a main constituent material, and a step of attaching the semiconductor to the wiring board within 60 minutes after the completion of this step. A step of fixing the integrated circuit chip using an adhesive, a step of connecting each electrode of the semiconductor integrated circuit chip to a substrate electrode provided on the wiring board with a conductive wire, a step of connecting the semiconductor integrated circuit chip, the connection wire, and the substrate electrode And a step of providing solder balls for connecting to the motherboard on the back surface of the wiring board.
【0037】(作用)本発明の半導体装置の製造方法
は、樹脂成分を主たる構成材料とする配線基板上に半導
体集積回路チップを接着剤を用いて固着する行程の直前
に、配線基板表面に付着した水分を除去する行程を有し
ている。(Function) In the method of manufacturing a semiconductor device according to the present invention, the semiconductor integrated circuit chip is adhered to the wiring board surface immediately before the step of fixing the semiconductor integrated circuit chip on the wiring board using a resin component as a main constituent material using an adhesive. It has a process of removing water that has been removed.
【0038】したがって、接着剤を用いて半導体集積回
路チップを配線基板に固着する行程で、配線基板の表面
に吸着した水分が接着剤の硬化温度の150℃程度に加
熱されることで気化し、配線基板と接着剤の界面に気泡
が残ることがない。したがって、PBGAをマザーボー
ドに実装するリフローハンダ付け行程で、前述の界面の
気泡にPBGA内の水分が気化膨張して吹き出すことが
なく、配線基板と接着剤の界面に剥離が発生しない。Therefore, in the process of fixing the semiconductor integrated circuit chip to the wiring substrate using the adhesive, the moisture adsorbed on the surface of the wiring substrate is vaporized by being heated to the curing temperature of the adhesive of about 150 ° C. No air bubbles remain at the interface between the wiring board and the adhesive. Therefore, in the reflow soldering process of mounting the PBGA on the motherboard, the moisture in the PBGA does not evaporate and expand to the bubbles at the interface, and the interface does not peel off at the interface between the wiring board and the adhesive.
【0039】さらに本発明の半導体装置の製造行程は、
配線基板表面に付着した水分を除去する行程の終了後6
0分以内に、配線基板上に半導体集積回路チップを接着
剤を用いて固着する。Further, the manufacturing process of the semiconductor device of the present invention is as follows.
After the end of the process of removing water adhering to the wiring board surface 6
Within 0 minutes, the semiconductor integrated circuit chip is fixed on the wiring substrate using an adhesive.
【0040】したがって、水分を除去した配線基板表面
に再び水分が付着する前に、半導体集積回路チップの固
着を完了する。このため接着剤の加熱硬化の行程で接着
剤と配線基板の界面に気泡が残留することがない。した
がって、PBGAをマザーボードに実装するリフローハ
ンダ付け行程で、前述の界面の気泡にPBGA内の水分
が気化膨張して吹き出すことがなく、配線基板と接着剤
の界面に剥離が発生しない。Therefore, before the moisture adheres again to the surface of the wiring board from which the moisture has been removed, the fixing of the semiconductor integrated circuit chip is completed. Therefore, no bubbles remain at the interface between the adhesive and the wiring board during the heating and curing process of the adhesive. Therefore, in the reflow soldering process of mounting the PBGA on the motherboard, the moisture in the PBGA does not evaporate and expand to the bubbles at the interface, and the interface does not peel off at the interface between the wiring board and the adhesive.
【0041】また、配線基板と接着剤の界面に気泡が残
留していないため、接着剤の有効接着面積を多く確保で
き、結果として界面の良好な密着力が得られる。このた
め、リフローハンダ付けの行程でPBGAを全体加熱し
ても、配線基板と接着剤の界面でせん断力による剥離が
発生しない。Further, since no air bubbles remain at the interface between the wiring board and the adhesive, a large effective adhesive area of the adhesive can be secured, and as a result, a good adhesion at the interface can be obtained. For this reason, even if the PBGA is entirely heated in the reflow soldering process, no separation due to shearing force occurs at the interface between the wiring substrate and the adhesive.
【0042】また、配線基板6と接着剤8の間に吸着水
分の層が介在しない密着の良好な接着が可能になる。こ
のため、リフローハンダ付けの行程でPBGAを全体加
熱しても、配線基板と接着剤の界面でせん断力による剥
離が発生しない。Further, good adhesion can be achieved without a layer of adsorbed moisture between the wiring board 6 and the adhesive 8. For this reason, even if the PBGA is entirely heated in the reflow soldering process, no separation due to shearing force occurs at the interface between the wiring substrate and the adhesive.
【0043】[0043]
【発明の実施の形態】以下図面に基づいて本発明の製造
方法の最適な実施形態について説明する。図1は本発明
の製造方法を採用する半導体装置の構造を示す断面図で
ある。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the manufacturing method of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing the structure of a semiconductor device employing the manufacturing method of the present invention.
【0044】図1に示す樹脂基板1は、その平面形状が
ほぼ四角形で、板厚が0.3mm程度の樹脂材料からな
る。樹脂基板1の材料としてはエポキシ樹脂やポリイミ
ド樹脂などの樹脂材料があげられるが、望ましくはガラ
ス繊維を含浸した熱硬化性のエポキシ樹脂である。この
樹脂基板1の熱硬化性エポキシ樹脂が半硬化状態のうち
に、おもて面とうら面とに厚さ18μm程度の銅箔を貼
る。The resin substrate 1 shown in FIG. 1 has a substantially square planar shape and is made of a resin material having a thickness of about 0.3 mm. Examples of the material of the resin substrate 1 include a resin material such as an epoxy resin and a polyimide resin, and preferably a thermosetting epoxy resin impregnated with glass fiber. While the thermosetting epoxy resin of the resin substrate 1 is in a semi-cured state, a copper foil having a thickness of about 18 μm is attached to the front and back surfaces.
【0045】つぎに銅箔を貼った樹脂基板1のおもて面
とうら面とを加圧しながら同時に加熱し熱硬化性エポキ
シ樹脂の硬化を完了させることで樹脂基板1のおもて面
とうら面に銅箔を固着する。Next, the front surface and the back surface of the resin substrate 1 on which the copper foil is adhered are simultaneously heated while applying pressure to complete the curing of the thermosetting epoxy resin. Fix the copper foil on the back side.
【0046】その後、複数のスルーホール2を切削ドリ
ルなどの穴あけ手段により設ける。さらにスルーホール
2の壁面を含む樹脂基板1表面を洗浄し、樹脂基板1の
全面に無電界メッキ処理および電解メッキ処理により銅
メッキ層を設ける。このメッキ層はスルーホール2内面
まで施す。Thereafter, a plurality of through holes 2 are provided by a drilling means such as a cutting drill. Further, the surface of the resin substrate 1 including the wall surfaces of the through holes 2 is cleaned, and a copper plating layer is provided on the entire surface of the resin substrate 1 by electroless plating and electrolytic plating. This plating layer is applied up to the inner surface of the through hole 2.
【0047】前述のように、おもて面とうら面に銅のう
す膜層を設けた樹脂基板1にエッチングマスクとエッチ
ング液を用いてエッチング処理を行う。このエッチング
処理により、図2に示すように樹脂基板1のおもて面に
半導体集積回路チップ7の各電極と電気的に接続するた
めの基板電極3と電気的経路を銅パターンとして設け
る。As described above, the resin substrate 1 provided with the copper thin film layer on the front and back surfaces is subjected to the etching process using the etching mask and the etching solution. By this etching process, as shown in FIG. 2, a substrate electrode 3 for electrically connecting to each electrode of the semiconductor integrated circuit chip 7 and an electric path are provided as a copper pattern on the front surface of the resin substrate 1.
【0048】図2に示すように、基板電極3は、後の行
程で固着する半導体集積回路チップ7の外周を取り囲む
ようにして設ける。As shown in FIG. 2, the substrate electrode 3 is provided so as to surround the outer periphery of the semiconductor integrated circuit chip 7 to be fixed in a later step.
【0049】さらに、このエッチング処理により、樹脂
基板1のおもて面に基板電極3とスルーホール2を電気
的に接続するための電気的経路を銅パターンとして設け
る。さらに、このエッチング処理により、樹脂基板1の
うら面にハンダボール端子11をハンダ付けするための
パッド電極4を銅パターンとして設ける。そのうえ樹脂
基板1のうら面にパッド電極4とスルーホール2を電気
的に接続するための図示しない電気的経路を銅パターン
として設ける。Further, by this etching process, an electric path for electrically connecting the substrate electrode 3 and the through hole 2 is provided on the front surface of the resin substrate 1 as a copper pattern. Further, by this etching process, pad electrodes 4 for soldering the solder ball terminals 11 are provided as copper patterns on the back surface of the resin substrate 1. In addition, an electrical path (not shown) for electrically connecting the pad electrode 4 and the through hole 2 is provided on the back surface of the resin substrate 1 as a copper pattern.
【0050】つぎに、前述のようにエッチング処理して
銅パターンを設けた樹脂基板1のおもて面とうら面に、
電気的経路を保護するための樹脂絶縁膜5を設ける。樹
脂絶縁膜5の材料としてはアクリル変成エポキシなどの
感光性樹脂組成物があげられる。Next, on the front and back surfaces of the resin substrate 1 provided with the copper pattern by etching as described above,
A resin insulating film 5 for protecting an electric path is provided. Examples of the material of the resin insulating film 5 include a photosensitive resin composition such as an acrylic modified epoxy.
【0051】樹脂絶縁膜5の材料として感光性樹脂組成
物を用いた場合は、露光現像処理を行うことで、樹脂基
板1のおもて面の基板電極3の部分は露出し、その他の
銅パターンは被服するように樹脂絶縁膜5を設ける。ま
た、樹脂基板1のうら面も露光現像処理を行うことで、
パッド電極4の部分は露出し、その他の銅パターンは被
服するように樹脂絶縁膜5を設ける。When a photosensitive resin composition is used as the material of the resin insulating film 5, the substrate electrode 3 on the front surface of the resin substrate 1 is exposed by performing exposure and development processing, and other copper The resin insulating film 5 is provided so as to cover the pattern. In addition, the back surface of the resin substrate 1 is also subjected to exposure and development processing,
A resin insulating film 5 is provided so as to expose the pad electrode 4 and cover other copper patterns.
【0052】以上説明したように、図1に示す配線基板
6はおもて面に基板電極3と樹脂絶縁膜5を有してい
る。さらに配線基板6はうら面にパッド電極4と樹脂絶
縁膜5を有している。また配線基板6はおもて面の基板
電極3とうら面のパッド電極4とをスルーホール2と銅
パターンからなる電気的経路とを介して電気的に接続し
ている。As described above, the wiring substrate 6 shown in FIG. 1 has the substrate electrode 3 and the resin insulating film 5 on the front surface. Further, the wiring board 6 has the pad electrode 4 and the resin insulating film 5 on the back surface. Further, the wiring board 6 electrically connects the substrate electrode 3 on the front surface and the pad electrode 4 on the back surface via the through hole 2 and an electric path formed of a copper pattern.
【0053】つぎに、配線基板6のおもて面とうら面の
樹脂絶縁膜5から露出している銅パターンの表面に、2
μmから5μm程度のニッケル(Ni)メッキ層を設
け、その上層に0.5μm程度の導通性の優れる金(A
u)メッキ層を設ける。Next, the surface of the copper pattern exposed from the resin insulating film 5 on the front and back surfaces of the wiring board 6
A nickel (Ni) plating layer of about 5 μm to 5 μm is provided, and a gold (A)
u) providing a plating layer;
【0054】つぎに、配線基板6を150℃で15分か
ら30分加熱することで、表面に付着している水分を除
去する。加熱には熱風オーブンや赤外線ヒーターのベル
ト炉などを用いる。Next, the wiring board 6 is heated at 150 ° C. for 15 to 30 minutes to remove moisture adhering to the surface. A hot air oven or a belt furnace of an infrared heater is used for heating.
【0055】配線基板6の表面に付着している水分を加
熱除去する場合、加熱温度は水分が気化する100℃以
上が望ましい。また200℃以上に長時間加熱すると配
線基板6が劣化する。したがって望ましい加熱温度は1
50℃程度である。When the moisture adhering to the surface of the wiring board 6 is removed by heating, the heating temperature is desirably 100 ° C. or higher at which the moisture evaporates. Further, when the wiring board 6 is heated to 200 ° C. or more for a long time, the wiring board 6 deteriorates. Therefore, the desired heating temperature is 1
It is about 50 ° C.
【0056】その後、配線基板6に熱硬化性の接着剤8
を供給し、さらに半導体集積回路チップ7を配線基板6
の中央に位置合わせして、接着剤8の厚みが50μm程
度になるように押さえつける。Thereafter, the thermosetting adhesive 8 is applied to the wiring substrate 6.
And the semiconductor integrated circuit chip 7 is connected to the wiring board 6.
And press down so that the thickness of the adhesive 8 becomes about 50 μm.
【0057】つぎに、接着剤8を加熱することで硬化さ
せる。接着剤8の材料に熱硬化性のエポキシ樹脂組成物
を用いる場合は150℃で60分程度加熱硬化を行う。
また、配線基板6上に半導体集積回路チップ7を接着剤
8を用い、加熱硬化して固着する行程は、配線基板6表
面に付着した水分を加熱除去する行程の終了後60分以
内に完了する必要がある。Next, the adhesive 8 is cured by heating. When a thermosetting epoxy resin composition is used as the material of the adhesive 8, heat curing is performed at 150 ° C. for about 60 minutes.
Further, the step of heating and curing the semiconductor integrated circuit chip 7 on the wiring board 6 using the adhesive 8 and fixing the same is completed within 60 minutes after the completion of the step of heating and removing the moisture attached to the surface of the wiring board 6. There is a need.
【0058】接着剤8を加熱硬化して固着する行程を、
配線基板6表面に付着した水分を加熱除去する行程の終
了後60分以内に完了しない場合は、再び配線基板6に
水分が付着し、本発明の効果が得られない。The process of fixing the adhesive 8 by heating and curing is as follows.
If the process of heating and removing the moisture adhering to the surface of the wiring board 6 is not completed within 60 minutes after the completion of the process, the moisture adheres to the wiring board 6 again, and the effect of the present invention cannot be obtained.
【0059】図3に配線基板6の150℃乾燥中の重量
変化を示す。図3から明らかなように配線基板6は15
0℃投入後、表面に吸着している水分が脱離するため重
量が減少する。また、図4に配線基板6の150℃乾燥
終了後、半導体装置を組み立てるために雰囲気が管理さ
れたクリーンルーム(温度22から25℃,湿度30か
ら65%)に放置した場合の重量変化を示す。FIG. 3 shows a change in weight of the wiring board 6 during drying at 150 ° C. As is clear from FIG.
After charging at 0 ° C., the moisture adsorbed on the surface is desorbed, so that the weight decreases. FIG. 4 shows a change in weight when the wiring board 6 is dried in a clean room (temperature: 22 to 25 ° C., humidity: 30 to 65%) in which the atmosphere is controlled after the drying of the wiring board 6 at 150 ° C. is completed.
【0060】図4から配線基板6は乾燥後クリーンルー
ム内に放置すると、再び表面に水分が付着するため重量
が時間とともに増加し、60分後にほとんど乾燥前の重
量にもっどっていることが解る。FIG. 4 shows that when the wiring substrate 6 is left in a clean room after being dried, the weight increases with time because moisture adheres to the surface again, and after 60 minutes, the weight has almost returned to the weight before drying.
【0061】図3と図4から配線基板6では乾燥工程の
実施前後の可逆的重量変化により、空気中の水分の付着
と脱離が、可逆的に起きていることが解る。したがっ
て、配線基板6上に半導体集積回路チップ7を接着剤8
を用い、加熱硬化して固着する行程は、配線基板6表面
に付着した水分を除去する行程の終了後60分以内に完
了する必要がある。FIGS. 3 and 4 show that in the wiring board 6, the adhesion and desorption of moisture in the air occur reversibly due to the reversible weight change before and after the drying step. Therefore, the semiconductor integrated circuit chip 7 is bonded on the wiring substrate 6 with the adhesive 8.
The step of fixing by heating and curing must be completed within 60 minutes after the end of the step of removing moisture adhering to the surface of the wiring board 6.
【0062】エポキシ等量が175のビスフェノールF
型エポキシ樹脂と2エチル4メチルイミダゾールとジシ
アンジアミドをそれぞれ90対5対5の重量比で混合し
て調整した熱硬化性の接着剤8を用いて、乾燥工程を行
わない配線基板6上に5mm角の半導体集積回路チップ
7を150℃60分の加熱硬化により接着した場合のせ
ん断方向の接着力は5.8kgfであった。Bisphenol F having an epoxy equivalent of 175
Using a thermosetting adhesive 8 prepared by mixing a type epoxy resin, 2-ethyl 4-methylimidazole and dicyandiamide at a weight ratio of 90: 5: 5, a 5 mm square on a wiring board 6 not subjected to a drying step When the semiconductor integrated circuit chip 7 was bonded by heat curing at 150 ° C. for 60 minutes, the adhesive force in the shear direction was 5.8 kgf.
【0063】また、上記の接着剤8を用いて、150℃
30分の表面乾燥工程を行なった直後の配線基板6上に
5mm角の半導体集積回路チップ7を150℃60分の
加熱硬化により接着した場合のせん断方向の接着力は
9.8kgfであった。Further, using the above-mentioned adhesive 8 at 150 ° C.
When a 5 mm square semiconductor integrated circuit chip 7 was bonded to the wiring board 6 immediately after the 30-minute surface drying step by heating and curing at 150 ° C. for 60 minutes, the adhesive force in the shear direction was 9.8 kgf.
【0064】また、上記の接着剤8を用いて、150℃
30分の表面乾燥工程を行なった後クリーンルーム内に
60分放置した配線基板6上に5mm角の半導体集積回
路チップ7を150℃60分の加熱硬化により接着した
場合のせん断方向の接着力は5.9kgfであった。Further, using the above-mentioned adhesive 8 at 150 ° C.
When a 5 mm square semiconductor integrated circuit chip 7 is bonded by heating and curing at 150 ° C. for 60 minutes on the wiring substrate 6 left in a clean room for 60 minutes after performing the surface drying step for 30 minutes, the adhesive force in the shear direction is 5 It was 0.9 kgf.
【0065】このように、接着剤8を加熱硬化して接着
する行程を、配線基板6表面に付着した水分を加熱除去
する行程の終了後60分以内に完了しない場合は、再び
配線基板6に水分が付着し、配線基板6と半導体集積回
路チップ7との良好な接着が得られない。As described above, if the step of heating and curing the adhesive 8 and bonding is not completed within 60 minutes after the end of the step of heating and removing the moisture adhering to the surface of the wiring board 6, Moisture adheres, and good adhesion between the wiring substrate 6 and the semiconductor integrated circuit chip 7 cannot be obtained.
【0066】また、配線基板6と半導体集積回路チップ
7との良好な接着を得るためには、接着剤8を加熱硬化
して固着する行程を、配線基板6表面に付着した水分を
加熱除去する行程の終了直後に完了することが望まし
い。In order to obtain good adhesion between the wiring board 6 and the semiconductor integrated circuit chip 7, the step of fixing the adhesive 8 by heating and curing is performed by removing moisture adhering to the surface of the wiring board 6 by heating. It is desirable to complete immediately after the end of the journey.
【0067】また、配線基板6表面に付着した水分を除
去する方法としては前述の基板加熱の他に、配線基板6
を減圧雰囲気に放置して除去する方法があげられる。こ
の方法でも、接着剤8を加熱硬化して接着する行程を、
配線基板6表面に付着した水分を減圧除去する行程の終
了後60分以内に完了しない場合は、再び配線基板6に
水分が付着し、配線基板6と半導体集積回路チップ7と
の良好な接着が得られない。As a method for removing moisture adhering to the surface of the wiring board 6, besides the above-described substrate heating, the wiring board 6 is removed.
Is left in a reduced-pressure atmosphere to remove. Also in this method, the process of heating and curing the adhesive 8 and bonding is performed.
If the process of removing the water adhering to the surface of the wiring substrate 6 under reduced pressure is not completed within 60 minutes after the end of the process, the water adheres to the wiring substrate 6 again, and good adhesion between the wiring substrate 6 and the semiconductor integrated circuit chip 7 is ensured. I can't get it.
【0068】さらに配線基板6と半導体集積回路チップ
7との良好な接着を得るためには、接着剤8を加熱硬化
して固着する行程を、配線基板6表面に付着した水分を
減圧除去する行程の終了直後に完了することが望まし
い。Further, in order to obtain good adhesion between the wiring board 6 and the semiconductor integrated circuit chip 7, the step of heating and curing the adhesive 8 and fixing the adhesive is performed in the step of removing water adhering to the surface of the wiring board 6 under reduced pressure. It is desirable to complete immediately after the end of.
【0069】上記のように本発明の半導体装置の製造方
法は、配線基板6上に半導体集積回路チップ7を接着剤
8を用いて固着する行程の直前に、配線基板6表面に付
着した水分を除去する行程を有している。As described above, in the method of manufacturing a semiconductor device according to the present invention, immediately before the step of fixing the semiconductor integrated circuit chip 7 on the wiring substrate 6 using the adhesive 8, the moisture adhering to the surface of the wiring substrate 6 is removed. It has a removal process.
【0070】したがって、接着剤8を用いて半導体集積
回路チップ7を配線基板6に固着する工程で、配線基板
6が接着剤8の硬化温度である150℃程度に加熱され
ても表面に吸着した水分が除去されているため、水分の
気化による気泡が配線基板6と接着剤8の界面に残らな
い。Therefore, in the step of fixing the semiconductor integrated circuit chip 7 to the wiring board 6 using the adhesive 8, even if the wiring board 6 is heated to about 150 ° C., which is the curing temperature of the adhesive 8, it is adsorbed on the surface. Since moisture has been removed, no air bubbles due to evaporation of moisture remain at the interface between the wiring board 6 and the adhesive 8.
【0071】したがって、PBGA12をマザーボード
に実装するリフローハンダ付け行程で、前述の界面の気
泡にPBGA12内の水分が気化膨張して吹き出すこと
がなく、配線基板6と接着剤8の界面に剥離が発生しな
い。Therefore, in the reflow soldering process of mounting the PBGA 12 on the motherboard, the moisture in the PBGA 12 does not evaporate and expand to the bubbles at the interface, and the interface between the wiring board 6 and the adhesive 8 is separated. do not do.
【0072】また、配線基板6と接着剤8の界面に気泡
が残留していないため、接着剤8の有効接着面積を多く
確保でき、結果として界面の良好な密着力が得られる。
このため、リフローハンダ付けの行程でPBGA12を
全体加熱しても、配線基板6と接着剤8の界面でせん断
力による剥離が発生しない。Further, since no air bubbles remain at the interface between the wiring substrate 6 and the adhesive 8, a large effective bonding area of the adhesive 8 can be secured, and as a result, a good adhesion at the interface can be obtained.
For this reason, even if the PBGA 12 is entirely heated in the reflow soldering process, the separation between the wiring substrate 6 and the adhesive 8 due to the shearing force does not occur.
【0073】また、配線基板6と接着剤8の間に吸着水
分の層が介在しない密着の良好な接着が可能になる。こ
のため、リフローハンダ付けの行程でPBGA12を全
体加熱しても、配線基板と接着剤の界面でせん断力によ
る剥離が発生しない。Further, good adhesion can be achieved without a layer of adsorbed moisture between the wiring board 6 and the adhesive 8. For this reason, even if the PBGA 12 is entirely heated in the reflow soldering process, peeling due to shearing force does not occur at the interface between the wiring board and the adhesive.
【0074】つぎに、半導体集積回路チップ7の各電極
と基板電極3を接続ワイヤー9を用いて電気的に接続す
る。接続ワイヤー9の材料として望ましいのは導通性の
優れる金(Au)ワイヤーである。Next, each electrode of the semiconductor integrated circuit chip 7 and the substrate electrode 3 are electrically connected by using the connection wire 9. Desirable as a material of the connection wire 9 is a gold (Au) wire having excellent conductivity.
【0075】その後、半導体集積回路チップ7の遮光と
保護を行うために、半導体集積回路チップ7と接続ワイ
ヤー9を熱硬化性の封止樹脂10を用いたトランスファ
ー・モールド成型方法により樹脂封止する。Thereafter, in order to shield and protect the semiconductor integrated circuit chip 7, the semiconductor integrated circuit chip 7 and the connection wires 9 are resin-sealed by a transfer molding method using a thermosetting sealing resin 10. .
【0076】つぎに、配線基板6うら面のパッド電極4
にハンダボールを供給し、加熱炉で加熱することによっ
て、ハンダボール端子11を設ける。このハンダボール
端子11は図示しないマザーボードの電極と電気的に接
続するために用いる。なお、PBGA12は、半導体集
積回路チップ7の各電極とハンダボール端子11とを、
接続ワイヤー9と配線基板6を介して電気的に接続して
いる。Next, the pad electrode 4 on the back surface of the wiring board 6
The solder ball terminal 11 is provided by supplying a solder ball to the solder ball and heating it in a heating furnace. The solder ball terminals 11 are used to electrically connect to electrodes of a motherboard (not shown). The PBGA 12 connects each electrode of the semiconductor integrated circuit chip 7 and the solder ball terminal 11 with each other.
It is electrically connected to the connection wire 9 via the wiring board 6.
【0077】以上説明したように、本発明の製造方法
は、配線基板6上に半導体集積回路チップ7を接着剤8
を用いて固着する行程の直前に、配線基板6表面に付着
した水分を除去する行程を有している。As described above, according to the manufacturing method of the present invention, the semiconductor integrated circuit chip 7 is
Immediately before the step of fixing by using the method, there is a step of removing moisture attached to the surface of the wiring board 6.
【0078】したがって、接着剤8を用いて半導体集積
回路チップ7を配線基板6に固着する行程で、配線基板
6の表面に吸着した水分が接着剤8の硬化温度の150
℃程度に加熱されることで気化し、配線基板6と接着剤
8の界面に気泡が残ることがない。したがって、接着剤
8の加熱硬化の行程で接着剤8と配線基板6の界面に気
泡が残留することがない。したがって、PBGA12を
マザーボードに実装するリフローハンダ付け行程で、前
述の界面の気泡にPBGA12内の水分が気化膨張して
吹き出すことがなく、配線基板6と接着剤8の界面に剥
離が発生しない。Therefore, in the process of fixing the semiconductor integrated circuit chip 7 to the wiring board 6 by using the adhesive 8, the moisture adsorbed on the surface of the wiring board 6 reduces the curing temperature of the adhesive 8 to 150 ° C.
When heated to about ° C., there is no gasification and no air bubbles remain at the interface between the wiring board 6 and the adhesive 8. Therefore, no bubbles remain at the interface between the adhesive 8 and the wiring board 6 during the heating and curing process of the adhesive 8. Therefore, in the reflow soldering process of mounting the PBGA 12 on the motherboard, the moisture in the PBGA 12 does not evaporate and expand to the bubbles at the interface, and the interface does not peel off at the interface between the wiring board 6 and the adhesive 8.
【0079】さらに本発明の半導体装置の製造行程は、
配線基板6表面に付着した水分を除去する行程の終了後
60分以内に、配線基板6上に半導体集積回路チップ7
を接着剤8を用いて固着する。Further, the manufacturing process of the semiconductor device of the present invention is as follows.
The semiconductor integrated circuit chip 7 is placed on the wiring board 6 within 60 minutes after the completion of the process of removing the moisture attached to the surface of the wiring board 6.
Is fixed using an adhesive 8.
【0080】したがって、水分を除去した配線基板6表
面に再び水分が付着する前に、半導体集積回路チップ7
の固着を完了する。このため接着剤8の加熱硬化の行程
で接着剤8と配線基板6の界面に気泡が残留することが
ない。したがって、PBGA12をマザーボードに実装
するリフローハンダ付け行程で、前述の界面の気泡にP
BGA12内の水分が気化膨張して吹き出すことがな
く、配線基板6と接着剤8の界面に剥離が発生しない。Therefore, before the moisture adheres again to the surface of the wiring substrate 6 from which the moisture has been removed, the semiconductor integrated circuit chip 7
Complete the fixation. Therefore, no bubbles remain at the interface between the adhesive 8 and the wiring board 6 during the heating and curing process of the adhesive 8. Therefore, during the reflow soldering process of mounting the PBGA 12 on the motherboard, the air bubbles at the interface are reduced by P.
The water in the BGA 12 is not vaporized and expanded and blows out, and no separation occurs at the interface between the wiring board 6 and the adhesive 8.
【0081】また、配線基板6と接着剤8の界面に気泡
が残留していないため、接着剤8の有効接着面積を多く
確保でき、結果として界面の良好な密着力が得られる。
このため、リフローハンダ付けの行程でPBGA12を
全体加熱しても、配線基板6と接着剤8の界面でせん断
力による剥離が発生しない。Further, since no air bubbles remain at the interface between the wiring board 6 and the adhesive 8, a large effective adhesive area of the adhesive 8 can be secured, and as a result, a good adhesion at the interface can be obtained.
For this reason, even if the PBGA 12 is entirely heated in the reflow soldering process, the separation between the wiring substrate 6 and the adhesive 8 due to the shearing force does not occur.
【0082】また、配線基板6と接着剤8の間に吸着水
分の層が介在しない密着の良好な接着が可能になる。こ
のため、リフローハンダ付けの行程でPBGA12を全
体加熱しても、配線基板6と接着剤8の界面でせん断力
による剥離が発生しない。Further, good adhesion can be achieved without a layer of adsorbed moisture between the wiring board 6 and the adhesive 8. For this reason, even if the PBGA 12 is entirely heated in the reflow soldering process, the separation between the wiring substrate 6 and the adhesive 8 due to the shearing force does not occur.
【0083】したがって、半導体集積回路チップ7下部
の剥離により、配線基板6がマザーボード側に膨れ実装
が不可能になったり、PBGA12内部の電気的経路が
断線するなどの故障を生じない。したがって半導体集積
回路チップ下部の剥離により、配線基板がマザーボード
側に膨れ実装が不可能になったり、PBGA内部の電気
的経路が断線するなどの故障を発生することがなく、耐
湿性に優れた半導体装置が得られる。Accordingly, the peeling of the lower portion of the semiconductor integrated circuit chip 7 does not cause a failure such as the wiring board 6 swelling toward the motherboard and cannot be mounted, or the electric path inside the PBGA 12 is disconnected. Therefore, the semiconductor substrate having excellent moisture resistance does not cause a failure such as a wiring board swelling to the motherboard side due to peeling of the lower portion of the semiconductor integrated circuit chip, making mounting impossible, and an electric path in the PBGA being disconnected. A device is obtained.
【0084】[0084]
【発明の効果】以上の説明から明らかなように、本発明
の半導体装置の製造方法においては、PBGAの完成
後、マザーボードに実装するリフローハンダ付け行程
で、配線基板と接着剤の界面の気泡にPBGA内部の水
分が気化膨張して吹き出すことで配線基板と接着剤の界
面に剥離が発生することはない。As is apparent from the above description, in the method of manufacturing a semiconductor device according to the present invention, after the completion of the PBGA, the air bubbles at the interface between the wiring board and the adhesive are removed in the reflow soldering process of mounting on the motherboard. Since the water inside the PBGA evaporates and expands and blows out, no separation occurs at the interface between the wiring board and the adhesive.
【図1】本発明の実施形態における半導体装置の製造方
法のPBGAの構造を示す断面図である。FIG. 1 is a cross-sectional view showing a PBGA structure in a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図2】本発明の実施形態における半導体装置の製造方
法のPBGAにおける樹脂基板おもて面の銅パターンを
示す平面図である。FIG. 2 is a plan view showing a copper pattern on a front surface of a resin substrate in a PBGA in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
【図3】本発明の実施形態における半導体装置の製造方
法の配線基板の乾燥中の重量変化を示すグラフである。FIG. 3 is a graph showing a change in weight during drying of a wiring board in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
【図4】本発明の実施形態における半導体装置の製造方
法の乾燥終了後の配線基板の重量変化を示すグラフであ
る。FIG. 4 is a graph showing a change in weight of a wiring board after drying of the method of manufacturing a semiconductor device according to the embodiment of the present invention.
1 樹脂基板 2 スルーホール 3 基板電極 4 パッド電極 5 樹脂絶縁膜 6 配線基板 7 半導体集積回路チップ 8 接着剤 9 接続ワイヤー 10 封止樹脂 11 ハンダボール 12 PBGA REFERENCE SIGNS LIST 1 resin substrate 2 through hole 3 substrate electrode 4 pad electrode 5 resin insulating film 6 wiring substrate 7 semiconductor integrated circuit chip 8 adhesive 9 connection wire 10 sealing resin 11 solder ball 12 PBGA
Claims (4)
板の表面に付着した水分を除去する行程と、 この配線基板に半導体集積回路チップを接着剤を用いて
固着する行程と、 半導体集積回路チップの各電極と配線基板に設ける基板
電極とを導電性のワイヤーで接続する行程と、 半導体集積回路チップと接続ワイヤーと基板電極を樹脂
封止する行程と、 配線基板のうら面にマザーボードと接続するためのハン
ダボールを設ける行程とを有することを特徴とするプラ
スチック・ボール・グリッド・アレイの半導体装置の製
造方法。1. A step of removing moisture adhering to the surface of a wiring board mainly composed of a resin component, a step of fixing a semiconductor integrated circuit chip to the wiring board by using an adhesive, and a step of fixing the semiconductor integrated circuit chip. Connecting each of the electrodes to the substrate electrode provided on the wiring board with a conductive wire, sealing the semiconductor integrated circuit chip, the connection wire and the substrate electrode with a resin, and connecting the mother board to the back surface of the wiring board. Providing a solder ball for use in the method of manufacturing a semiconductor device of a plastic ball grid array.
板の表面に付着した水分を加熱除去する行程と、 この配線基板に半導体集積回路チップを接着剤を用いて
固着する行程と、 半導体集積回路チップの各電極と配線基板に設ける基板
電極とを導電性のワイヤーで接続する行程と、 半導体集積回路チップと接続ワイヤーと基板電極を樹脂
封止する行程と、 配線基板のうら面にマザーボードと接続するためのハン
ダボールを設ける行程とを有することを特徴とするプラ
スチック・ボール・グリッド・アレイの半導体装置の製
造方法。2. A step of heating and removing moisture adhering to the surface of a wiring board containing a resin component as a main constituent material, a step of fixing a semiconductor integrated circuit chip to the wiring board by using an adhesive, and Connecting each electrode of the chip to the substrate electrode provided on the wiring board with a conductive wire; connecting the semiconductor integrated circuit chip, the connection wire and the substrate electrode with resin; connecting the mother board to the back surface of the wiring board Providing a solder ball for performing the method of manufacturing the semiconductor device of the plastic ball grid array.
板の表面に付着した水分を除去する行程と、 この行程の終了後60分以内に前記配線基板に半導体集
積回路チップを接着剤を用いて固着する行程と、 半導体集積回路チップの各電極と配線基板に設ける基板
電極とを導電性のワイヤーで接続する行程と、 半導体集積回路チップと接続ワイヤーと基板電極を樹脂
封止する行程と、 配線基板のうら面にマザーボードと接続するためのハン
ダボールを設ける行程とを有することを特徴とするプラ
スチック・ボール・グリッド・アレイの半導体装置の製
造方法。3. A step of removing moisture adhering to the surface of the wiring board mainly composed of a resin component, and applying a semiconductor integrated circuit chip to the wiring board using an adhesive within 60 minutes after the completion of this step. A step of connecting each electrode of the semiconductor integrated circuit chip to a substrate electrode provided on the wiring board with a conductive wire; a step of resin-sealing the semiconductor integrated circuit chip, the connection wire, and the substrate electrode; Providing a solder ball for connecting to a motherboard on the back surface of the substrate.
板の表面に付着した水分を加熱除去する行程と、 この行程の終了後60分以内に前記配線基板に半導体集
積回路チップを接着剤を用いて固着する行程と、 半導体集積回路チップの各電極と配線基板に設ける基板
電極とを導電性のワイヤーで接続する行程と、 半導体集積回路チップと接続ワイヤーと基板電極を樹脂
封止する行程と、 配線基板のうら面にマザーボードと接続するためのハン
ダボールを設ける行程とを有することを特徴とするプラ
スチック・ボール・グリッド・アレイの半導体装置の製
造方法。4. A step of heating and removing moisture adhering to the surface of the wiring board mainly composed of a resin component, and using a bonding agent to attach the semiconductor integrated circuit chip to the wiring board within 60 minutes after the completion of this step. A step of connecting each electrode of the semiconductor integrated circuit chip and a substrate electrode provided on the wiring board with a conductive wire, a step of resin-sealing the semiconductor integrated circuit chip, the connection wire, and the substrate electrode, Providing a solder ball for connecting to a motherboard on the back surface of the wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10004697A JPH11204549A (en) | 1998-01-13 | 1998-01-13 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10004697A JPH11204549A (en) | 1998-01-13 | 1998-01-13 | Method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11204549A true JPH11204549A (en) | 1999-07-30 |
Family
ID=11591093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10004697A Pending JPH11204549A (en) | 1998-01-13 | 1998-01-13 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11204549A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010051976A (en) * | 1999-11-30 | 2001-06-25 | 가네꼬 히사시 | Semiconductor device manufactured by package group molding and dicing method |
| US6472749B1 (en) * | 1999-02-15 | 2002-10-29 | Hitachi, Ltd. | Semiconductor device having a shortened wiring length to reduce the size of a chip |
| JP2002324814A (en) * | 2001-04-25 | 2002-11-08 | Nec Corp | Method and apparatus for resin sealing of COF semiconductor package |
-
1998
- 1998-01-13 JP JP10004697A patent/JPH11204549A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6472749B1 (en) * | 1999-02-15 | 2002-10-29 | Hitachi, Ltd. | Semiconductor device having a shortened wiring length to reduce the size of a chip |
| US6838767B2 (en) | 1999-02-15 | 2005-01-04 | Hitachi, Ltd. | Semiconductor device |
| KR20010051976A (en) * | 1999-11-30 | 2001-06-25 | 가네꼬 히사시 | Semiconductor device manufactured by package group molding and dicing method |
| JP2002324814A (en) * | 2001-04-25 | 2002-11-08 | Nec Corp | Method and apparatus for resin sealing of COF semiconductor package |
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