JPH11205101A - Phase tracking device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve phase followup ability while reducing the error of phase difference between clock signals by detecting the phase difference between a reference clock signal and a most delayed clock signal and applying a delay control signal to a phase different clock signal generating block based on this phase difference. SOLUTION: When a phase comparator 34 detects the case of the phase of a clock signal B < the phase of the reference clock signal, the phases of clock signals A and B are advanced from the clock signal, and the phase difference between the clock signals generated by the phase difference generating block does not satisfy the first setting value, a count control signal for increasing the count value of a delay counter 35 is applied from the phase comparator 34 to the delay counter 35. The count value is increased and the correspondent delay control signal is applied to a variable delay circuit 31. Then, a delay element is selected so as to be increased corresponding to the delay control signal by the selector circuit of the variable delay circuit 31, and the phase difference between clock signals generated from the phase difference generating block is made closer to the first setting value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a phase tracking apparatus for optimally controlling a phase difference between a plurality of clock signals each having a phase difference.

[0002]

2. Description of the Related Art For example, in serial communication using a universal serial bus used in communication of a personal computer or the like, correct communication data is identified and extracted from communication signals containing jitter received serially. Therefore, it is necessary to generate an identification signal synchronized with the communication signal. As this identification signal, it is desirable to use a clock signal sufficiently faster than the communication speed in order to accurately determine the communication data. However, at the present time when the communication speed is remarkably increased, it is becoming extremely difficult to generate a clock signal identification signal sufficiently faster than the communication speed.

As a solution to this problem, there is a method of generating an identification signal using a DPL (Digital Phase Lock) circuit with a clock signal having the same speed as the communication speed. In this method, since it is necessary to lock the identification signal with a very limited synchronization pattern, for example, a DPL circuit as shown in FIG. 8 has been used.

In FIG. 8, a DPL circuit generates a plurality of clock signals (CLK1 to CLK5) each having a predetermined phase difference from a reference clock signal (CLK0) by a plurality of phase difference generating circuits 101 connected in cascade. A clock signal selection circuit 102 selects and generates a following clock signal serving as an identification signal from the generated clock signals based on a communication signal (serial data). By adopting such a configuration, synchronization can be achieved by one phase adjustment.

However, it is difficult for the phase difference generating circuit 101 in the DPL circuit to generate a plurality of clock signals having a desired phase difference due to use conditions and potentially existing errors, and performs a reliable phase tracking. It was difficult. For this reason, an accurate identification signal cannot be generated, and data may not be correctly extracted from a high-speed communication signal.

[0006]

As described above,
In a conventional phase tracking device that generates an identification signal for identifying correct data from communication signals in a short time in accordance with the frequency of the communication signal, the identification signal is determined by an error inherent in the circuit and use conditions. It has been difficult to set the phase difference between a plurality of clock signals to be generated to a predetermined value with high accuracy. For this reason, there has been a problem in that data cannot be accurately identified and extracted from communication signals by performing phase tracking reliably.

Accordingly, the present invention has been made in view of the above, and it is an object of the present invention to provide a phase tracking device in which an error in a phase difference between clock signals is reduced to improve phase tracking. Is to do.

[0008]

According to one aspect of the present invention, there is provided a reference clock signal generating device for generating a reference clock signal, and a reference clock signal generated by the reference clock signal generating circuit. A phase difference clock signal generation block that receives a signal and generates a plurality of clock signals having a predetermined phase difference between the clock signals based on the delay control signal; and a plurality of clocks generated by the phase difference clock signal generation block. A selection circuit that selects a tracking clock signal to follow the communication signal based on the communication signal from among the signals, and a delay circuit that is the most delayed with respect to the reference clock signal among a plurality of clock signals generated by the phase difference clock signal generation block. Receiving the most delayed clock signal of the phase and the reference clock signal generated by the reference clock signal generation circuit, A phase difference detection block for detecting a phase difference between the lock signal and the most delayed clock signal, and providing a delay control signal to the phase difference clock signal generation block based on the detection result, and detecting a phase difference error between the clock signals. It is characterized in that it can be suppressed to a minimum, and good phase tracking is achieved.

According to a second aspect of the present invention, in the phase follower according to the first aspect, the phase difference clock signal generation block delays an input clock signal by a predetermined fixed delay amount. Receiving the clock signal delayed by the fixed delay circuit and the delay control signal output from the phase difference detection block, and selecting a clock signal provided by selecting a plurality of delay elements based on the delay control signal. A variable delay circuit that variably delays the phase difference to control the phase difference, thereby minimizing the phase difference error between the clock signals, and achieving good phase tracking. .

According to a third aspect of the present invention, in the phase tracking apparatus according to the first or second aspect, the phase difference detection block receives a most delayed clock signal and a delay control signal and receives a plurality of delay control signals based on the delay control signal. A variable delay circuit for variably delaying the most-delayed clock signal by selecting a delay element; and receiving the clock signal delayed by the variable delay circuit, delaying the clock signal by a preset fixed delay amount. A fixed delay circuit for generating a comparison signal, a comparator for receiving a reference clock signal and a comparison signal, comparing the two, and outputting a count control signal for increasing or decreasing a counter based on the comparison result; and a count control for the comparator. And a counter for increasing or decreasing the count value based on the signal and outputting a delay control signal corresponding to the counter value. It is possible to suppress the difference to a minimum, characterized in that to achieve a good phase tracking ability.

According to a fourth aspect of the present invention, in the phase tracking apparatus according to the third aspect, the phase difference detection block compares a plurality of leading phases and lag phases having different phase differences with respect to the output of the variable delay circuit. A signal is generated, and an error in a phase difference between clock signals can be suppressed to a minimum.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a phase tracking apparatus according to an embodiment of the present invention.

In FIG. 1, the phase follower has a phase difference of, for example, π / 3 from the reference clock signal.
A reference clock signal generator 1 that generates two clock signals and performs phase tracking on a serial communication signal, and generates a reference clock signal (CLK0).
And a clock signal (CLK1) having a phase difference of π / 3 with respect to the reference clock signal based on the delay control signal in response to the reference clock signal of the reference clock signal generator 1.
Receiving the clock signal output from the phase difference generating block 2-1 and generating a π / 3 based on the delay control signal.
Phase difference generating block 2-2 for generating a clock signal (CLK2) having a phase difference of
A phase difference generating block 2-3 for receiving a clock signal output from the phase control signal 2 and generating a clock signal (CLK3) having a phase difference of π / 3 with respect to the clock signal based on the delay control signal; Phase difference generating block 2 receiving a clock signal output from generating block 2-3 and generating a clock signal (CLK4) having a phase difference of π / 3 with respect to this clock signal based on a delay control signal.
Receiving the clock signal output from the phase difference generation block 2-4 and generating a clock signal (CLK5) having a phase difference of π / 3 with respect to this clock signal based on the delay control signal. A phase difference generating block 2-5;
Reference clock signal and fifth-stage phase difference generating block 2-5
, The phase difference between the reference clock signal and the clock signal (CLK5) is detected, and based on the detection result, each of the phase difference generation blocks 2-1 to 2-1 is detected.
2-5, a phase difference detecting block 3 for providing a delay control signal for controlling the signal delay to each of the phase difference generating blocks 2-1 to 2-5, and each of the phase difference generating blocks 2-1 to 2-1.
The clock signal selection circuit 4 receives the clock signal generated in 2-5 and the serial data serving as a communication signal, selects a clock signal serving as a serial data identification signal based on the communication signal, and outputs the selected clock signal as a following clock signal. It is configured with. Note that the number of clock signals to be phase-followed and the phase difference between the respective clock signals are not limited to the above values, but can be set arbitrarily.

FIG. 2 is a diagram showing the configuration of the phase difference generating blocks 2-1 to 2-5 shown in FIG. 1 in the phase tracking apparatus according to one embodiment of the present invention.

In FIG. 2, a phase difference generating block 2-1 is shown.
2-5, a fixed delay circuit 21 receiving the clock signal of the preceding stage and delaying the clock signal of the preceding stage so as to have a predetermined phase difference slightly smaller than π / 3, and a fixed delay circuit 2
1 and a delay control signal, the selection circuit 23 selects a plurality of delay elements 22 having a delay amount ΔX based on the delay control signal, thereby variably delaying the output of the fixed delay circuit 21. 24. With such a configuration, the phase difference generating blocks 2-1 to 2-5
When n delay elements 22 are selected by the delay control signal in the variable delay circuit 24, the input clock signal is (delay amount of the fixed delay circuit 21) + (n × Δ
X) will output a clock signal delayed in phase. The unselected delay element 22 includes a selection circuit 23
, So that power is not consumed.
Here, as an initial value of the design, for example, the selection circuit 23 sets about half of all the delay elements 22 to the selected state, and the delay amount obtained by adding this delay amount and the delay amount of the fixed delay circuit 21 is π /
It is set to be about three.

FIG. 3 is a diagram showing the configuration of the phase difference detection block 3 shown in FIG. 1 in the phase tracking apparatus according to one embodiment of the present invention.

In FIG. 3, the phase difference detection block 3
The clock signal (C) of the fifth-stage phase difference generation block 2-5
LK5), a variable delay circuit 31 for variably delaying the clock signal by the same configuration as the variable delay circuit 24 shown in FIG. 2, and a clock signal delayed by the variable delay circuit 31 to receive the clock signal. 2 outputs a clock signal A having a delay amount of the fixed delay circuit 21 shown in FIG. 2 and a delay amount of −3ΔX, that is, the phase difference generation block 2-5 having a phase difference of 5π / 3 with respect to the reference clock signal. ｛(Π / 3) -3Δ with respect to clock signal (CLK5)
A fixed delay circuit 32 for outputting a clock signal A having a phase difference of (2π−3ΔX) having a phase difference of X｝, and receiving the clock signal A of the fixed delay circuit 32, the clock signal A is converted by a delay amount of 6ΔX. Upon receiving a delay element 33 that outputs a delayed clock signal B having a phase difference of (2π + 3ΔX), a reference clock signal, a clock signal A, and a clock signal B,
The phase comparator 34 compares the phase difference between the clock signal A and the clock signal B with respect to the reference clock signal and outputs a count control signal corresponding to the comparison result. It is provided with a delay counter 35 for increasing or decreasing the count value based on the signal and outputting a delay control signal for selectively controlling the delay elements 22 of the variable delay circuits 24 and 31.

In such a configuration, the phase comparison circuit 34 of the phase difference detection block 3 detects that the phase of the clock signal B <the phase of the reference clock signal, and as shown in FIG. The phase difference between the clock signals generated by the phase difference generating blocks 2-1 to 2-5 becomes the leading phase with respect to the clock signal.
Is less than the count value, the count control signal for increasing the count value of the delay counter 35 is provided from the phase comparator 34 to the delay counter 35, the count value of the delay counter 35 is increased, and the corresponding delay control signal is changed to the variable delay circuit. 2
4,31. Thereby, the variable delay circuit 2
The delay element 22 according to the delay control signal is further selected by the selection circuits 24 and 4 in the increasing direction, and the phase difference between the clock signals generated from the phase difference generation blocks 2-1 to 2-5 is And the phase difference is π / 3
It is adjusted in the direction approaching. In FIG. 4, the clock signal (CLK6) has an intermediate value between the clock signal A and the clock signal B, and the clock signal A and the clock signal B
Have the same phase difference with respect to the clock signal (CLK6).

As a result of such control, the phase comparator 34 of the phase difference detection block 3 detects that the phase of the clock signal A <the phase of the reference clock signal <the phase of the clock signal B, and FIG. As shown, when the clock signal A has a leading phase with respect to the reference clock signal and the clock signal B has a lagging phase with respect to the reference clock signal, the clock generated by the phase difference generation blocks 2-1 to 2-5. Assuming that the phase difference between the signals substantially satisfies the initially set π / 3, the count value of the delay counter 35 is kept unchanged and the delay control signal is not changed. As a result, the phase difference between the clock signals generated from the phase difference generating blocks 2-1 to 2-5 is substantially equal to π / 3.
It is adjusted to.

On the other hand, the phase comparison circuit 34 of the phase difference detection block 3 detects that the phase of the clock signal A> the phase of the reference clock signal, and as shown in FIG. 6, the clock signals A and B are different from the reference clock signal. If the phase difference between the clock signals generated by the phase difference generation blocks 2-1 to 2-5 exceeds the initially set π / 3,
A count control signal for decreasing the count value of the delay counter 35 is supplied from the phase comparator 34 to the delay counter 35, and the count value of the delay counter 35 is reduced and the corresponding delay control signal is supplied to the variable delay circuits 24 and 31. . Thereby, the selection circuit 2 of the variable delay circuits 24 and 31
4, the delay element 22 corresponding to the delay control signal is selected in a direction in which the delay element 22 in the selected state decreases more than before, and the delay element 22 between the clock signals generated from the phase difference generation blocks 2-1 to 2-5 is selected. The phase difference is reduced, the phase difference is adjusted in a direction approaching π / 3, and the phase difference is adjusted as shown in FIG.

By employing such a configuration, it is possible to minimize the error of the phase difference between the clock signals generated by the respective phase difference generating blocks 2-1 to 2-5 in a short time. Become. In addition, the phase difference generation block 2-
In 1 to 2-5 and the phase difference detection block 3,
Since the phase difference is generated by selecting the delay element 22, it is effective particularly in a method that can be dealt with by changing only the wiring such as the gate array, and can be suitably and easily implemented in the ASIC such as the gate array. .

FIG. 7 is a diagram showing a configuration of a phase difference detection block in a phase tracking apparatus according to an embodiment of the present invention.

In FIG. 7, the feature of this embodiment is that the fixed delay circuit 3 is different from the embodiment shown in FIG.
2 instead of the phase comparator 34, the fixed delay circuit 21 outputs a clock signal A having a delay amount of -9ΔX with respect to the clock signal delayed by the variable delay circuit 31. Delay circuit 36 and fixed delay circuit 3
The clock signal B (the phase of the clock signal A + 6ΔX) and the clock signal C (the phase of the clock signal B + 6ΔX) obtained by delaying the six clock signals A by the delay element 33 having a delay amount of 6ΔX cascaded in three stages. , The clock signal D (the phase of the clock signal C + 6ΔX) and the clock signal A are compared with the reference clock signal (CLK0) to determine in which range the phase of the reference clock signal is between the phases of the respective clock signals. A phase comparator 37 for detecting and outputting a count control signal according to the detection result to the delay counter 35 is provided. Range of phase leading from -9ΔX, range of -9ΔX to -3ΔX, -3ΔX to + 3Δ
X range, + 3ΔX to + 9ΔX range and + 9ΔX
That is, the range of the lag phase is set.

Thus, the error of the phase difference is, for example, (π /
3) From -15ΔX to (π / 3) -9ΔX, or (π /
3) In the above-described embodiment, when the phase difference is in the range of + 9ΔX to (π / 3) + 15ΔX, the optimal adjustment of the phase difference is performed twice before the optimal adjustment of the phase difference ends. In this embodiment, the optimal count control signal is output in one phase comparison, and the optimal phase difference adjustment can be performed. When the error of the phase difference is large, the short time is about half that of the above-described embodiment. Thus, the phase difference can be adjusted. In this embodiment, the number of clock signals to be compared with the reference clock signal is set to four, and the delay difference between the signals is set to 6ΔX. However, the present invention is not limited to this and can be set arbitrarily. It is.

[0026]

As described above, according to the present invention, the detection result of the phase difference between the clock signal having the most delayed phase and the reference clock signal with respect to the reference clock signal among the plurality of clock signals having different phase differences. Therefore, since the phase difference between the respective clock signals is controlled, the error of the phase difference between the clock signals can be suppressed to a minimum, and a good phase tracking property can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a phase tracking device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a phase difference generation block.

FIG. 3 is a diagram illustrating a configuration of a phase difference detection block.

FIG. 4 is a diagram showing one operation timing of the device shown in FIG. 1;

FIG. 5 is a diagram showing another operation timing of the device shown in FIG. 1;

FIG. 6 is a diagram showing another operation timing of the device shown in FIG. 1;

FIG. 7 is a diagram showing a configuration of a phase difference detection block according to an embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a conventional digital phase lock circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reference clock signal generation circuit 2 Phase difference generation block 3 Phase difference detection block 4 Clock signal selection circuit 21, 32, 36 Fixed delay circuit 22, 33 Delay element 23 Selection circuit 24, 31 Variable delay circuit 34, 37 Phase comparator 35 Delay counter

Claims (4)

[Claims] A reference clock signal generator for generating a reference clock signal; receiving a reference clock signal generated by the reference clock signal generation circuit, and generating a predetermined phase difference between the clock signals based on a delay control signal. A phase difference clock signal generating block for generating a plurality of clock signals, and a following clock signal to be made to follow the communication signal based on the communication signal from the plurality of clock signals generated by the phase difference clock signal generating block. A selection circuit; a plurality of clock signals generated by the phase difference clock signal generation block; a most delayed clock signal having the most delayed phase with respect to the reference clock signal; and a reference signal generated by the reference clock signal generation circuit. Upon receiving the clock signal, the phase difference between the reference clock signal and the delayed clock signal is detected, and based on the detection result, And a phase difference detection block for providing a delay control signal to the phase difference clock signal generation block. 2. The phase difference clock signal generation block, comprising: a fixed delay circuit for delaying an input clock signal by a predetermined fixed delay amount; a clock signal delayed by the fixed delay circuit; A variable delay circuit that receives a delay control signal output from the detection block, variably delays a given clock signal by selecting a plurality of delay elements based on the delay control signal, and controls a phase difference. The phase tracking device according to claim 1, wherein: 3. A variable delay for receiving the most delayed clock signal and the delay control signal and selecting a plurality of delay elements based on the delayed control signal to variably delay the most delayed clock signal. Receiving a clock signal delayed by the variable delay circuit,
A fixed delay circuit that generates a comparison signal by delaying this clock signal by a preset fixed delay amount, and a count that receives and compares the reference clock signal and the comparison signal, and increases or decreases the counter based on the comparison result. 3. A comparator that outputs a control signal, and a counter that increases or decreases the count value based on the count control signal of the comparator and outputs a delay control signal corresponding to the counter value.
A phase tracking device according to claim 1. 4. The phase tracking device according to claim 3, wherein the phase difference detection block generates a plurality of leading phase and lagging phase comparison signals having different phase differences with respect to the output of the variable delay circuit. apparatus.