JPH11205731A - Digital camera - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the cost of a synchronous DRAM(SDRAM) and to display pluralities of images on a monitor by reading data at a high speed. SOLUTION: An input buffer 22 converts a clock rate of image data from 12 MHz into 48 MHz and the image data with 48 MHz are written in an SDRAM 26 via a bus 24. The image data stored in the SDRAM 26 are read twice at a rate of 48 MHz. The one image data are written in an output buffer 30 via the bus 24 and the other image data are written in the output buffer 32. Character data are read from the SDRAM 26 at the same rate and written in the output buffer 34. Data are read from the output buffers 30-34 at a rate of 12 MHz and then a plurality of images and characters are displayed on an LCD 46.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital camera, and more particularly, to a digital camera that outputs, for example, image data through a memory.

[0002]

2. Description of the Related Art As a conventional digital camera of this type, there has been one using a dual port VRAM.
That is, for example, a captured moving image is
When outputting from a CD, image data output by a progressive scan from a CCD imager is written to a VRAM through an input port, the VRAM is interlaced and read, and the image data is output from an output port.

[0003]

However, in such a conventional technique, there is a problem that the cost is high because a VRAM having low versatility is used. Also, since there is only one output path for image data, only one type of image
D could not be displayed. SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a digital camera capable of suppressing costs and displaying a plurality of images.

[0004]

SUMMARY OF THE INVENTION The present invention is directed to a memory having a single port, a bus having a single data input path and a plurality of data output paths parallel to each other, and input from a single data input path. First writing means for writing input image data to the memory at a first speed higher than the reference speed;
And outputting the plurality of output image data to a second
First reading means for individually reading from the memory at a speed and outputting from each of the plurality of data output paths, wherein the first speed is correlated with a first occupation period in which the first writing means occupies the bus; Is a digital camera correlated with a second occupation period in which the first reading means occupies the bus.

[0005]

The clock rate of the input image data is converted from 12 MHz to 48 MHz by the input buffer. The 48 MHz image data output from the input buffer is written to a synchronous DRAM (SDRAM) via a data input path and a data input / output path formed on a bus. The image data written to the SDRAM is 4
It is read twice at a clock rate of 8 MHz. One image data is supplied to a first output buffer via a first data output path formed on a bus, and the other image data is supplied to a second output buffer via a second data output path. Given. Character data is also read from the SDRAM at a clock rate of 48 MHz and applied to a third output buffer via a third data output path. In each output buffer, the data clock rate is converted from 48 MHz to 12 MHz. Then, a part of each image data is given to the LCD, and a plurality of images are displayed on the LCD. Also, a predetermined character is displayed on the LCD based on the character data. Note that the image data written to the SDRAM and the two image data and character data displayed from the SDRAM pass through the bus at different times, and the data do not collide.

[0006]

According to the present invention, since a memory having a single port is used, the cost can be reduced. Also, a plurality of image data are read from the memory and output from different data output paths, so that a plurality of images can be simultaneously displayed on the monitor.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the accompanying drawings.

[0008]

Referring to FIG. 1, a digital camera 10 of this embodiment includes a lens 12, and a light image incident from the lens 12 is applied to a CCD imager 14 via a color filter (not shown). The CCD imager 14
An electric signal (progressive scan signal) of each pixel is output according to the progressive scan (pixel sequential scan). The progressive scan signal from the CCD imager 14 is given to a CDS / AGC circuit 16. C
The DS / AGC circuit 16 performs well-known noise removal and level adjustment on the progressive scan signal. The progressive scan signal subjected to such processing is 12
The data is converted into digital data (image data) by the A / D converter 18 at a reference clock rate (reference speed) of MHz. The signal processing circuit 20 performs well-known white balance adjustment and gamma correction on the 12 MHz image data.

The decoder 28 writes the 12 MHz image data output from the signal processing circuit 20 to the input buffer 22 at the same clock rate of 12 MHz, and then reads the image data at a high clock rate of 48 MHz. The read image data is provided to the SDRAM 26 via the data input path 24a formed on the bus 24. The decoder 28 converts this image data into four times four times 12 MHz.
SDRAM 2 at 8 MHz clock rate (first speed)
Write to 6. Note that the input buffer 22
An O memory is used.

[0010] The decoder 28 also operates during the period in which image data is not read from the input buffer 22.
Image data is repeatedly read twice from
Character data is read from the DRAM 26 once. The clock rate (second speed) at the time of reading is also 48 MHz.
It is. The first read image data is written to the output buffer 30 via the data output path 24b, and the next read image data is written to the output buffer 32 via the data output path 24c. The character data is written to the output buffer 34 via the data output path 24d. That is, the decoder 28 outputs the output buffers 30, 32 and 34 at different times from each other.
It is driven at a clock rate of 8 MHz, whereby the respective data is written to output buffers 30, 32 and 34, respectively. The output buffers 30, 32
And 34 are also FIFO memories.

The data written in the output buffers 30, 32 and 34 in this manner is subsequently read out at a clock rate of 12 MHz. Output buffer 3
The image data read from 0 is supplied to the zoom circuit 36, and the image data read from the output buffer 32 is supplied to the zoom circuit 38. Each zoom circuit 3
The zoom processing is performed on a part of the image data by 6 and 38 to create zoom image data. Switch SW
1 is connected to one of the zoom circuits 36 and 38 according to the window pulses H _WIN and V _WIN output from the window pulse generation circuit 40. Therefore, each zoom image data is selectively input to the character synthesizing circuit 42. On the other hand, the character data read from the buffer 34 is directly input to the character synthesizing circuit 42. This character data is bitmap data that is displayed on-screen as needed.

The character synthesizing circuit 42 is provided for the operator.
The character data is combined with the zoom image data according to the instruction.
To achieve. The image data output from the character synthesizing circuit 42
The data is read by the encoder 44 as Y data and C data.
Is converted to That is, the data read from the SDRAM 26
Image data and character data are YUV data
As a result, the output from the character synthesizing circuit 42 is
This image data is also YUV data.
UV data is converted into Y data and C
Converted to data. Y data obtained in this way
And C data are provided to LCD 46, for example, as shown in FIG.
2 images are displayed. In other words, Win
The H shown in FIG._WINPulse
And V_{WI N}If either pulse is low
If the switch SW1 is connected to the zoom circuit 36 side,
Zoom image data corresponding to image 1 is selected. Also,
H _WINPulse and V_WINBoth pulses are high level
If so, the switch SW1 is connected to the zoom circuit 38 side.
You. Thereby, the zoom image data corresponding to the image 2
Is selected. Note that when character data is synthesized
At this time, a character is displayed at a predetermined position.

The decoder 28, based on the H pulse as shown in FIG. 3 (A), has the configuration shown in FIGS. 3 (B), (E), (F),
Write pulses W1 to W5 and read pulses R1 to R as shown in (I), (J), (M), (N) and (Q).
4, R5a to R5c are output. During a period in which the write pulse W1 shown in FIG.
Is output to the input buffer 22 at a clock rate of 48 MHz.

Each time 4N-bit image data is stored in the input buffer 22, the decoder 28 stores the stored 4N-bit image data.
The bit image data is read at a clock rate of 48 MHz. That is, the read pulse R1 is given to the input buffer 22 at the timing shown in FIG. 3E, and the image data is continuously read out by 4N bits. Assuming that a period required to write 4N-bit image data at a clock rate of 12 MHz is a 4N-bit period, a period required to read 4N-bit image data at a clock rate of 48 MHz is a 1N-bit period. Thus, the read pulse R1 rises for every 1N bit period for only 1N bit period.

As can be seen from FIG. 3E, the SDRAM 26 has a write pulse W5 having the same waveform as the read pulse R1.
Is given. Therefore, at the same time as reading from the input buffer 22, the read 4N bits (first predetermined amount)
Is written to the SDRAM 26. SD
The RAM 26 also has a read pulse R5a output from the decoder 28 and having the same pulse width as the write pulse W5.
To R5c are input at timings shown in FIGS. 3 (F), (J) and (N). Thereby, the SDRAM 26
, The same image data is repeatedly read, and character data is read. Each of the image data and the character data is read out at a clock rate of 48 MHz by 4N bits (second predetermined amount).
Write pulse W2 having the same waveform as read pulse R5a is applied to output buffer 30, write pulse W3 having the same waveform as read pulse R5b is applied to output buffer 32, and write pulse W4 having the same waveform as read pulse R5c. Is supplied to the output buffer 34. Therefore, the image data read first is written to the output buffer 30, the image data read second is written to the output buffer 32, and the character data is written to the output buffer 34.

The decoder 28 further includes a decoder 28 shown in FIG.
As shown in (M) and (Q), read pulses R2 to R4 having the same waveform and phase as write pulse W1 are output and applied to output buffers 30, 32 and 34. SD
The data read from the RAM 26 is written to the output buffers 30, 32 and 34 every 4N bits at a clock rate of 48 MHz, and thereafter, at 12 MHz.
At the clock rate of That is, data written over a 1N-bit period is read out over a 4N-bit period.

As can be seen from FIGS. 3 (F), 3 (J) and 3 (N), the read pulses R5a to R5c rise at different times from each other for only the 1N bit period. There is no overlap with time. In other words, the times when the bus 24 is occupied for writing and reading image data and reading character data are different from each other. The image data output from the input buffer 22 is written to the SDRAM 26 at a clock rate of 48 MHz every 1N bit period, and is read from the SDRAM 26 at a clock rate of 48 MHz every 1N bit period. On the other hand, 4N-bit data is written to the input buffer 22 at a clock rate of 12 MHz during the 4N-bit period, and 4N-bit data is written at a clock rate of 12 MHz from the output buffers 30, 32, and 34 during the 4N-bit period. Is read. That is, the period during which the bus 24 is occupied for writing to the SDRAM 26 and the writing speed are correlated with each other, and the period during which the bus 24 is occupied for reading from the SDRAM 26 and the reading speed are also correlated with each other. .

As can be seen from FIGS. 3B to 3E, the period for writing data to the input buffer 22 and the period for reading data partially overlap. In addition, FIG.
As can be seen from (I), (J) to (M) and (N) to (Q), the data writing periods and the reading periods for the output buffers 30, 32, and 34 also partially overlap. And, from the problem of the occupation time of the bus 24 described above,
Each overlap period is different. For this reason, the minimum capacity required by each buffer may be different depending on the overlap time. That is, for example, the input buffer 22
With regard to (2), the reading of this image data is started immediately after the writing of the 4N-bit image data, and the reading is completed in the 1N-bit period.

However, in this embodiment, the input buffer 2
2 and output buffers 30, 32 and 34 all have the same capacity, and the capacity value is 8N bits.
That is, it is twice the amount of data that is continuously read or written at a clock rate of 48 MHz. By setting the capacitance value in this way, the input buffer 2
2 and the output buffer 3
The data write timing at 0, 32, and 34 can be arbitrarily changed.

According to this embodiment, since a highly versatile SDRAM is used as a memory for storing image data, the cost can be reduced. The clock rate used for writing image data and reading image data and character data is 12 MHz.
Since it is faster, a plurality of data can be read from the SDRAM, and a plurality of images can be displayed on the LCD.

In this embodiment, the clock rate for writing to and reading from the SDRAM 26 is set to 48 MHz.
However, since the SDRAM operates properly even at a clock rate of about 100 MHz, the write and read clock rates may be further increased. Then, more images can be displayed on the LCD. In this embodiment, an SDRAM is used as a memory for storing image data.
SGRAM (synchronous graphic RAM) may be used instead of DRAM. Further, in this embodiment, the high-speed clock rate is set to 48 MHz.
In order to avoid the data collision in No. 4, the clock rate may be increased to about 50 MHz. The character data is a type of image data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an illustrative view showing one portion of an operation of the embodiment in FIG. 1;

FIG. 3 is a timing chart showing a part of the operation of the embodiment in FIG. 1;

[Description of Signs] 10 Digital camera 22 Input buffer 30, 32, 34 Output buffer 24 Bus 26 SDRAM 28 Decoder

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI // G06F 3/153 336

Claims (6)

[Claims] A memory having a single port; a bus having a single data input path and a plurality of data output paths in parallel with each other; and input image data input from the single data input path being compared with a reference speed. First writing means for writing to the memory at a faster first speed, and a plurality of output image data individually read out from the memory at a second speed faster than the reference speed, and output from each of the plurality of data output paths. The first speed is correlated with a first occupation period in which the first writing unit occupies the bus, and the second speed is a second speed in which the first reading unit occupies the bus. A digital camera that correlates to two occupancy periods. 2. The method according to claim 1, wherein the writing means stores the input image data in a first
2. The digital camera according to claim 1, wherein a predetermined amount is written to said memory, and said readout unit reads each said output image data from said memory by a second predetermined amount. 3. An input buffer connected to the data input path and temporarily holding the input image data, and temporarily storing the output image data connected to and corresponding to each of the plurality of data output paths. 3. The digital camera according to claim 2, further comprising a plurality of output buffers for holding the output buffers. 4. The digital camera according to claim 3, wherein said input buffer has a capacity at least twice as large as said first predetermined amount, and each of said output buffers has at least twice as much capacity as said second predetermined amount. . 5. The digital camera according to claim 2, wherein said first speed and said second speed are equal to each other, and said first predetermined amount and said second predetermined amount are equal to each other. 6. The digital camera according to claim 1, wherein said memory is a synchronous DRAM.