JPH11214444A - Semiconductor device and circuit board - Google Patents

Semiconductor device and circuit board

Info

Publication number
JPH11214444A
JPH11214444A JP10011777A JP1177798A JPH11214444A JP H11214444 A JPH11214444 A JP H11214444A JP 10011777 A JP10011777 A JP 10011777A JP 1177798 A JP1177798 A JP 1177798A JP H11214444 A JPH11214444 A JP H11214444A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor device
wiring board
printed wiring
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10011777A
Other languages
Japanese (ja)
Inventor
Yuji Nishitani
祐司 西谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP10011777A priority Critical patent/JPH11214444A/en
Publication of JPH11214444A publication Critical patent/JPH11214444A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【課題】作業性及び接続の信頼性を向上し得る半導体装
置及び回路基板を実現し難かつた。 【解決手段】半導体装置において、半導体チツプの他面
に、当該他面よりも大きい外寸を有する這上り防止手段
をその周辺部が当該半導体チツプの他面の各端部からそ
れぞれ突出するように固着するようにした。また回路基
板において、一面側に複数の突起電極が形成された半導
体チツプの他面側に、当該半導体チツプの他面よりも大
きい外寸を有する這上り防止手段を当該這上り防止手段
の周辺部が当該半導体チツプの他面の各端部からそれぞ
れ突出するように固着された半導体装置と、プリント配
線板とを設け、半導体装置をプリント配線板上に封止樹
脂を介してフリツプチツプ実装するようにした。
(57) [Summary] It has been difficult to realize a semiconductor device and a circuit board capable of improving workability and connection reliability. In a semiconductor device, a crawling prevention means having an outer dimension larger than the other surface is provided on the other surface of the semiconductor chip such that a peripheral portion thereof protrudes from each end of the other surface of the semiconductor chip. It was fixed. In the circuit board, on the other surface of the semiconductor chip having a plurality of protruding electrodes formed on one surface, a crawling prevention device having an outer dimension larger than the other surface of the semiconductor chip is provided on a peripheral portion of the crawling prevention device. And a printed wiring board provided so as to protrude from each end of the other surface of the semiconductor chip, and a flip-chip mounting of the semiconductor device on the printed wiring board via a sealing resin. did.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【目次】以下の順序で本発明を説明する。[Table of Contents] The present invention will be described in the following order.

【0002】発明の属する技術分野 従来の技術(図3) 発明が解決しようとする課題(図3) 課題を解決するための手段 発明の実施の形態 (1)本実施の形態による半導体装置の構成(図1) (2)本実施の形態の動作及び効果(図2) (3)他の実施の形態(図1及び図2) 発明の効果2. Description of the Related Art Conventional technology (FIG. 3) Problems to be solved by the invention (FIG. 3) Means for solving the problems (FIG. 1) (2) Operation and effect of this embodiment (FIG. 2) (3) Other embodiments (FIGS. 1 and 2) Effects of the invention

【0003】[0003]

【発明の属する技術分野】本発明は半導体装置及び回路
基板に関し、例えばフリツプチツプ実装に適用して好適
なものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a circuit board, and is preferably applied to, for example, flip-chip mounting.

【0004】[0004]

【従来の技術】近年、エレクトロニクス機器は軽薄短小
傾向を強め、高機能集積化及び信号処理の高速化が進ん
できており、これに伴い半導体チツプの電極間ピツチも
100〔μm 〕以下が要求されるようになつてきている。
2. Description of the Related Art In recent years, electronic devices have become lighter, thinner and smaller, and high-performance integration and high-speed signal processing have been progressing. As a result, the pitch between electrodes of semiconductor chips has also increased.
A requirement of 100 [μm] or less has been required.

【0005】この場合このような電極間ピツチの狭い半
導体チツプをはんだを用いてプリント配線板上に実装す
ることは技術的に極めて困難であり、また耐環境性が全
世界的に重要視されてきていることから、近年では半導
体チツプをはんだを用いることなくプリント配線板の実
装面にフリツプチツプ実装する方法が盛んに検討されて
きている。
In this case, it is technically extremely difficult to mount such a semiconductor chip having a narrow pitch between electrodes on a printed wiring board by using solder, and environmental resistance is regarded as important worldwide. Therefore, in recent years, methods for flip-chip mounting a semiconductor chip on a mounting surface of a printed wiring board without using solder have been actively studied.

【0006】そしてこのようなフリツプチツプ実装法の
1つとして、従来、エポキシ等の樹脂を用いた方法があ
る。
As one of the flip chip mounting methods, there is a method using a resin such as epoxy.

【0007】実際上このようなフリツプチツプ実装法で
は、まず図3(A)に示すように半導体チツプ1の一面
1Aに所定パターンで形成された各電極2上にそれぞれ
めつき法、蒸着法又はワイヤーボンド法等を用いて金バ
ンプ3を形成すると共に、これと対応するプリント配線
板4の実装面4Aの所定部位上に導電粒子を含む又は含
まない液体状若しくはフイルム状のエポキシ等の樹脂材
料からなる封止樹脂6をデイスペンス、印刷法又は張付
け法等の方法により供給する。
In practice, in such a flip chip mounting method, first, as shown in FIG. 3A, a plating method, a vapor deposition method, or a wire method is applied to each electrode 2 formed in a predetermined pattern on one surface 1A of a semiconductor chip 1. The gold bumps 3 are formed using a bonding method or the like, and a predetermined portion of the mounting surface 4A of the printed wiring board 4 corresponding to the gold bumps 3 is formed from a liquid or film-like resin material such as epoxy containing or not containing conductive particles. The sealing resin 6 is supplied by a method such as dispense, printing, or pasting.

【0008】次いでこの状態において実装装置を用いて
そのボンデイングツール7に半導体チツプ1を吸着保持
させ、当該半導体チツプ1の各金バンプ3とプリント配
線板4のそれぞれ対応するランド5とが対向するように
位置決めさせる。
Next, in this state, the semiconductor chip 1 is sucked and held by the bonding tool 7 by using the mounting apparatus so that each gold bump 3 of the semiconductor chip 1 and the corresponding land 5 of the printed wiring board 4 face each other. Position.

【0009】次に図3(B)に示すようにボンデイング
ツール7を下降させ半導体チツプ1の各金バンプ3とプ
リント配線板4のそれぞれ対応するランド5とを当接さ
せた後、ボンデイングツール7により半導体チツプ1を
プリント配線板4の厚み方向に所定圧力で加圧する一
方、これと共に所定温度で加熱し、この後図3(C)に
示すようにこのボンデイングツール7を半導体チツプ1
上から取り除く。
Next, as shown in FIG. 3B, the bonding tool 7 is lowered to bring each gold bump 3 of the semiconductor chip 1 into contact with a corresponding land 5 of the printed wiring board 4, and then the bonding tool 7 The semiconductor chip 1 is pressed at a predetermined pressure in the thickness direction of the printed wiring board 4 while being heated at a predetermined temperature, and then the bonding tool 7 is moved to the semiconductor chip 1 as shown in FIG.
Remove from above.

【0010】この結果半導体チツプ1の周辺に加熱され
た封止樹脂6のフイレツト6Aが収縮しながら硬化する
とき半導体チツプ1とプリント配線板4との間に引き合
うような力が加えられることにより、封止樹脂6が導電
粒子を含む場合には半導体チツプ1の各金バンプ3とこ
れに対応するプリント配線板4の各ランド5とが導電粒
子を介して電気的に接続され、封止樹脂6が導電粒子を
含まない場合には半導体チツプ1の各金バンプ3とこれ
に対応するプリント配線板4の各ランド5とが直接電気
的に接続され、かくしてプリント配線板4の実装面4A
に半導体チツプ1を実装することができる。
As a result, when the heat is applied to the periphery of the semiconductor chip 1 and the cured resin 6A of the sealing resin 6 contracts and hardens, a force is applied between the semiconductor chip 1 and the printed wiring board 4 so as to be attracted. When the sealing resin 6 contains conductive particles, each gold bump 3 of the semiconductor chip 1 and each corresponding land 5 of the printed wiring board 4 are electrically connected via the conductive particles, and the sealing resin 6 Does not contain conductive particles, each gold bump 3 of the semiconductor chip 1 and each corresponding land 5 of the printed wiring board 4 are directly electrically connected, and thus the mounting surface 4A of the printed wiring board 4
The semiconductor chip 1 can be mounted on the semiconductor chip.

【0011】[0011]

【発明が解決しようとする課題】ところがこのような方
法によると、加圧及び加熱工程(図3(B))において
封止樹脂6が加熱されて硬化反応が始まる直前の温度に
達したときに、当該封止樹脂6の粘度が急激に低下する
ため、半導体チツプ1の外にはみ出した封止樹脂6が半
導体チツプ1の側面を這い上がり、ボンデイングツール
7に付着する場合がある。
However, according to such a method, when the sealing resin 6 is heated in the pressing and heating step (FIG. 3B) to reach a temperature immediately before the curing reaction starts, Since the viscosity of the sealing resin 6 suddenly decreases, the sealing resin 6 protruding outside the semiconductor chip 1 may crawl up the side surface of the semiconductor chip 1 and adhere to the bonding tool 7.

【0012】そしてこの後、半導体チツプ1から離れた
ボンデイングツール7に付着する封止樹脂6は図3
(C)のようにボンデイングツール7に硬化した状態で
付着するため、当該ボンデイングツール7を清掃しなけ
れば次のボンデイング作業ができない問題があつた。
Thereafter, the sealing resin 6 attached to the bonding tool 7 separated from the semiconductor chip 1 is removed as shown in FIG.
As shown in FIG. 3C, since the adhesive adheres to the bonding tool 7 in a hardened state, the next bonding operation cannot be performed unless the bonding tool 7 is cleaned.

【0013】かかる問題を解決する1つの方法として、
封止樹脂6のプリント配線板4への供給工程(図3
(A))時に当該封止樹脂6の供給量を少なくする方法
も考えられるものの、この方法によると今度は加圧及び
加熱工程(図3(B))において、半導体チツプ1の周
辺に十分な封止樹脂6のフイレツト6Aが形成されない
ため、半導体チツプ1の各金バンプ3とこれに対応する
プリント配線板4の各ランド5とが電気的に接続し難く
なり、半導体チツプ1とプリント配線板4との接続の信
頼性が大きく低下する問題があつた。
As one method for solving such a problem,
Step of supplying sealing resin 6 to printed wiring board 4 (FIG. 3)
Although a method of reducing the supply amount of the sealing resin 6 at the time of (A)) is conceivable, according to this method, in the pressing and heating steps (FIG. 3B), a sufficient area around the semiconductor chip 1 is provided. Since the fill 6A of the sealing resin 6 is not formed, it is difficult to electrically connect each gold bump 3 of the semiconductor chip 1 and each land 5 of the corresponding printed wiring board 4, so that the semiconductor chip 1 and the printed wiring board are hardly connected. There is a problem that the reliability of the connection with No. 4 is greatly reduced.

【0014】さらに上述のようなフリツプチツプ実装法
では、半導体チツプ1を高密度に実装することができる
反面、半導体チツプ1から放出される熱を効率良く外部
に放出し難く、この結果半導体チツプ1が消費電力の高
いものであつた場合に当該半導体チツプ1が自ら放出し
た熱により破損するおそれがあつた。
Further, in the flip chip mounting method described above, the semiconductor chip 1 can be mounted at a high density, but it is difficult for the semiconductor chip 1 to efficiently radiate the heat radiated from the semiconductor chip 1 to the outside. If the power consumption is high, the semiconductor chip 1 may be damaged by the heat emitted by itself.

【0015】本発明は以上の点を考慮してなされたもの
で、作業性及び接続の信頼性を向上し得る半導体装置及
び回路基板を実現しようとするものである。
The present invention has been made in consideration of the above points, and has as its object to realize a semiconductor device and a circuit board which can improve workability and connection reliability.

【0016】[0016]

【課題を解決するための手段】かかる課題を解決するた
め本発明においては、半導体装置において、半導体チツ
プの他面に、当該他面よりも大きい外寸を有する這上り
防止手段をその周辺部が当該半導体チツプの他面の各端
部からそれぞれ突出するように固着するようにした。
According to the present invention, there is provided, in a semiconductor device, a semiconductor device, comprising a semiconductor chip having a crawling prevention means having an outer dimension larger than that of the other surface. The semiconductor chip is fixed so as to protrude from each end of the other surface of the semiconductor chip.

【0017】この結果この半導体装置では、この這上り
防止手段により半導体チツプの外にはみ出し当該半導体
チツプの側面を這い上がる封止樹脂をせき止めることが
できるため、半導体装置をプリント配線板上に連続して
実装することができる。
As a result, in the semiconductor device, the sealing resin that protrudes outside the semiconductor chip and creeps up on the side surface of the semiconductor chip can be damped by the rise preventing means, so that the semiconductor device can be continuously connected to the printed wiring board. Can be implemented.

【0018】また本発明においては、回路基板におい
て、一面側に複数の突起電極が形成された半導体チツプ
の他面側に、当該半導体チツプの他面よりも大きい外寸
を有する這上り防止手段を当該這上り防止手段の周辺部
が当該半導体チツプの他面の各端部からそれぞれ突出す
るように固着された半導体装置と、プリント配線板とを
設け、半導体装置をプリント配線板上に封止樹脂を介し
てフリツプチツプ実装するようにした。
According to the present invention, in the circuit board, on the other surface side of the semiconductor chip having a plurality of protruding electrodes formed on one surface side, a crawling prevention means having an outer dimension larger than the other surface of the semiconductor chip is provided. A semiconductor device and a printed wiring board, which are fixed so that the peripheral portion of the climbing-up prevention means protrudes from each end of the other surface of the semiconductor chip, are provided, and the semiconductor device is mounted on the printed wiring board with a sealing resin. The flip chip was implemented via.

【0019】この結果この回路基板では、この這上り防
止手段により半導体チツプの外にはみ出し当該半導体チ
ツプの側面を這い上がる封止樹脂をせき止めることがで
きるため、半導体装置をプリント配線板上に連続して実
装することができる。
As a result, in the circuit board, the sealing device that sticks out of the semiconductor chip and rises on the side surface of the semiconductor chip can be damped by the rise preventing means, so that the semiconductor device can be continuously mounted on the printed wiring board. Can be implemented.

【0020】[0020]

【発明の実施の形態】以下図面について、本発明の一実
施の形態を詳述する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

【0021】(1)本実施の形態による半導体装置の構
成 図1において10は全体として本実施の形態による半導
体装置を示し、半導体チツプ1上の各電極2が形成され
た一面1Aと相対する他面1B側に接着剤11を介して
這上り防止板12が固着されることにより構成されてい
る。
(1) Configuration of Semiconductor Device According to the Present Embodiment In FIG. 1, reference numeral 10 denotes a semiconductor device according to the present embodiment as a whole, which is opposed to one surface 1A on a semiconductor chip 1 on which electrodes 2 are formed. The crawling prevention plate 12 is fixed to the surface 1B via an adhesive 11.

【0022】この場合這上り防止板12は、半導体チツ
プ1の他面1Bよりも大きい外寸(例えば半導体チツプ
1の四辺よりも0.5 〔mm〕ずつ大きい四辺を有する程
度)で形成されており、その周辺部が当該半導体チツプ
1の他面1Bの各端部からそれぞれ突出すると共に、そ
の中心が半導体チツプ1の他面1Bと一致するように当
該半導体チツプ1に固着されている。
In this case, the crawling prevention plate 12 is formed to have an outer dimension larger than the other surface 1B of the semiconductor chip 1 (for example, having four sides larger by 0.5 mm than the four sides of the semiconductor chip 1). The peripheral portion protrudes from each end of the other surface 1B of the semiconductor chip 1 and is fixed to the semiconductor chip 1 such that its center coincides with the other surface 1B of the semiconductor chip 1.

【0023】これによりこの半導体装置10では、図3
(A)〜図(C)について上述したフリツプチツプ実装
法によりプリント配線板4上に加圧及び加熱処理を経て
実装する際に、半導体チツプ1の外にはみ出した封止樹
脂6が当該半導体チツプ1の側面を這い上がるのをこの
這上り防止板12によつてせき止めることができるよう
になされている。この実施の形態の場合、這上り防止板
12は例えば熱伝導率の高い銅を用いて形成されてお
り、例えば銀ペースト(エポキシ系の樹脂材料の中に銀
を入れたもの)等の熱伝導性が高い接着剤11を用いて
半導体チツプ1上に固着されている。
As a result, in this semiconductor device 10, FIG.
(A) to (C), when the semiconductor chip 1 is mounted on the printed wiring board 4 by applying the pressure and heat treatment by the flip-chip mounting method described above, the sealing resin 6 protruding from the semiconductor chip 1 is removed. The crawling up of the side surface can be blocked by the crawling up prevention plate 12. In the case of this embodiment, the crawling prevention plate 12 is made of, for example, copper having high thermal conductivity, and is made of, for example, a heat conductive material such as silver paste (silver in an epoxy resin material). It is fixed on the semiconductor chip 1 by using an adhesive 11 having a high property.

【0024】これによりこの半導体装置10では、半導
体チツプ1から放出される熱を接着剤11及び這上り防
止板12を順次介して効率良く外部に放出することがで
き、かくして半導体チツプ1が消費電力の高いものであ
つた場合においても当該半導体チツプ1が自ら放出する
熱により破損するのを未然に防止し得るようになされて
いる。
As a result, in the semiconductor device 10, the heat radiated from the semiconductor chip 1 can be efficiently radiated to the outside via the adhesive 11 and the anti-roll-up plate 12 in order, and thus the semiconductor chip 1 consumes power. The semiconductor chip 1 can be prevented from being damaged by the heat emitted by the semiconductor chip 1 even when the semiconductor chip 1 is high.

【0025】(2)本実施の形態の動作及び効果 以上の構成においてこの半導体装置10は、図3(A)
〜図3(C)との対応部分に同一符号を付した図2
(A)〜図2(C)に示す以下の手順によりプリント配
線板4の実装面4A上に実装することができる。
(2) Operation and Effect of the Present Embodiment In the above configuration, the semiconductor device 10 has the structure shown in FIG.
FIG. 2 in which the same reference numerals are assigned to corresponding parts to FIG.
It can be mounted on the mounting surface 4A of the printed wiring board 4 by the following procedures shown in FIGS.

【0026】すなわちまず図2(A)に示すように、プ
リント配線板4の実装面4Aにおいける対応する位置に
封止樹脂6を供給すると共に、実装装置のボンデイング
ツール7によりこの半導体装置10を吸着保持させ、当
該半導体装置10を半導体チツプ1の各金バンプ3とプ
リント配線板4のそれぞれ対応するランド5とが対向す
るように位置決めさせる。
That is, first, as shown in FIG. 2A, the sealing resin 6 is supplied to a corresponding position on the mounting surface 4A of the printed wiring board 4, and the semiconductor device 10 is supplied by a bonding tool 7 of the mounting device. And the semiconductor device 10 is positioned so that the gold bumps 3 of the semiconductor chip 1 and the corresponding lands 5 of the printed wiring board 4 face each other.

【0027】続いて図2(B)に示すように、ボンデイ
ングツール7を下降させて半導体装置10上の半導体チ
ツプ1の各金バンプ3とプリント配線板4のそれぞれ対
応するランド5とを当接させた後、ボンデイングツール
7により半導体チツプ1をプリント配線板4の厚み方向
に所定圧力及び所定温度で加圧及び加熱し、この後図2
(C)に示すようにボンデイングツール7を半導体装置
10上から取り除く。
Subsequently, as shown in FIG. 2B, the bonding tool 7 is lowered to bring each gold bump 3 of the semiconductor chip 1 on the semiconductor device 10 into contact with a corresponding land 5 of the printed wiring board 4. After that, the semiconductor chip 1 is pressed and heated at a predetermined pressure and a predetermined temperature in a thickness direction of the printed wiring board 4 by a bonding tool 7.
The bonding tool 7 is removed from the semiconductor device 10 as shown in FIG.

【0028】この結果加熱された封止樹脂6のフイレツ
ト6Bが収縮しながら硬化するときに半導体装置10と
プリント配線板4との間に引き合うような力が生じるこ
とにより、封止樹脂6が導電粒子を含む場合には半導体
装置10の半導体チツプ1の各金バンプ3とこれに対応
するプリント配線板4の各ランド5とが導電粒子を介し
て電気的に接続され、封止樹脂6が導電粒子を含まない
場合には半導体装置10の半導体チツプ1の各金バンプ
3とこれに対応するプリント配線板4の各ランド5とが
直接電気的に接続され、かくしてプリント配線板4の実
装面4Aに半導体装置10が実装される。
As a result, a force is generated between the semiconductor device 10 and the printed wiring board 4 when the heated filler 6B of the sealing resin 6 is cured while shrinking, so that the sealing resin 6 becomes conductive. When particles are included, each gold bump 3 of the semiconductor chip 1 of the semiconductor device 10 and each corresponding land 5 of the printed wiring board 4 are electrically connected through conductive particles, and the sealing resin 6 is electrically conductive. When no particles are contained, each gold bump 3 of the semiconductor chip 1 of the semiconductor device 10 and each corresponding land 5 of the printed wiring board 4 are directly electrically connected, and thus the mounting surface 4A of the printed wiring board 4 The semiconductor device 10 is mounted.

【0029】この場合半導体装置10を加圧及び加熱す
る際(図2(B))に半導体チツプ1の外にはみ出した
封止樹脂6が当該半導体チツプ1の側面を這い上がるも
のの、この封止樹脂6は這上り防止板12によつてせき
止められる。
In this case, when the semiconductor device 10 is pressurized and heated (FIG. 2B), the sealing resin 6 protruding outside the semiconductor chip 1 crawls up the side surface of the semiconductor chip 1. The resin 6 is blocked by the climb-up prevention plate 12.

【0030】従つてこの半導体装置10では、ボンデイ
ングツール7に封止樹脂6が付着するのを確実に防止す
ることができる。またこの半導体装置10では、プリン
ト配線板4上に連続でボンデイングすることができると
共に、封止樹脂6の供給量を少なくする必要がないこと
から、半導体チツプ1の周辺に十分な封止樹脂6のフイ
レツト6Bを形成することができる。
Therefore, in the semiconductor device 10, it is possible to reliably prevent the sealing resin 6 from adhering to the bonding tool 7. Further, in the semiconductor device 10, since the bonding can be continuously performed on the printed wiring board 4 and the supply amount of the sealing resin 6 does not need to be reduced, a sufficient amount of the sealing resin 6 is provided around the semiconductor chip 1. Can be formed.

【0031】さらにこの半導体装置10では、這上り防
止板12の材料として熱伝導率の高い金属材料を用いて
いるため、半導体チツプ1が消費電力の高いものであつ
た場合においても半導体チツプ1の熱を効率良く外部に
放出することができ、その分半導体チツプ1が自ら放出
した熱により破損するのを未然に防止することができ
る。
Further, in the semiconductor device 10, since the metal material having high thermal conductivity is used as the material of the anti-climbing plate 12, even if the semiconductor chip 1 has high power consumption, the semiconductor chip 1 can be used. The heat can be efficiently released to the outside, and accordingly, the semiconductor chip 1 can be prevented from being damaged by the heat released by itself.

【0032】以上の構成によれば、半導体チツプ1上の
各電極2が形成された一面1Aと相対する他面1B側に
這上り防止板12を設けるようにしたことにより、プリ
ント配線板4上に実装する際に封止樹脂6が半導体チツ
プ1の側面を這い上がるのをこの這上り防止板12によ
つてせき止めることができ、ボンデイングツール7に封
止樹脂6が付着するのを確実に防止することができる。
かくするにつき半導体装置10をプリント配線板4上に
連続でボンデイングすることができると共に、当該半導
体装置10の半導体チツプ1の周辺に十分な封止樹脂6
のフイレツト6Bを形成することができ、かくして作業
性及び接続の信頼性を向上し得る半導体装置10を実現
することができる。
According to the above configuration, the anti-roll-up plate 12 is provided on the other surface 1B of the semiconductor chip 1 opposite to the one surface 1A on which the electrodes 2 are formed. When the sealing resin 6 is mounted on the semiconductor chip 1, it is possible to prevent the sealing resin 6 from creeping up the side surface of the semiconductor chip 1 with the use of the anti-climbing plate 12, thereby reliably preventing the sealing resin 6 from adhering to the bonding tool 7. can do.
As a result, the semiconductor device 10 can be continuously bonded on the printed wiring board 4 and a sufficient sealing resin 6 is provided around the semiconductor chip 1 of the semiconductor device 10.
Thus, the semiconductor device 10 capable of improving workability and connection reliability can be realized.

【0033】(3)他の実施の形態 なお上述の実施の形態においては、這上り防止手段とし
ての這上り防止板12を銅を用いて形成するようにした
場合について述べたが、本発明はこれに限らず、要は熱
伝導率の高い材料を用いて這上り防止板12を形成する
ものであればその材料としては、この他例えばアルミニ
ウム等の種々の材料を広く適用することができる。
(3) Other Embodiments In the above-described embodiment, a case has been described in which the anti-climbing plate 12 as anti-climbing means is formed using copper. However, the material is not limited to this, and as long as the material for forming the anti-climbing plate 12 is formed of a material having a high thermal conductivity, various other materials such as aluminum can be widely used.

【0034】また上述の実施の形態においては、接着剤
11を銀ペーストを用いるようにした場合について述べ
たが、本発明はこれに限らず、要は熱伝導性の高い接着
材料を用いるものであればその材料としては、この他種
々の接着材料を使用する場合においても適用できる。
Further, in the above-described embodiment, the case where the silver paste is used for the adhesive 11 has been described. However, the present invention is not limited to this, and the key is to use an adhesive material having high thermal conductivity. If so, the material can be applied to the case where various other adhesive materials are used.

【0035】さらに上述の実施の形態においては、這上
り防止板12を半導体チツプ1の四辺よりも0.5 〔mm〕
ずつ大きい四辺を有する形状で形成するようにした場合
について述べたが、本発明はこれに限らず、要は這上り
防止板12の周辺部が半導体チツプ1の他面1Bの各端
部からそれぞれ突出するような形状であればその形状と
しては、この他種々の形状を広く適用することができ
る。
Further, in the above-described embodiment, the crawling prevention plate 12 is set to be 0.5 mm more than the four sides of the semiconductor chip 1.
Although the case of forming the shape having four larger sides has been described, the present invention is not limited to this, and the point is that the peripheral portion of the crawling prevention plate 12 is formed from each end of the other surface 1B of the semiconductor chip 1 respectively. As long as the shape protrudes, various other shapes can be widely applied.

【0036】[0036]

【発明の効果】上述のように本発明によれば、半導体装
置において、半導体チツプの他面に、当該他面よりも大
きい外寸を有する這上り防止手段をその周辺部が当該半
導体チツプの他面の各端部からそれぞれ突出するように
固着するようにしたことにより、半導体チツプの外には
み出し当該半導体チツプの側面を這い上がる封止樹脂を
当該這上り防止手段によりせき止めることができるた
め、半導体装置をプリント配線板上に連続して実装する
ことができ、かくして作業性及び接続の信頼性を向上し
得る半導体装置を実現できる。
As described above, according to the present invention, in a semiconductor device, a crawling prevention means having an outer dimension larger than the other surface is provided on the other surface of the semiconductor chip. By fixing the sealing resin so as to protrude from each end of the surface, the sealing resin that protrudes outside the semiconductor chip and rises on the side surface of the semiconductor chip can be dammed by the rise preventing means. The device can be continuously mounted on the printed wiring board, and thus a semiconductor device capable of improving workability and connection reliability can be realized.

【0037】また上述のように本発明によれば、回路基
板において、一面側に複数の突起電極が形成された半導
体チツプの他面側に、当該半導体チツプの他面よりも大
きい外寸を有する這上り防止手段を当該這上り防止手段
の周辺部が当該半導体チツプの他面の各端部からそれぞ
れ突出するように固着された半導体装置と、プリント配
線板とを設け、半導体装置をプリント配線板上に封止樹
脂を介してフリツプチツプ実装するようにしたことによ
り、半導体チツプの外にはみ出し当該半導体チツプの側
面を這い上がる封止樹脂を当該這上り防止手段によりせ
き止めることができため、半導体装置をプリント配線板
上に連続して実装することができ、かくして作業性及び
接続の信頼性を向上し得る半導体装置の実装方法を実現
できる。
As described above, according to the present invention, the circuit board has a larger outer dimension than the other surface of the semiconductor chip on the other surface side of the semiconductor chip having the plurality of projecting electrodes formed on one surface side. A semiconductor device fixed to the crawling prevention means such that a peripheral portion of the crawling prevention means protrudes from each end of the other surface of the semiconductor chip; and a printed wiring board, and the semiconductor device is mounted on the printed wiring board. Since the flip chip is mounted on the semiconductor chip via the sealing resin, the sealing resin that protrudes outside the semiconductor chip and crawls on the side surface of the semiconductor chip can be dammed up by the crawling prevention means. A semiconductor device mounting method which can be continuously mounted on a printed wiring board and thus can improve workability and connection reliability can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本実施の形態による半導体装置の構成を示す断
面図である。
FIG. 1 is a sectional view showing a configuration of a semiconductor device according to the present embodiment.

【図2】本実施の形態による半導体装置の実装手順の説
明に供する断面図である。
FIG. 2 is a cross-sectional view for explaining a mounting procedure of the semiconductor device according to the present embodiment;

【図3】従来のフリツプチツプ実装法による半導体チツ
プの実装手順の説明に供する断面図である。
FIG. 3 is a cross-sectional view for explaining a mounting procedure of a semiconductor chip by a conventional flip-chip mounting method.

【符号の説明】[Explanation of symbols]

1……半導体チツプ、1A……一面、1B……他面、2
……電極、3……金バンプ、4……プリント配線板、4
A……実装面、5……ランド、6……封止樹脂、6A、
6B……フイレツト、7……ボンデイングツール、10
……半導体装置、11……接着剤、12……這上り防止
板。
1 ... Semiconductor chip, 1A ... One side, 1B ... Other side, 2
…… electrode, 3 …… gold bump, 4 …… printed wiring board, 4
A: mounting surface, 5: land, 6: sealing resin, 6A,
6B: Fillet, 7: Bonding tool, 10
... Semiconductor device, 11... Adhesive, 12.

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】一面側に複数の突起電極が形成された半導
体チツプを有し、プリント配線板上に封止樹脂を介して
フリツプチツプ実装される半導体装置において、 上記半導体チツプの上記他面よりも大きい外寸を有する
と共に、周辺部が上記半導体チツプの上記他面の各端部
からそれぞれ突出するように上記半導体チツプの上記他
面側に固着された這上り防止手段を具えることを特徴と
する半導体装置。
1. A semiconductor device having a semiconductor chip having a plurality of protruding electrodes formed on one surface side and being flip-chip mounted on a printed wiring board via a sealing resin, wherein the semiconductor chip is mounted on the printed wiring board with a higher height than the other surface of the semiconductor chip. The semiconductor chip has a large outer dimension, and a crawling prevention means fixed to the other surface of the semiconductor chip so that a peripheral portion protrudes from each end of the other surface of the semiconductor chip. Semiconductor device.
【請求項2】上記這上り防止手段は、熱伝導率の高い材
料からなることを特徴とする請求項1に記載の半導体装
置。
2. The semiconductor device according to claim 1, wherein said climb-up preventing means is made of a material having high thermal conductivity.
【請求項3】上記這上り防止手段は、熱伝導性が高い接
着剤を用いて上記半導体チツプの上記他面に固着された
ことを特徴とする請求項2に記載の半導体装置。
3. The semiconductor device according to claim 2, wherein said crawling prevention means is fixed to said other surface of said semiconductor chip using an adhesive having high thermal conductivity.
【請求項4】一面側に複数の突起電極が形成された半導
体チツプの他面側に、上記半導体チツプの上記他面より
も大きい外寸を有する這上り防止手段を上記這上り防止
手段の周辺部が上記半導体チツプの上記他面の各端部か
らそれぞれ突出するように固着された半導体装置と、 一面側に上記半導体チツプの各上記突起電極にそれぞれ
対応させて複数の電極が形成されたプリント配線板とを
具え、 上記半導体装置の上記半導体チツプの各上記突起電極が
それぞれ上記プリント配線板の対応する各上記電極と接
合するように、上記半導体装置が上記プリント配線板上
に封止樹脂を介してフリツプチツプ実装されたことを特
徴とする回路基板。
4. A semiconductor chip having a plurality of protruding electrodes formed on one surface thereof, and a creep preventing means having an outer dimension larger than the other surface of the semiconductor chip is provided on the other surface of the semiconductor chip. A semiconductor device fixed in such a manner that a portion thereof protrudes from each end of the other surface of the semiconductor chip, and a print in which a plurality of electrodes are formed on one surface side in correspondence with the respective protruding electrodes of the semiconductor chip. A wiring board, and the semiconductor device is provided with a sealing resin on the printed wiring board so that each of the protruding electrodes of the semiconductor chip of the semiconductor device is bonded to each of the corresponding electrodes of the printed wiring board. A circuit board characterized by being flip-chip mounted via the board.
【請求項5】上記這上り防止手段は、熱伝導率の高い材
料からなることを特徴とする請求項4に記載の回路基
板。
5. The circuit board according to claim 4, wherein said climb-up preventing means is made of a material having high thermal conductivity.
【請求項6】上記這上り防止手段は、熱伝導性が高い接
着剤を用いて上記半導体チツプの上記他面に固着された
ことを特徴とする請求項5に記載の回路基板。
6. The circuit board according to claim 5, wherein said climb-up preventing means is fixed to said other surface of said semiconductor chip by using an adhesive having high thermal conductivity.
JP10011777A 1998-01-23 1998-01-23 Semiconductor device and circuit board Pending JPH11214444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10011777A JPH11214444A (en) 1998-01-23 1998-01-23 Semiconductor device and circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10011777A JPH11214444A (en) 1998-01-23 1998-01-23 Semiconductor device and circuit board

Publications (1)

Publication Number Publication Date
JPH11214444A true JPH11214444A (en) 1999-08-06

Family

ID=11787395

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10011777A Pending JPH11214444A (en) 1998-01-23 1998-01-23 Semiconductor device and circuit board

Country Status (1)

Country Link
JP (1) JPH11214444A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012174722A (en) * 2011-02-17 2012-09-10 Hitachi Chem Co Ltd Semiconductor device manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012174722A (en) * 2011-02-17 2012-09-10 Hitachi Chem Co Ltd Semiconductor device manufacturing method

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