JPH11214682A - Fabrication of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce junction capacity between a source-drain region and a semiconductor substrate. SOLUTION: The method for fabricating a semiconductor device having source-drain regions 10, 11 formed contiguously to a gate electrode 8 being formed on a gate insulator on the surface of a semiconductor substrate 1 comprises a step for forming a first impurity region 12A for preventing punch- through beneath the gate electrode 8 and a second impurity region 12B in a region deeper than the source-drain regions 10, 11 by implanting boron ions into the substrate 1 at an acceleration voltage high enough for the boron ions to penetrate the gate electrode 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor substrate and a source / drain region formed by a punch-through prevention region formed to prevent punch-through between a source region and a drain region. The present invention relates to a method for manufacturing a semiconductor device that suppresses an increase in junction capacitance between the semiconductor devices.

[0002]

2. Description of the Related Art As the density of LSIs increases, the gate length of integrated MOS devices becomes shorter, and the short channel effect becomes more pronounced. As a means for suppressing the short channel effect, a method of forming the drain into a double structure of a low-concentration layer and a high-concentration layer, such as an LDD (Lightly Doped Drain) structure, has conventionally been used.

[0003] In FIG. 13, a semiconductor substrate 51 of one conductivity type, for example, a P-type is approximately 4500 by a LOCOS method.
After forming the element isolation film 52 having a thickness of Å, a dummy oxide film 61 having a thickness of about 500 形成 is formed in the active region excluding the element isolation film 52. In FIG. 14, for example, boron ions are
By implanting at an acceleration voltage of 0 KeV and an implantation amount of approximately 6.0 × 10 12 / cm 2, a punch-through preventing region 54 is formed in a desired region. Thereafter, the dummy oxide film 61 is removed, and the gate insulating film 53 having a thickness of about 70
To form

In FIG. 15, a gate electrode 55 is formed by forming a polysilicon film having a thickness of, for example, about 2000 ° on the gate insulating film 53 and patterning the same, and using the gate electrode 55 as a mask, an N-type By implanting impurities, for example, phosphorus ions at an acceleration voltage of about 20 KeV and an implantation amount of about 4.0 × 10 13 / cm 2, low concentration source / drain regions 56 and 57 are formed adjacent to the gate electrode 55. . Then, after forming a sidewall spacer film 58 so as to cover the side wall portion of the gate electrode 55, an N-type impurity is formed by using the sidewall spacer film 58 and the gate electrode 55 as a mask.
For example, high-concentration source / drain regions 59 and 60 are formed adjacent to the sidewall spacer film 58 by implanting arsenic ions at an acceleration voltage of approximately 100 KeV and an injection amount of approximately 5.0 × 10 15 / cm 2. Semiconductor devices.

At this time, as shown in FIG. 15, ion implantation is performed on the entire surface of the active region, and the punch-through preventing region 54 is formed.
Is formed at a desired position below the gate electrode 55, the punch-through prevention region 54 comes into contact with the high-concentration source / drain regions 59 and 60, and the junction capacitance between the source / drain regions 59 and 60 and the substrate is reduced. Increase. Therefore, it has hindered the speeding up of the circuit operation.

Further, if a punch-through preventing region is formed only below the gate electrode using a mask, the junction capacity is not increased because ion implantation for preventing punch-through is not performed in the source / drain regions. However, in this case, alignment is required because the alignment is not self-aligned.

[0007]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device which can reduce a junction capacitance between a source / drain region and a semiconductor substrate.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and the present invention according to claim 1 is formed on a gate insulating film on the surface of a semiconductor substrate of one conductivity type. In a method of manufacturing a semiconductor device, wherein a source / drain region is formed in a surface layer of a substrate so as to be adjacent to a gate electrode, an impurity of one conductivity type is implanted into the substrate at a high acceleration voltage through the gate electrode. A step of forming a first impurity region for preventing punch-through near the lower portion of the gate electrode and a second impurity region in a region deeper than the formation region of the source / drain regions.

According to a second aspect of the present invention, an element isolation film is formed on a semiconductor substrate of one conductivity type by a LOCOS method, and a well of an opposite conductivity type is formed on the substrate by a retrograde well method. Next, after forming a gate insulating film on the substrate surface and then forming a gate electrode on the gate insulating film, low-concentration one-conductivity-type impurities are implanted into the gate electrode by using the gate electrode as a mask. A low concentration source / drain region is formed adjacently. A side wall spacer formed so as to cover a side wall portion of the gate electrode after forming an anti-punch-through region below the gate electrode by injecting impurities of a reverse conductivity type with a high acceleration voltage penetrating the gate electrode. Forming a high-concentration source / drain region adjacent to the sidewall spacer film by implanting high-concentration one-conductivity-type impurities using the film and the gate electrode as a mask.

Further, according to the present invention, an element isolation film is formed on a semiconductor substrate of one conductivity type by a LOCOS method, and a well of an opposite conductivity type is formed on the substrate by a retrograde well method. Next, after forming a gate insulating film on the surface of the substrate and forming a gate electrode on the gate insulating film, low-concentration one-conductivity-type impurities are implanted into the gate electrode by using the gate electrode as a mask. A low concentration source / drain region is formed adjacently. Then, a high-concentration one-conductivity-type impurity is implanted by using the sidewall spacer film and the gate electrode formed as masks to cover the sidewall portions of the gate electrode, and the high-concentration impurity is implanted adjacent to the sidewall spacer film. After forming the source / drain regions, a step of injecting impurities of the opposite conductivity type at a high acceleration voltage penetrating the gate electrode to form a punch-through preventing region below the gate electrode.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, an element isolation film 2 having a thickness of about 4500 ° is formed on a semiconductor substrate 1 of one conductivity type, for example, a P-type by a LOCOS method. In FIG. 2, the substrate 1 was formed by a retrograde well method.
After the resist film 3 is formed at the desired position above, a P-type impurity, for example, boron ions is implanted at an acceleration voltage of about 190 KeV and an implantation amount of about 1.5.times.10@13 / cm @ 2, so that a P-well is formed in the substrate. 4 is formed.

In FIG. 3, after a resist film 5 is formed at a desired position on the substrate 1 by a retrograde well method, an N-type impurity, for example, phosphorus ions is accelerated at an acceleration voltage of about 380 KeV, about 1.5 × 10 13 / cm
The N well 6 is formed in the substrate by injecting at an implantation amount of 2. In FIG. 4, after a gate insulating film 7 having a thickness of about 70 ° is formed in an active region except for the element isolation film 2, a polysilicon film having a thickness of, for example, about 2000 ° is formed and patterned to form a gate electrode 8. To form

In FIG. 5, after a resist film 9 is formed at a desired position on the substrate 1, N-type impurities, for example, phosphorus ions are roughly removed by using the resist film 9, the gate electrode 8 and the element isolation film 2 as a mask. An accelerating voltage of 20 KeV,
By implanting at a dose of about 4.0.times.10@13 / cm @ 2, a low-concentration source
Drain regions 10 and 11 are formed.

In FIG. 6, implantation conditions for penetrating the gate electrode 8 using the resist film 9 and the element isolation film 2 as a mask, an acceleration voltage of about 110 KeV, and about 6.0
By implanting a P-type impurity, for example, boron ions at an implantation amount of × 10 12 / cm 2, the first impurity region 12A and the low-concentration source
The second impurity region 12B is formed in a region sufficiently deeper than the formation region of the drain regions 10 and 11. In addition, the first
Impurity region 12A functions as a punch-through prevention region.

In FIG. 7, after a resist film 13 is formed at a desired position on the substrate 1, a P-type impurity such as difluoride is formed by using the resist film 13, the gate electrode 8 and the element isolation film 2 as a mask. About 20 Ke of boron ions
By implanting at a V accelerating voltage of about 2.0 × 10 13 / cm 2, low concentration source / drain regions 14 and 15 are formed adjacent to the gate electrode 8.

In FIG. 8, implantation conditions for penetrating the gate electrode 8 using the resist film 13 and the element isolation film 2 as a mask, an acceleration voltage of about 300 KeV, and about 4.
By implanting N-type impurities, for example, phosphorus ions at a dose of 0 × 10 12 / cm 2, the first impurity region 16A and the low-concentration source
The second impurity region 16B is formed in a region sufficiently deeper than the region where the drain regions 14 and 15 are formed. In this case as well, the first impurity region 16A functions as a punch-through prevention region.

Referring to FIG. 9, a sidewall spacer film 17 is formed so as to cover the side wall of the gate electrode 8. In FIG. 10, after a resist film 18 is formed at a desired position on the substrate 1, an N-type impurity such as an N-type impurity is formed by using the resist film 18, the sidewall spacer film 17, the gate electrode 8 and the element isolation film 2 as a mask. Arsenic ions are accelerated at an acceleration voltage of about 100 KeV, about 5.0 × 10
By implanting at a dose of 15 / cm <2>, high concentration source / drain regions 19 and 20 are formed adjacent to the sidewall spacer film 17.

In FIG. 11, after a resist film 21 is formed at a desired position on the substrate 1, the resist film 21,
Using the side wall spacer film 17, the gate electrode 8 and the element isolation film 2 as a mask, a P-type impurity such as boron difluoride ion is implanted at an acceleration voltage of about 40 KeV and an injection amount of about 2.0 × 10 15 / cm 2. by doing,
Highly doped source / drain regions 22 and 23 are formed adjacent to the sidewall spacer film 17.

Thus, a semiconductor device as shown in FIG. 12 is formed. At this time, as shown in FIG. 12, the second impurity regions 12B and 16B are formed in regions deeper than the diffusion depth of the high-concentration source / drain regions 19, 20, 22, and 23. The junction capacitance between the substrates can be reduced as compared with the related art, and the speed of the circuit operation can be increased.

In one embodiment of the present invention, after the low concentration source / drain region is formed using the gate electrode as a mask, ion implantation for forming a punch-through prevention region is performed using the same mask. However, the present invention is not limited to this. For example, after forming a side wall spacer film covering the side wall of the gate electrode and forming a high concentration source / drain region adjacent to the side wall spacer film, the same mask is used. May be used to perform ion implantation for forming a punch-through prevention region.

Also in this case, since the punch-through preventing region is formed in a region deeper than the diffusion depth of the high-concentration source / drain region, the junction capacitance between the source / drain region and the substrate can be reduced as compared with the conventional case. And speeding up the circuit operation.

[0022]

As described above, according to the present invention, the punch-through preventing region is formed near the lower portion of the gate electrode by performing the ion implantation for forming the punch-through preventing region under the implantation condition penetrating the gate electrode. In this case, a punch-through prevention region is formed in a sufficiently deep region below the source / drain region, so that the junction capacitance between the source / drain region and the substrate can be reduced as compared with the conventional case, and the circuit operation can be speeded up. I can do it.

[Brief description of the drawings]

FIG. 1 is a first sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 3 is a third sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 4 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 5 is a fifth sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a sixth sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 7 is a seventh sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 8 is an eighth sectional view showing the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 9 is a ninth cross-sectional view illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention;

FIG. 10 is a tenth cross-sectional view illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention;

FIG. 11 is an eleventh cross-sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 12 is a twelfth cross-sectional view illustrating the method for manufacturing the semiconductor device of one embodiment of the present invention;

FIG. 13 is a first cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 14 is a second cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 15 is a third cross-sectional view showing a conventional method for manufacturing a semiconductor device.

Claims (3)

[Claims] 1. A method for manufacturing a semiconductor device comprising: a source / drain region formed in a surface layer of a substrate so as to be adjacent to a gate electrode formed on a gate insulating film on a surface of a semiconductor substrate of one conductivity type; Implanting an impurity of one conductivity type at a high accelerating voltage penetrating the gate electrode, a first impurity region for preventing punch-through near the lower portion of the gate electrode, and a region deeper than the formation region of the source / drain region Forming a second impurity region in the semiconductor device. 2. A step of forming an element isolation film on a semiconductor substrate of one conductivity type by a LOCOS method; a step of forming an opposite conductivity type well on the substrate by a retrograde well method; and forming a gate insulating film on a surface of the substrate. Forming a gate electrode on the gate insulating film after formation; implanting a low-concentration one-conductivity-type impurity into the substrate using the gate electrode as a mask; Forming a source / drain region; a step of implanting a reverse conductivity type impurity at a high accelerating voltage penetrating the gate electrode to form a punch-through preventing region below the gate electrode; and forming a side wall portion of the gate electrode. A high-concentration one-conductivity-type impurity is implanted by using the side wall spacer film and the gate electrode formed so as to cover the mask as a mask and adjacent to the side wall spacer film. The method of manufacturing a semiconductor device characterized by a step of forming a heavily doped source and drain regions of the so that. 3. A step of forming an element isolation film on a semiconductor substrate of one conductivity type by a LOCOS method, a step of forming a reverse conductivity type well on the substrate by a retrograde well method, and forming a gate insulating film on a surface of the substrate. Forming a gate electrode on the gate insulating film after formation; implanting a low-concentration one-conductivity-type impurity into the substrate using the gate electrode as a mask; Forming a source / drain region; and implanting a high-concentration one-conductivity-type impurity by using the sidewall spacer film and the gate electrode formed so as to cover the sidewalls of the gate electrode as a mask. Forming a high-concentration source / drain region adjacent to the film; and implanting a reverse conductivity type impurity at a high acceleration voltage penetrating the gate electrode. The method of manufacturing a semiconductor device characterized by a step of the gate electrode lower to form the punch-through prevention region.