JPH11214903A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide with a small number of item parts a field-effect transistor(FET) which has superior electrical characteristics. SOLUTION: An insulation ceramic part 12 is extended toward a FET chip 15, a metalized open stub 17 is formed on its top surface and a capacitance component is added. The stub 17 is preferably divided into plural parts and they are selectively interconnected by a bonding wire 18. Consequently, it is possible to get an inexpensive FET that has a superior electrical characteristic with a small number of item parts and to adjust a capacitance component by correcting manufacturing dispersion as necessary.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (hereinafter referred to as "FET"), and more particularly to a gallium arsenide (GaAs) FET suitable for high frequency power amplification.

[0002]

2. Description of the Related Art FETs are widely used as alternative amplifiers for vacuum tubes because of their good linearity, substantially no input power consumption, and operating characteristics similar to vacuum tubes.

[0003] Depending on the semiconductor material used, such FETs are divided into those based on silicon and those based on compound semiconductors centered on GaAs.
Especially since the mobility of the carrier is large,
GaAs FETs are widely used for high frequency signal amplification, and power GaAs FETs are used for high frequency power amplification.

The prior art of such an FET is disclosed in, for example,
No. 0-66048, JP-A-64-4710 and JP-A-2-246251.
The structure of these conventional FETs will be described below with reference to the accompanying drawings, particularly FIGS. First, in the conventional FET shown in FIG. 2, the FET chip 5 is directly mounted on the package heat sink portion 1. The heat sink 1 is generally formed of a good heat conductive metal such as aluminum. For example, a rectangular insulating ceramic portion 2 surrounding the FET chip 5 is formed on the heat sink portion 1. The package lead part 3 is fixed on the upper surface of the insulating ceramic part 2. Electrical connection is made between the electrode of the FET chip 5 and the package lead section 3 by a well-known bonding wire 4 using, for example, a gold wire.

In the conventional FET shown in FIG. 3, a package heat sink portion 1 ', an FET chip 5', an insulating ceramic portion 2 ', and a package lead portion 3' are provided.
Is similar to the FET of FIG. However, the FET of FIG. 3 differs from the FET of FIG. 2 in that chip capacitors 6a and 6b are arranged between both sides of the FET chip 5 'and the inner wall of the insulating ceramic portion 2.
Different from ET. Therefore, the electrode of the FET chip 5 '
The chip capacitors 6a and 6b are connected by an extremely short bonding wire 4a.
a and 6b are electrically connected to the package lead portions 3 'via bonding wires 4b.

[0006]

In the field of electronics in recent years, there is an increasing demand for FETs with higher output and higher gain. For this reason, the gate width of the FET chip increases, which causes problems such as lowering the impedance and increasing the inductance between the bonding wire and the package lead.

However, in the FET shown in FIG. 2, it is difficult to achieve high gain and high output even if an external matching circuit is used.

The FET shown in FIG. 3 is of an internal matching type in which a chip capacitor is used for matching, so that high gain and high output characteristics can be obtained at high frequencies.
There has been a problem that the number of parts increases and the number of assembling or manufacturing steps increases as compared with ET, resulting in an increase in cost.

Accordingly, it is an object of the present invention to provide an FET, especially a power GaAs FET, which uses a small number of parts and reduces the number of assembling steps and has good high-frequency amplification characteristics.

[0010]

In order to solve the above-mentioned problems, a field-effect transistor according to the present invention has the following characteristic configuration.

(1) In a field effect transistor in which an FET chip arranged on a package heat sink is connected to a package lead on the upper surface of an insulating ceramic part by a bonding wire, the insulating ceramic part is connected to the F.
A field-effect transistor that extends toward the ET chip and forms an open stub on the top.

(2) The field effect transistor according to (1), wherein the open stub is separately formed into a plurality of pieces and selectively connected by a bonding wire.

(3) The field effect transistor according to (1), wherein the open stub is selectively separated.

(4) The field-effect transistor according to (2), wherein the open stub is divided into three parts in advance.

(5) The FET chip is a power GaAs.
The field effect transistors according to (1) to (4), which are FETs.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a field effect transistor according to the present invention will be described below in detail with reference to the drawings. Note that this embodiment is merely an example and does not limit the scope of the present invention.

FIG. 1 shows a power GaAs FET of the present invention.
3A is a plan view, and FIG. 3B is a cross-sectional view. This FET has a package heat sink 11,
It has a configuration similar to that of the FET of FIG. 2 in that it has an FET chip 15, an insulating ceramic portion 12, and a package lead portion 13 on the upper surface thereof. However, as is clear from FIGS. 1A and 1B, it should be noted that the insulating ceramic portion 12 extends in the direction of the FET chip 15, that is, inwardly, and narrows the space therebetween. Thereby, the FET chip 15
Bonding wire 14 between package lead portion 13
Is extremely short, and its inductance is reduced.

Further, in the FET of the present invention, FIG.
As is clear from the plan view of FIG.
Has an open stub 17 formed by, for example, aluminum evaporation or the like. According to this preferred embodiment, the open stub 17 is formed separately in three stages indicated by and. These three-stage open stubs 17 can be interconnected by bonding wires 18 as necessary.

In the FET having such a configuration, the inductance of the bonding wire 14 is equal to that of the conventional FET shown in FIG.
Smaller than It should be noted that the inductance component of the package lead portion 13 forms a capacitor component at a high frequency due to the formation of the open stub 17, and has the same effect as a chip capacitor. Therefore, internal matching is possible without using a chip capacitor as in the conventional FET shown in FIG. That is, high gain and high output characteristics can be realized by external matching using external inductance and capacitance (capacitor).

Further, by separating the open stub 17 into a plurality of parts and combining (interconnecting) them with the bonding wires 18, it is possible to use the band in a wide range. Furthermore, the open stub 17 separated into a plurality
Has the effect of correcting (adjusting) variations in the characteristics of the FET during mass production together with the bonding wire 18.

The preferred embodiment of the FET according to the present invention has been described above. The FET according to the present invention is characterized in that the insulating ceramic portion 12 is widened and the metalized open stub 17 is formed on the upper surface thereof. The present invention can be variously modified without being limited to the above embodiment. For example, open stubs are formed continuously and trimmed (cut) with a laser beam etc. after manufacturing / assembly,
The capacitance component of the package lead 13 may be adjusted to a desired optimum value.

[0022]

As can be understood from the above description, according to the FET of the present invention, the insulating ceramic portion formed around the FET chip and formed on the package heat sink portion is formed by the FET.
Spreading to the chip side, the width of the upper surface of the insulating ceramic portion is widened, and a metallized open stub is formed on the upper surface to impart a capacitance component to perform internal matching. Therefore, an FET having excellent electrical characteristics with a small number of parts can be obtained at a low cost, and the capacitance component can be adjusted if necessary or by correcting the manufacturing variation, thereby making it possible to adjust the capacitance component. Present.

[Brief description of the drawings]

FIG. 1 shows a FET according to a preferred embodiment of the present invention;
(A) is a plan view and (B) is a sectional view.

FIG. 2 shows an example of a conventional FET, where (A) is a plan view,
(B) is a sectional view.

3A and 3B show another example of a conventional FET, in which FIG. 3A is a plan view and FIG. 3B is a cross-sectional view.

[Explanation of symbols]

 11 Package Heat Sink 12 Insulating Ceramic 13 Package Lead 14, 18 Bonding Wire 15 FET Chip 17 Open Stub

Claims (5)

[Claims] An F disposed on a heat sink of a package.
A field effect transistor in which an ET chip is connected to a package lead portion on an upper surface of an insulating ceramic portion by a bonding wire, wherein the insulating ceramic portion is expanded toward the FET chip and an open stub is formed on the upper surface. Transistor. 2. The method according to claim 1, wherein the open stub is separated into a plurality of pieces.
2. The field effect transistor according to claim 1, wherein the field effect transistor is selectively connected by a bonding wire. 3. The field effect transistor according to claim 1, wherein said open stub is selectively separated. 4. The field effect transistor according to claim 2, wherein said open stub is formed in advance into three parts. 5. The power semiconductor device according to claim 1, wherein the FET chip is a power GaAs FE.
5. The field effect transistor according to claim 1, wherein T is T.