JPH11233515A - 半導体装置の多層配線平坦化方法 - Google Patents
半導体装置の多層配線平坦化方法Info
- Publication number
- JPH11233515A JPH11233515A JP10232206A JP23220698A JPH11233515A JP H11233515 A JPH11233515 A JP H11233515A JP 10232206 A JP10232206 A JP 10232206A JP 23220698 A JP23220698 A JP 23220698A JP H11233515 A JPH11233515 A JP H11233515A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- dielectric material
- metallization level
- metallization
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
- H10W20/48—Insulating materials thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
- H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
- H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
- H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H10P14/6923—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
- H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
- H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
- H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/092—Manufacture or treatment of dielectric parts thereof by smoothing the dielectric parts
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT97RM000431A IT1293536B1 (it) | 1997-07-14 | 1997-07-14 | Procedimento di metallizzazione multilivello ad alta planarizzazione per dispositivi a semiconduttore |
| IT97A000431 | 1997-07-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11233515A true JPH11233515A (ja) | 1999-08-27 |
Family
ID=11405176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10232206A Pending JPH11233515A (ja) | 1997-07-14 | 1998-07-14 | 半導体装置の多層配線平坦化方法 |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0897193A3 (2) |
| JP (1) | JPH11233515A (2) |
| KR (1) | KR19990013850A (2) |
| IT (1) | IT1293536B1 (2) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN120261401B (zh) * | 2025-05-30 | 2025-09-26 | 合肥晶合集成电路股份有限公司 | 半导体结构及其制造方法 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5063175A (en) * | 1986-09-30 | 1991-11-05 | North American Philips Corp., Signetics Division | Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material |
| US5612254A (en) * | 1992-06-29 | 1997-03-18 | Intel Corporation | Methods of forming an interconnect on a semiconductor substrate |
| US5366911A (en) * | 1994-05-11 | 1994-11-22 | United Microelectronics Corporation | VLSI process with global planarization |
| JP2836529B2 (ja) * | 1995-04-27 | 1998-12-14 | 日本電気株式会社 | 半導体装置の製造方法 |
-
1997
- 1997-07-14 IT IT97RM000431A patent/IT1293536B1/it active IP Right Grant
-
1998
- 1998-07-14 JP JP10232206A patent/JPH11233515A/ja active Pending
- 1998-07-14 EP EP98305603A patent/EP0897193A3/en not_active Withdrawn
- 1998-07-14 KR KR1019980028388A patent/KR19990013850A/ko not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990013850A (ko) | 1999-02-25 |
| ITRM970431A0 (2) | 1997-07-14 |
| EP0897193A2 (en) | 1999-02-17 |
| EP0897193A3 (en) | 1999-08-04 |
| ITRM970431A1 (it) | 1999-01-14 |
| IT1293536B1 (it) | 1999-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5872052A (en) | Planarization using plasma oxidized amorphous silicon | |
| US6774048B2 (en) | Method of manufacturing a semiconductor device | |
| KR100494955B1 (ko) | 유동성희생산화물을이용하는이중다마신법을사용한다층동일평면금속/절연체막형성방법 | |
| US6235629B1 (en) | Process for producing a semiconductor device | |
| US5296092A (en) | Planarization method for a semiconductor substrate | |
| US5747382A (en) | Two-step planarization process using chemical-mechanical polishing and reactive-ion-etching | |
| US6287956B2 (en) | Multilevel interconnecting structure in semiconductor device and method of forming the same | |
| US20050059234A1 (en) | Method of fabricating a dual damascene interconnect structure | |
| US5234864A (en) | Method for interconnecting layers in a semiconductor device using two etching gases | |
| US6350688B1 (en) | Via RC improvement for copper damascene and beyond technology | |
| US6147005A (en) | Method of forming dual damascene structures | |
| US6278189B1 (en) | High density integrated circuits using tapered and self-aligned contacts | |
| KR100350111B1 (ko) | 반도체 장치의 배선 및 이의 제조 방법 | |
| US6114253A (en) | Via patterning for poly(arylene ether) used as an inter-metal dielectric | |
| WO2004010495A1 (ja) | 半導体装置の製造方法 | |
| JP2573621B2 (ja) | 電気的相互接続部の製造方法 | |
| US6236091B1 (en) | Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide | |
| US5723380A (en) | Method of approach to improve metal lithography and via-plug integration | |
| US6780778B2 (en) | Method for fabricating semiconductor device | |
| US5888901A (en) | Multilevel interconnection and method for making | |
| JPH11233515A (ja) | 半導体装置の多層配線平坦化方法 | |
| US6225216B1 (en) | Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide | |
| JP2001250863A (ja) | 半導体装置およびその製造方法 | |
| JPH10340952A (ja) | 集積回路の多層配線形成方法 | |
| JPH08139190A (ja) | 半導体装置の製造方法 |