JPH11233669A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH11233669A JPH11233669A JP4436698A JP4436698A JPH11233669A JP H11233669 A JPH11233669 A JP H11233669A JP 4436698 A JP4436698 A JP 4436698A JP 4436698 A JP4436698 A JP 4436698A JP H11233669 A JPH11233669 A JP H11233669A
- Authority
- JP
- Japan
- Prior art keywords
- external connection
- insulating layer
- semiconductor device
- semiconductor chip
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 229910000679 solder Inorganic materials 0.000 claims abstract description 13
- 239000011347 resin Substances 0.000 claims abstract description 9
- 229920005989 resin Polymers 0.000 claims abstract description 9
- 229920001721 polyimide Polymers 0.000 claims abstract description 7
- 239000004642 Polyimide Substances 0.000 claims description 4
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 claims description 4
- 238000007747 plating Methods 0.000 abstract description 22
- 230000008646 thermal stress Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 229920000178 Acrylic resin Polymers 0.000 abstract 1
- 239000004925 Acrylic resin Substances 0.000 abstract 1
- 239000009719 polyimide resin Substances 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000011888 foil Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- CJRQAPHWCGEATR-UHFFFAOYSA-N n-methyl-n-prop-2-ynylbutan-2-amine Chemical compound CCC(C)N(C)CC#C CJRQAPHWCGEATR-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の製造方
法に関する。The present invention relates to a method for manufacturing a semiconductor device.
【０００２】[0002]
【従来の技術】半導体装置は高機能化、小型化を要請さ
れチップサイズパッケージ或はＢＧＡ型半導体装置等が
提案されている。2. Description of the Related Art As a semiconductor device is required to have high functionality and small size, a chip size package or a BGA type semiconductor device has been proposed.
【０００３】一般にこれら半導体装置はサイズが小さく
且つ多ピンであり、その外部接続端子は小ピッチで多
数、例えば一辺１０ｍｍの正方形のサイズの配線基板或
は半導体チップ下面に９００ピン以上の外部接続端子を
必要とするものがある。In general, these semiconductor devices are small in size and have many pins, and their external connection terminals are many at a small pitch, for example, a wiring board having a square size of 10 mm on a side or an external connection terminal having 900 pins or more on the lower surface of a semiconductor chip. There is something that needs.
【０００４】[0004]
【この発明が解決しようとする課題】従来の半導体装置
では外部接続端子として半田ボ−ルを溶着して設置した
ものであるが、半田ボ−ルの設置にはピッチの微小化に
限界があり超多ピンへの対応が難しいのが実情である。In a conventional semiconductor device, solder balls are welded and installed as external connection terminals. However, there is a limit to the miniaturization of pitch in the installation of solder balls. It is a fact that it is difficult to handle very many pins.
【０００５】また仮に前記半田ボ−ルがピッチを狭くし
例えば０．３ｍｍ未満の間隔で設置できたとしても、マ
ザ−ボ−ドへのクリ−ム半田を使用した表面実装の際
に、短絡発生の点から一括して実装できない問題があ
る。[0005] Even if the solder balls are narrowed in pitch and can be installed at intervals of, for example, less than 0.3 mm, a short circuit occurs during surface mounting using cream solder on a mother board. There is a problem that it cannot be implemented collectively from the point of occurrence.
【０００６】また、半田ボ−ルが多ピン化につれて小さ
くなると、半導体チップとマザ−ボ−ドの熱膨張係数差
に起因して生じる熱応力を吸収しきれず、剥離或はクラ
ックが発生する。If the solder ball becomes smaller as the number of pins increases, the thermal stress generated due to the difference in thermal expansion coefficient between the semiconductor chip and the motherboard cannot be absorbed, and peeling or cracking occurs.
【０００７】本発明は外部接続端子が小ピッチで形成さ
れ、且つマザ−ボ−ドへの表面実装が短絡することなく
行え、また半導体チップとマザ−ボ−ドの熱膨張係数差
による熱応力を吸収する能力がすぐれた外部接続端子を
設けた半導体装置を得ることを目的とする。According to the present invention, external connection terminals are formed at a small pitch, surface mounting on a motherboard can be performed without short-circuit, and thermal stress due to a difference in thermal expansion coefficient between the semiconductor chip and the motherboard. It is an object of the present invention to obtain a semiconductor device provided with an external connection terminal having an excellent ability to absorb the heat.
【０００８】[0008]
【課題を解決するための手段】本発明の要旨は、半導体
チップの下面側に外部接続端子を絶縁層及び配線パタ−
ンを介在して設けた半導体装置の製造方法において、半
導体チップの下面に第１絶縁層を半導体チップのバンプ
を露出して設け、該第１絶縁層の下面に配線パタ−ンを
形成し、前記配線パタ−ンの下面に第２絶縁層を設ける
とともに外部接続端子形成予定箇所の第２絶縁層を除去
し、前記第２絶縁層より厚いポリイミド、アクリル等の
感光性樹脂からなる第３絶縁層を第２絶縁層に重ねて設
け、前記第３絶縁層に外部接続端子形成パタ−ンを焼付
け現像して外部接続端子形成予定箇所に外部接続突起を
形成し、該外部接続突起にめっきを施すとともに半田め
っきを施して外部接続端子を形成する半導体装置の製造
方法にある。The gist of the present invention is that an external connection terminal is provided on the lower surface of a semiconductor chip with an insulating layer and a wiring pattern.
Forming a first insulating layer on the lower surface of the semiconductor chip by exposing the bumps of the semiconductor chip, forming a wiring pattern on the lower surface of the first insulating layer, A second insulating layer is provided on the lower surface of the wiring pattern and the second insulating layer is removed at a location where an external connection terminal is to be formed, and a third insulating layer made of a photosensitive resin such as polyimide or acrylic thicker than the second insulating layer. A layer is provided on the second insulating layer, and an external connection terminal forming pattern is baked and developed on the third insulating layer to form an external connection projection at a location where the external connection terminal is to be formed, and plating is applied to the external connection projection. And a method of manufacturing a semiconductor device in which external connection terminals are formed by performing solder plating.
【０００９】[0009]
【発明の実施の形態】本発明の実施例について図面を参
照して説明する。図面において、１は半導体チップであ
り、下面側にバンプ２が多数形成されている。該半導体
チップ１の下面に第１絶縁層３例えばポリイミドフィル
ム、シリコン窒化膜、または酸化珪素膜等がバンプ２を
除く部分に設けられる。なお、半導体チップ１の下端面
角部には損傷防止のために弾性のある樹脂１２が設けら
れている。Embodiments of the present invention will be described with reference to the drawings. In the drawing, reference numeral 1 denotes a semiconductor chip, and a large number of bumps 2 are formed on the lower surface side. A first insulating layer 3 such as a polyimide film, a silicon nitride film, or a silicon oxide film is provided on the lower surface of the semiconductor chip 1 except for the bumps 2. Note that an elastic resin 12 is provided at a corner of the lower end face of the semiconductor chip 1 to prevent damage.
【００１０】４は配線パタ−ンで、前記第１絶縁層３の
下面に蒸着した金属箔例えば銅箔にレジストフィルムを
設け、これに配線パタ−ンを焼付け現像して配線パタ−
ンマスクを作成しエッチングを施して形成される。該配
線パタ−ン４は前記バンプ３と電気的に接続している。
なお、配線パタ−ン４は前記金属箔のエッチング法に限
らず、めっき或はスパッタ等で形成することができる。Reference numeral 4 denotes a wiring pattern. A resist film is provided on a metal foil, for example, a copper foil, deposited on the lower surface of the first insulating layer 3, and the wiring pattern is baked and developed thereon.
The mask is formed and etched. The wiring pattern 4 is electrically connected to the bump 3.
The wiring pattern 4 is not limited to the above-described method of etching the metal foil, but can be formed by plating or sputtering.
【００１１】５は前記配線パタ−ン４の下面を覆うよう
に設けられた第２絶縁層で、例えばポリイミドフィルム
等である。該第２絶縁層５は外部接続端子形成予定箇所
６に在る部分は外部接続端子パタ−ンの焼付け現像によ
り除去される。Reference numeral 5 denotes a second insulating layer provided so as to cover the lower surface of the wiring pattern 4, for example, a polyimide film or the like. The portion of the second insulating layer 5 located at the portion 6 where the external connection terminal is to be formed is removed by baking and developing the external connection terminal pattern.
【００１２】７は前記第２絶縁層５に重ねて設けたポリ
イミド、アクリル等の感光性樹脂からなる第３絶縁層で
あり、第２絶縁層５より厚みが大である。該第３絶縁層
７に外部接続端子形成パタ−ンを焼付け現像して外部接
続突起８を形成する。該外部接続突起８は感光性樹脂か
ら形成されているので弾力性があり熱応力を吸収する能
力がたけている。また、外部接続突起８は前記ようにパ
タ−ンの焼付け現像にて形成されるので微細なピッチで
設置できる。Reference numeral 7 denotes a third insulating layer made of a photosensitive resin such as polyimide or acrylic which is provided on the second insulating layer 5 and has a thickness larger than that of the second insulating layer 5. An external connection terminal forming pattern is formed on the third insulating layer 7 by baking and developing an external connection terminal forming pattern. Since the external connection projections 8 are formed of a photosensitive resin, they have elasticity and a capability of absorbing thermal stress. Further, since the external connection projections 8 are formed by baking and developing the pattern as described above, they can be installed at a fine pitch.
【００１３】９は前記外部接続突起８の周りに設けため
っきで、例えばＮｉめっき、Ａｕめっき、Ｐｄめっき或
は前記めっき金属から選択された積層めっきであり、該
めっきはめっきリ−ドを使用して公知の方法で施され
る。該めっき９により前記配線パタ−ン４と外部接続突
起８が電気的に接続される。Numeral 9 denotes plating provided around the external connection projections 8, for example, Ni plating, Au plating, Pd plating or a laminated plating selected from the above-mentioned plating metals, and the plating uses plating leads. And a known method. The wiring pattern 4 and the external connection projection 8 are electrically connected by the plating 9.
【００１４】前記外部接続突起８の外周或は底面部に前
記めっき９に重ねて半田めっき１０を設ける。該半田め
っき１０及び前記めっき９を外部接続突起８に設けるこ
とにより外部接続端子１１が形成される。A solder plating 10 is provided on the outer periphery or bottom surface of the external connection projection 8 so as to overlap the plating 9. The external connection terminals 11 are formed by providing the solder plating 10 and the plating 9 on the external connection protrusions 8.
【００１５】前記のようにして半導体チップ１に絶縁層
及び配線パタ−ンを介在して外部接続端子１１が設けら
れた半導体装置が製造される。As described above, a semiconductor device in which the external connection terminals 11 are provided on the semiconductor chip 1 with the insulating layer and the wiring pattern interposed therebetween is manufactured.
【００１６】[0016]
【発明の効果】本発明によると外部接続端子がポリイミ
ド、アクリル等の感光性樹脂絶縁層から外部接続端子形
成パタ−ンの焼付け現像により形成されるので、微小な
ピッチで形成され半導体装置の小型化、超多ピン化が実
現できる。また当該感光性樹脂層を骨格とする外部接続
端子は弾力性があって半導体チップとマザ−ボ−ドの熱
膨張係数差により生じる熱応力を吸収する能力がすぐ
れ、半導体チップの剥離或はクラック等が生ぜず半導体
装置の信頼性が高くなる。According to the present invention, since the external connection terminals are formed by baking and developing an external connection terminal formation pattern from a photosensitive resin insulating layer of polyimide, acrylic, or the like, the external connection terminals are formed at a fine pitch and the size of the semiconductor device is reduced. , Ultra-high pin count can be realized. Further, the external connection terminal having the photosensitive resin layer as a skeleton is resilient and has an excellent ability to absorb thermal stress caused by a difference in thermal expansion coefficient between the semiconductor chip and the mother board, so that the semiconductor chip can be separated or cracked. Does not occur, and the reliability of the semiconductor device is increased.
【００１７】また、本発明によると外部接続端子は外周
にめっきと半田めっきを形成しているので、マザ−ボ−
ドへ不活性雰囲気で半田リフロ−による表面実装ができ
る。さらに該外部接続端子は直接的な表面実装ができる
ので、何らかの理由で半導体装置の取り外しが必要にな
った場合には容易に取り外せる等の効果がある。Further, according to the present invention, since the external connection terminals are formed by plating and solder plating on the outer periphery, the mother board is formed.
Surface mounting by solder reflow in an inert atmosphere. Further, since the external connection terminal can be directly surface-mounted, there is an effect that if the semiconductor device needs to be removed for some reason, it can be easily removed.
【図１】本発明の１実施例における半導体装置の製造を
示す図。FIG. 1 is a diagram showing the manufacture of a semiconductor device according to one embodiment of the present invention.
１ 半導体チップ ２ バンプ ３ 第１絶縁層 ４ 配線パタ−ン ５ 第２絶縁層 ６ 外部接続端子形成予定箇所 ７ 第３絶縁層 ８ 外部接続突起 ９ めっき １０ 半田めっき １１ 外部接続端子 １２ 樹脂 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Bump 3 1st insulating layer 4 Wiring pattern 5 2nd insulating layer 6 Place where external connection terminal is to be formed 7 3rd insulating layer 8 External connection protrusion 9 Plating 10 Solder plating 11 External connection terminal 12 Resin
Claims (1)
絶縁層及び配線パタ−ンを介在して設けた半導体装置の
製造方法において、半導体チップの下面に第１絶縁層を
バンプを露出して設け、該第１絶縁層の下面に配線パタ
−ンを形成し、前記配線パタ−ンの下面に第２絶縁層を
設けるとともに外部接続端子形成予定箇所の第２絶縁層
を除去し、前記第２絶縁層より厚いポリイミド、アクリ
ル等の感光性樹脂からなる第３絶縁層を第２絶縁層に重
ねて設け、前記第３絶縁層に外部接続端子形成パタ−ン
を焼付け現像して外部接続突起を形成し、該外部接続突
起にめっきを施すとともに半田めっきを施して外部接続
端子を形成する半導体装置の製造方法。In a method of manufacturing a semiconductor device in which external connection terminals are provided on the lower surface side of a semiconductor chip with an insulating layer and a wiring pattern interposed, a first insulating layer is exposed on a lower surface of the semiconductor chip by exposing a bump. Forming a wiring pattern on the lower surface of the first insulating layer; providing a second insulating layer on the lower surface of the wiring pattern; and removing the second insulating layer at a location where an external connection terminal is to be formed. A third insulating layer made of a photosensitive resin such as polyimide or acrylic, which is thicker than the two insulating layers, is provided on the second insulating layer, and an external connection terminal forming pattern is baked and developed on the third insulating layer. And a method of manufacturing a semiconductor device in which the external connection protrusions are plated and solder plated to form external connection terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4436698A JPH11233669A (en) | 1998-02-10 | 1998-02-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4436698A JPH11233669A (en) | 1998-02-10 | 1998-02-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11233669A true JPH11233669A (en) | 1999-08-27 |
Family
ID=12689525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4436698A Pending JPH11233669A (en) | 1998-02-10 | 1998-02-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11233669A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6667559B2 (en) * | 2001-06-12 | 2003-12-23 | International Business Machines Corporation | Ball grid array module and method of manufacturing same |
| US7268430B2 (en) | 2004-08-30 | 2007-09-11 | Renesas Technology Corp. | Semiconductor device and process for manufacturing the same |
| JP2007250618A (en) * | 2006-03-14 | 2007-09-27 | Matsushita Electric Ind Co Ltd | Electronic component mounting structure and manufacturing method thereof |
| US7301243B2 (en) | 2004-08-30 | 2007-11-27 | Sharp Kabushiki Kaisha | High-reliable semiconductor device using hermetic sealing of electrodes |
| US8119449B2 (en) | 2006-03-14 | 2012-02-21 | Panasonic Corporation | Method of manufacturing an electronic part mounting structure |
-
1998
- 1998-02-10 JP JP4436698A patent/JPH11233669A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6667559B2 (en) * | 2001-06-12 | 2003-12-23 | International Business Machines Corporation | Ball grid array module and method of manufacturing same |
| US7268430B2 (en) | 2004-08-30 | 2007-09-11 | Renesas Technology Corp. | Semiconductor device and process for manufacturing the same |
| US7301243B2 (en) | 2004-08-30 | 2007-11-27 | Sharp Kabushiki Kaisha | High-reliable semiconductor device using hermetic sealing of electrodes |
| US7776735B2 (en) | 2004-08-30 | 2010-08-17 | Renesas Technology Corp. | Semiconductor device and process for manufacturing the same |
| JP2007250618A (en) * | 2006-03-14 | 2007-09-27 | Matsushita Electric Ind Co Ltd | Electronic component mounting structure and manufacturing method thereof |
| US8119449B2 (en) | 2006-03-14 | 2012-02-21 | Panasonic Corporation | Method of manufacturing an electronic part mounting structure |
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