JPH1125588A - Disk motor control circuit and disk reproducing apparatus using the same - Google Patents

Abstract

(57) Abstract: A disk motor control circuit capable of detecting a frequency error and performing accurate speed control of a disk motor based on the error signal, and a disk reproducing apparatus using the same. SOLUTION: An offset applying means 10 periodically takes in a frequency error, and sets D in a direction in which the frequency error disappears.
The C value is applied stepwise. Speed control can be accurately performed by adding an offset to the control output stepwise so as to eliminate the error. The offset application circuit 10 periodically takes in the output of the frequency error detection circuit 7 and applies an offset in such a direction as to eliminate the frequency error at such a low speed that the lock of the PLL circuit is not released according to the size and direction. To go. The offset applying circuit 10 may be operated by software by the system controller 9 or may be constituted by hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CD-ROM
The present invention relates to a disk motor control of a disk reproducing apparatus for reproducing an optical disk such as a VD-ROM.

[0002]

2. Description of the Related Art In the field of audio equipment, digital recording / reproducing systems are currently being developed. This system converts audio signals into digital signals using PCM (Pulse Code Modulation) technology and records them on a recording medium, such as a disk or magnetic tape, for reproduction and reproduction. I do. A CD (Compact Disc) or CD-RO configured to form a bit string corresponding to digital data on a disc and read it optically
M is currently the most widespread. This CD stores digital data (main information data) obtained by converting an analog audio signal into PCM with 16 bits. The digital data has 8 bits as one symbol and 24 symbols as one frame, and the frame is repeated to store data. In this disc, a cross interleaved Reed-Solomon code (CIRC: Cross
Interleave Reed-Solomon Code) is used.

[0003] In a disk reproducing apparatus for reproducing data from a disk, a disk is controlled by a disk motor control circuit and a disk motor at a constant linear velocity (CLV).
rotate with earVelocity). An optical pickup device having a built-in semiconductor laser or photoelectric conversion device reads data recorded on a disk by performing linear tracking from the inner circumference to the outer circumference of the disk rotated by the disk motor. The read data (current signal) is supplied to the amplifier. The amplifier converts the current signal into a broadband signal (RF signal) as a voltage signal and supplies the signal to a data slice circuit. The data slice circuit binarizes the reproduced signal and supplies it to the PLL (Phase Locked Loop) circuit and the signal processing circuit, for example, as an EFM signal. The signal processing circuit separates the synchronization signal from the EFM signal, and then performs EFM demodulation to separate the data into 32-symbol data components including parity data P and Q and subcode data components. Next, the data subjected to the EFM demodulation is written to the memory in the data processing circuit by the clock signal generated by the PLL circuit. The data read from the memory is output as 16-bit digital data after error correction. The reproduction speed is varied by the system controller.

[0004] Recent disc reproducing apparatuses, for example, CD-
Variable speed reproduction is predominant in ROMs and the like.
In the variable speed reproduction, the phase error control (APC) for the clock generated by X'tal of the frame synchronization signal performed in the constant linear velocity (CLV) reproduction is not performed, but only the frequency error control (AFC) is performed. ing. FIG. 5 shows a disk motor servo loop based on only frequency error control (AFC) that has been generally performed conventionally.
An electric signal read by the pickup (PU) 3 from the disk 1 rotated by the disk motor 2 is input to the RF amplifier 4. The RF amplifier 4 generates an RF signal based on the electric signal. The RF signal is
The signal is input to the slice / PLL circuit 5. Then, the data is binarized by the data slice circuit of the slice / PLL circuit 5 to generate an EFM (Eight to Fourteen Modulation) signal. The binarized signal EFM is sent to the PLL circuit of the slice / PLL circuit 5, where the PL signal synchronized with the EFM signal is output.
An L clock PLCK is generated. EFM signal and PLL
The clock PLCK is input to the CD processing / CD synchronization detection circuit 6 to generate a frame synchronization signal PFCK having a frequency proportional to the reproduction speed.

[0005] The frame synchronization signal PFCK is input to a frequency error detection circuit 7. Then, a clock (reference clock) CK having a reference frequency is generated from a clock generator 8 using X'tal or the like under the control of a system controller 9 and input to the frequency error detection circuit 7 in the same manner. In the frequency error detection circuit 7, the frame synchronization signal P
The frequencies of FCK and reference clock CK are compared to generate a frequency error. The difference between the frequency error signal and the
Thus, the electric power of the disk motor 2 is converted to drive the disk motor 2. The EFM signal generated by the data slice circuit is separated by the CD processing circuit of the CD processing / CD synchronization detection circuit 6 after separating the synchronization signal.
FM demodulation is performed. The CD processing circuit performs EFM demodulation, error correction, and the like, and outputs an audio signal via a digital-to-analog converter and a low-pass filter.

[0006]

In the above-described disk motor control system, the frequency error is used as the control output as it is, so that when the error disappears, power is not supplied to the disk motor. However, in an actual operation, a stable control state is achieved by a control output generated with a certain error. Therefore, accurate speed control could not be performed. As a method of obtaining more accurate speed control, it is known to increase the gain of the amplifier or insert an integrator in the servo loop to compress the error. However, in these methods, the loop characteristic has a second-order delay. Therefore, there is a problem that the servo loop tends to be unstable. The present invention has been made in view of such circumstances, and a disk motor control circuit capable of detecting a frequency error and performing accurate speed control of a disk motor based on the error signal, and a disk reproducing apparatus using the same. Provide equipment.

[0007]

According to the present invention, a frequency error is detected, and an offset is gradually added to a control output for controlling the disk motor based on the error signal so as to eliminate the error. And That is, the disk motor control circuit of the present invention generates frame synchronization signal detection means for detecting a frame synchronization signal from a disk on which a signal is recorded at a constant linear velocity, and generates a clock for comparing the frequency with the frame synchronization signal. Clock generating means, a frequency error detecting means for detecting a frequency error between the frame synchronization signal and the clock, an offset applying means for adding a DC value corresponding to the frequency error to the frequency error, Disk motor driving means for driving a disk motor using the sum of the outputs of the offset applying means as a control signal, wherein the offset applying means periodically takes in the frequency error and gradually changes the DC value in a direction to eliminate the frequency error. Is applied. A first counter that counts the number of frequency errors obtained from the frequency error detection unit, a second counter that outputs the count number obtained from the first counter in a stepwise manner, An adder may be provided for adding the count number obtained from the second counter to the output of the frequency error detecting means in a stepwise manner.

Further, a disc reproducing apparatus according to the present invention comprises: a photoelectric conversion means for optically reading data recorded on a disc on which a signal is recorded at a constant linear velocity and converting the data into an electric signal; An amplifier for amplifying the supplied electric signal; a data slice circuit for converting the electric signal supplied from the amplifier to a binary signal; and a data slice circuit for converting data based on the binary signal supplied from the data slice circuit. A PLL circuit for generating a clock signal according to a change in reproduction speed, and a signal processing circuit for demodulating the EFM signal supplied from the data slice circuit in response to the clock signal supplied from the PLL circuit and reproducing data And a disk motor control circuit for controlling rotation of the disk, wherein the disk motor control circuit Frame synchronization signal detecting means for detecting the over arm synchronization signal, a clock generating means for generating a clock for comparing the frame synchronization signal and the frequency,
Frequency error detecting means for detecting a frequency error between the frame synchronization signal and the clock; offset applying means for adding a DC value corresponding to the frequency error to the frequency error; and a sum of the frequency error and the output of the offset applying means. And a disk motor driving means for driving a disk motor with the control signal as a control signal, wherein the offset applying means periodically takes in the frequency error and applies a DC value stepwise in a direction in which the frequency error disappears. It is characterized by. Speed control can be accurately performed by adding an offset to the control output stepwise so as to eliminate the error.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a disk motor servo loop in variable speed reproduction of a disk reproducing apparatus (CD-ROM) of the present invention. An electric signal read by the pickup (PU) 3 from the disk 1 rotated by the disk motor 2 is input to the RF amplifier 4. The RF amplifier 4 generates an RF signal based on the electric signal. RF signal is slice P
Input to the LL circuit 5. Then, the data is binarized by the data slice circuit of the slice / PLL circuit 5 to generate an EFM signal. The binarized signal EFM is sent to the PLL circuit of the slice / PLL circuit 5, where a PLL clock PLCK synchronized with the EFM signal is generated. Binary signal E
The FM and the PLL clock PLCK are input to the CD processing / CD synchronization detection circuit 6 to generate a frame synchronization signal PFCK having a frequency proportional to the reproduction speed. The frame synchronization signal PFCK is input to the frequency error detection circuit 7.

A clock (reference clock) CK of a reference frequency is generated from a clock generator 8 using X'tal or the like under the control of a system controller 9, and the reference clock CK is similarly generated by a frequency error detection circuit. 7 is input. The frequency error detection circuit 7 compares the frequencies of the frame synchronization signal PFCK and the reference clock CK to generate a frequency error. The frequency error signal is converted as electric power of the disk motor 2 by the amplifier 13 and drives the disk motor 2. At this time, an offset is applied according to the output value of the frequency error detection circuit 7, and a stable control signal is sent to the desk motor 2 via the amplifier 13. That is, the frequency error detection circuit 7 and the amplifier 13
And the offset application circuit 1 which is a feature of the present invention.
0 is connected. Note that the EFM signal generated by the data slice circuit, after separating the synchronization signal,
EFM in CD processing circuit of CD processing / CD synchronization detection circuit 6
Demodulated. The CD processing circuit performs EFM demodulation, error correction, and the like, and outputs an audio signal via a digital-to-analog converter and a low-pass filter.

The offset application circuit 10 periodically takes in the output of the frequency error detection circuit 7 and, in accordance with its magnitude and direction, moves in such a direction that the frequency error disappears at such a low speed that the lock of the PLL circuit is not released. Offset is applied. The offset applying circuit 10 may be operated by software by the system controller 9 or may be constituted by hardware as shown in FIG. FIG.
3 is a circuit diagram of the offset applying circuit shown in FIG.
The offset applying circuit 10 basically includes a first counter 11, a second counter 12, and an adder 14. The output (frequency error number) from the frequency error detection circuit 7 is supplied to the amplifier 13 via the adder 14 and becomes a signal for controlling the rotation of the disk motor 2. The output from the frequency error detection circuit 7 is also input to the input terminal IN of the first counter 11. The first counter 11 has a preset terminal P to which a preset clock is input.
R and a clock terminal CK to which a count clock is input. The output of the first counter 11 is input from its output terminal OUT to a zero detection circuit 17 and is input to an AND circuit 15 via an inverter (NOT circuit) 16 together with a count clock. The output (count clock signal) of the AND circuit 15 is input to the clock terminals CK of the first and second counters 11 and 12. The MSB bit of the first counter 11 is input to the second counter 12 via the inverter 18. An offset is output from the output terminal OUT of the second counter 12 and is applied to the adder 14.

The output of the frequency error detection circuit 7 is, for example,
The first counter (up / down counter) 11 is periodically preset by a preset clock formed by X'tal. The first counter 11 counts in the direction in which the count value becomes zero with this count clock, and at the same time, the second counter (up-down counter) 12 counts with the same count clock. First counter 11
Becomes zero, the output of the first counter 11 is input to the zero detection circuit 17, which acts so as not to supply the count clock and stops counting. At this time, the counting direction of the second counter 12 is opposite to that of the first counter 11. Since the magnitude of the offset required to reduce the frequency error to zero changes according to the number of rotations, the cycle of the preset clock is short when the change in the target rotation speed of the disk motor 2 is large, and when the change is stable. Lengthen. In the embodiment shown in FIG. 3, the case where the frequency error is “3” and “−2” is described. In response to the output from the frequency error detection circuit 7, the first counter 11
"3, 2, 1, 0" and "-2, -1, 0" are counted, and the second counter 12 counts as "+1, +2, +3" and "+1, +2".

When the disk 1 is reproduced at a constant angular velocity (CAV), one pulse is sufficient for the preset clock since the target rotational speed is constant. In this case, the frequency characteristics are not affected as compared with the case where an integrator is provided in the disk motor servo loop to suppress the low frequency range, so that there is no need to hinder the design of the servo loop. Also, the cycle of the count clock affects the rate of change of the disk motor control signal, and rapid acceleration / deceleration of the disk motor 2 unlocks the PLL circuit. . By doing so, the offset applying circuit 1
The offset is applied stepwise from 0, and the frequency error can be made zero.

Next, the DVD-ROM shown in FIG. 4 will be described.
As shown in the drawing, it is basically the same as the CD-ROM reproducing apparatus of FIG. 1, but does not use the CD signal processing circuit / CD synchronization detecting circuit, and instead, the DVD signal processing circuit / DV
A D synchronization detection circuit is used. 4 also has a circuit 10 for applying an offset to the output of the frequency error detection circuit 7 in accordance with the value. The offset application circuit 10 periodically takes in the output of the frequency error detection circuit 7 and applies an offset in such a direction as to eliminate the frequency error at such a low speed that the lock of the PLL circuit is not released according to the size and direction. You can go.

[0015]

According to the present invention, the residual error generated by the disk motor control due to the frequency error at the time of variable speed reproduction can be reduced by the above configuration, and accurate reproduction speed control can be performed, so that the management of the time schedule can be easily performed. In addition, it is possible to suppress product variations.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a disk motor servo loop of a disk reproducing apparatus in variable speed reproduction according to the present invention.

FIG. 2 is a circuit diagram of an offset applying circuit in the disk reproducing semiconductor device of FIG. 1;

FIG. 3 is an operation timing chart of the offset applying circuit shown in FIG. 2;

FIG. 4 is a circuit block diagram showing a disk motor servo loop of the disk reproducing apparatus in variable speed reproduction according to the present invention.

FIG. 5 is a circuit block diagram showing a disk motor servo loop of a conventional disk playback device in variable speed playback.

[Explanation of symbols]

1 ··· disk, 2 ··· disk motor, 3 ·
..Pickup (PU), 4 ... RF amplifier,
5: slice / PLL circuit, 6: CD signal processing / CD synchronization detection circuit, 7: frequency error detection circuit,
8 ... clock generator, 9 ... system controller, 10 ... offset application circuit, 11 ...
First counter, 12... Second counter, 13
... Amplifier, 14 ... Adder, 15 ...
AND circuit, 16, 18 ... Inverter (NOT circuit), 19 ... DVD signal processing / DVD synchronization detection circuit.

Claims (3)

[Claims] 1. A frame synchronization signal detection unit for detecting a frame synchronization signal from a disk on which a signal is recorded at a constant linear velocity, a clock generation unit for generating a clock for comparing a frequency with the frame synchronization signal, Frequency error detecting means for detecting a frequency error between the frame synchronization signal and the clock; offset applying means for adding a DC value corresponding to the frequency error to the frequency error; a sum of the frequency error and the output of the offset applying means. Disk drive means for driving a disk motor with the control signal as a control signal, wherein the offset applying means periodically takes in the frequency error and applies a DC value in a stepwise manner in a direction in which the frequency error disappears. A disk motor control circuit. 2. The method according to claim 1, wherein the offset means includes a first counter for counting the number of frequency errors obtained from the frequency error detection means, and a step-by-step output of the count number obtained from the first counter. 2 and the second
2. The disk motor control circuit according to claim 1, further comprising: an adder for adding a count number obtained from said counter to the output of said frequency error detecting means in a stepwise manner. 3. A photoelectric conversion unit for optically reading data recorded on a disk on which a signal is recorded at a constant linear velocity and converting the data into an electric signal, and amplifying the electric signal supplied from the photoelectric conversion unit. An amplifier; a data slice circuit for converting an electric signal supplied from the amplifier into a binary signal; and a clock corresponding to a change in a data reproduction speed based on the binary signal supplied from the data slice circuit. A PLL circuit that generates a signal; a signal processing circuit that demodulates the EFM signal supplied from the data slice circuit in accordance with a clock signal supplied from the PLL circuit to reproduce data; and controls a rotation of the disk. A disk motor control circuit for detecting a frame synchronization signal from the disk. Synchronization signal detection means,
A clock generation unit for generating a clock for comparing the frequency with the frame synchronization signal, a frequency error detection unit for detecting a frequency error between the frame synchronization signal and the clock, and a DC value corresponding to the frequency error. An offset applying means for adding to the frequency error, and a disk motor driving means for driving a disk motor using a sum of the frequency error and the output of the offset applying means as a control signal, wherein the offset applying means periodically reduces the frequency error. A disc reproducing apparatus, wherein a DC value is gradually applied in a direction in which the frequency error is eliminated.