JPH1126461A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH1126461A JPH1126461A JP9182095A JP18209597A JPH1126461A JP H1126461 A JPH1126461 A JP H1126461A JP 9182095 A JP9182095 A JP 9182095A JP 18209597 A JP18209597 A JP 18209597A JP H1126461 A JPH1126461 A JP H1126461A
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- JP
- Japan
- Prior art keywords
- titanium nitride
- film
- copper
- insulating film
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体装置及びその
製造方法に関し、詳しくは、低抵抗で、かつ高い信頼性
を有する銅もしくは銅合金からなる配線を具備した半導
体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a low-resistance and highly reliable wiring made of copper or copper alloy and a method of manufacturing the same.
【0002】[0002]
【従来の技術】周知のように、従来、LSI(大規模集
積回路)の配線材料としては、アルミニウムまたはアル
ミニウム合金が主に使用された。しかし、アルミニウム
は融点が低く(660℃)、耐マイグレーション性に劣
るため、断線などの故障が起きやすく、LSIの高集積
化,高速化に対応するのは困難である。2. Description of the Related Art As is well known, aluminum or an aluminum alloy has been mainly used as a wiring material of an LSI (Large Scale Integrated Circuit). However, since aluminum has a low melting point (660 ° C.) and poor migration resistance, failures such as disconnection are likely to occur, and it is difficult to cope with high integration and high speed of LSI.
【0003】これに対して、銅はアルミニウムよりはる
かに融点が高く(1083℃)、電気抵抗率も低いため
(バルク値でアルミニウムの約2/3)、次世代LSI
配線材料として有力である。On the other hand, copper has a much higher melting point than aluminum (1083 ° C.) and a lower electric resistivity (about 2/3 of aluminum in bulk value), so that next-generation LSI
It is effective as a wiring material.
【0004】しかし、銅配線にはアルミニウム配線と比
較していくつかの欠点がある。その1つは、銅配線と絶
縁膜の接着性が低いという問題である。However, copper wiring has some disadvantages as compared with aluminum wiring. One of the problems is that the adhesion between the copper wiring and the insulating film is low.
【0005】この問題を解決するために、銅配線と絶縁
膜の間に接着層として異種金属,合金を挟み込む方法が
知られている。In order to solve this problem, there is known a method in which a different kind of metal or alloy is sandwiched between a copper wiring and an insulating film as an adhesive layer.
【0006】この方法を用いて銅配線を作成した例が、
「アプライド・フィジックス・レター(Applied Physic
s Letter, 63(19) (1993) pp.2703-2704)」に示されて
いる。An example of forming a copper wiring using this method is as follows.
"Applied Physic Letter
s Letter, 63 (19) (1993) pp. 2703-2704).
【0007】この方法では、絶縁膜として酸化シリコン
膜が100nm形成されたシリコン基板上に、スパッタ
法で膜厚100nmの窒化チタン膜,膜厚500nmの
銅膜,膜厚50nmの窒化チタン膜を順次形成した後、
酸化シリコン膜を300nm形成し、この酸化シリコン
膜をマスクとしてドライエッチングを行い銅配線を形成
している。ここに記載された方法では銅配線直上の窒化
チタン層はエッチングマスクである酸化シリコン膜と銅
配線との接着層,銅配線直下の窒化チタン層は基板と銅
配線との接着層として用いられている。In this method, a 100-nm-thick titanium nitride film, a 500-nm-thick copper film, and a 50-nm-thick titanium nitride film are sequentially formed on a silicon substrate on which a 100-nm-thick silicon oxide film is formed as an insulating film by sputtering. After forming
A silicon oxide film is formed to a thickness of 300 nm, and dry etching is performed using the silicon oxide film as a mask to form a copper wiring. In the method described here, the titanium nitride layer immediately above the copper wiring is used as an adhesive layer between the silicon oxide film serving as an etching mask and the copper wiring, and the titanium nitride layer immediately below the copper wiring is used as the bonding layer between the substrate and the copper wiring. I have.
【0008】しかし、一般的に銅膜と窒化チタン膜の接
着性はあまり高くないため、微細加工後や洗浄後に銅膜
と窒化チタン膜の間ではがれが発生する恐れがあり、高
い信頼性を有する銅配線を形成するのは困難である。However, since the adhesion between the copper film and the titanium nitride film is generally not so high, there is a possibility that the copper film and the titanium nitride film may be peeled off after fine processing or cleaning, and high reliability is required. It is difficult to form a copper wiring having the same.
【0009】この問題を解決するための技術の一例が特
開平5−218036 号に示してある。An example of a technique for solving this problem is disclosed in Japanese Patent Application Laid-Open No. H5-218036.
【0010】ここに記載された方法は、半導体素子が形
成された基板上に、CVD(化学的気相成長)法により
膜厚100nmのタングステン層を形成した後、膜厚5
0nmのチタン層をスパッタ法で形成し、さらにCVD法
により膜厚300nmの銅層を形成し、ドライエッチン
グ法により銅配線を形成する方法である。In the method described here, a 100-nm-thick tungsten layer is formed on a substrate on which a semiconductor element is formed by a CVD (chemical vapor deposition) method, and then a tungsten film having a thickness of 5 nm is formed.
In this method, a titanium layer having a thickness of 0 nm is formed by a sputtering method, a copper layer having a thickness of 300 nm is formed by a CVD method, and copper wiring is formed by a dry etching method.
【0011】[0011]
【発明が解決しようとする課題】しかし、銅膜とチタン
膜が直接接触する構造では、チタン原子が銅膜中に拡散
し銅膜の抵抗率が上昇する恐れがある。However, in a structure in which a copper film and a titanium film are in direct contact, titanium atoms may diffuse into the copper film and the resistivity of the copper film may increase.
【0012】本発明の目的は、上記従来方法の有する問
題を解決し、上記銅膜の抵抗率上昇を起こさずに、配線
のはがれのない高い信頼性を有する銅配線及びその製造
方法を提供することである。An object of the present invention is to solve the problems of the conventional method and to provide a highly reliable copper wiring without peeling of the wiring without causing an increase in the resistivity of the copper film, and a method of manufacturing the same. That is.
【0013】[0013]
【課題を解決するための手段】上記目的は、銅もしくは
銅合金配線の周面の少なくとも1面と絶縁膜との間に、
窒素濃度52原子%以上の窒化チタンを形成することに
より達成される。An object of the present invention is to provide a method for manufacturing a semiconductor device, comprising the steps of:
This is achieved by forming titanium nitride having a nitrogen concentration of 52 atomic% or more.
【0014】[0014]
【発明の実施の形態】以下、図面を用いて本発明の実施
例を説明する。なお、各図面は模式的に描かれており、
説明に不要な箇所は図示が省略されている。Embodiments of the present invention will be described below with reference to the drawings. In addition, each drawing is drawn schematically,
Parts unnecessary for the description are not shown.
【0015】<実施例1>図1は本発明の半導体装置の
製造工程を示す断面図である。以下順を追って説明す
る。Embodiment 1 FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to the present invention. The description will be made in the following order.
【0016】まず、図1(a)に示したように、半導体
素子(図示せず)が形成されたシリコン基板100上
に、開口部を有する膜厚500nmの酸化シリコン膜か
らなる絶縁膜200を形成し、タングステン・プラグ3
00を選択CVD法によって形成して、上記開口部を充
填した。その後、チタンのターゲットを用いたスパッタ
法により、DCパワー=4kW(1平方センチメートル
あたりのパワー密度8W),アルゴンガスに対する窒素
ガスの流量比(窒素/アルゴン流量比)=2の条件で、
膜厚50nmの第1の窒化チタン膜301を形成した
後、膜厚400nmの銅膜302,キャップ用窒化チタ
ン膜303,微細加工時のエッチングマスクとして膜厚
400nmの酸化シリコン膜からなる第2の絶縁膜20
1を形成した。First, as shown in FIG. 1A, an insulating film 200 made of a 500-nm-thick silicon oxide film having an opening is formed on a silicon substrate 100 on which a semiconductor element (not shown) is formed. Formed and tungsten plug 3
00 was formed by a selective CVD method to fill the opening. Then, by a sputtering method using a titanium target, under the conditions of DC power = 4 kW (power density per square centimeter 8 W) and a flow rate ratio of nitrogen gas to argon gas (flow rate ratio of nitrogen / argon) = 2,
After the first titanium nitride film 301 having a thickness of 50 nm is formed, a copper film 302 having a thickness of 400 nm, a titanium nitride film 303 for a cap, and a second silicon oxide film having a thickness of 400 nm are used as an etching mask for fine processing. Insulating film 20
1 was formed.
【0017】次に、フォトリソグラフィー法,ドライエ
ッチング法を用いて所望のパターンをエッチングマスク
である第2の絶縁膜201に転写し、RFプラズマエッ
チング装置を用いて塩素ガスによりドライエッチングを
行い、図1(b)に示したような所望のパターニングさ
れた銅配線を得た。上記第1の窒化チタン膜301の成
膜条件および膜厚を変えて同様に処理し、数種類の半導
体装置を作成した。Next, a desired pattern is transferred to the second insulating film 201 serving as an etching mask by using a photolithography method and a dry etching method, and is dry-etched by a chlorine gas using an RF plasma etching apparatus. A desired patterned copper wiring as shown in FIG. 1 (b) was obtained. The same processing was performed by changing the film forming conditions and the film thickness of the first titanium nitride film 301, and several types of semiconductor devices were manufactured.
【0018】このようにして形成された試料の表面を光
学顕微鏡及びSEM(走査型電子顕微鏡)で観察した。
銅配線がはがれずに残っている割合を接着性と定義する
と、図2に示したように窒素/アルゴン流量比が大き
く、DCパワーが低い条件で窒化チタン膜を形成すれ
ば、はがれのない配線が形成できた。The surface of the sample thus formed was observed with an optical microscope and an SEM (scanning electron microscope).
If the ratio of the copper wiring remaining without peeling is defined as adhesiveness, if the titanium nitride film is formed under the condition that the nitrogen / argon flow rate ratio is large and the DC power is low as shown in FIG. 2, no peeling occurs. Wiring could be formed.
【0019】このようにして形成された試料の、第1の
窒化チタン膜301の組成をオージェ電子分光法によっ
て調べた。図3は各試料の第1の窒化チタン膜301の
窒素濃度(原子%)と銅配線の接着性の関係を表す図で
ある。従来は、たとえば特開平8−97209号に記載のよう
に、バリア性を向上させるために窒素濃度が50原子%
以下の窒化チタン膜を用いていたが、図3に示したよう
に従来の窒化チタン膜を用いて銅配線を形成した場合に
は、はがれが生じる。しかしながら、第1の窒化チタン
膜301の窒素濃度を52原子%以上にすれば、はがれ
のない高性能の銅配線を得ることができる。The composition of the first titanium nitride film 301 of the sample thus formed was examined by Auger electron spectroscopy. FIG. 3 is a diagram showing the relationship between the nitrogen concentration (atomic%) of the first titanium nitride film 301 of each sample and the adhesiveness of the copper wiring. Conventionally, as described in JP-A-8-97209, for example, a nitrogen concentration of 50 atomic% is used to improve barrier properties.
Although the following titanium nitride film has been used, when a copper wiring is formed using a conventional titanium nitride film as shown in FIG. 3, peeling occurs. However, when the nitrogen concentration of the first titanium nitride film 301 is set to 52 atomic% or more, a high-performance copper wiring without peeling can be obtained.
【0020】また、このようにして形成された試料の、
銅配線の接着性と第1の窒化チタン膜301の膜厚の関
係を調べた。図4からわかるように銅配線と絶縁膜の間
に5nm以上の窒化チタン膜があれば、はがれのない銅
配線を得ることができる。Further, the sample thus formed is
The relationship between the adhesiveness of the copper wiring and the thickness of the first titanium nitride film 301 was examined. As can be seen from FIG. 4, if there is a titanium nitride film of 5 nm or more between the copper wiring and the insulating film, a copper wiring without peeling can be obtained.
【0021】また、このようにして形成された試料を、
水素雰囲気中において450℃で30分間熱処理した
後、銅配線の抵抗率を求めたところ、第1の窒化チタン
膜の窒素濃度が50原子%以上であれば、配線の抵抗率
は1.9μΩcm 以下なので、実用上問題にならない。The sample thus formed is
After heat treatment at 450 ° C. for 30 minutes in a hydrogen atmosphere, the resistivity of the copper wiring was determined. If the nitrogen concentration of the first titanium nitride film was 50 at% or more, the resistivity of the wiring was 1.9 μΩcm or less. Therefore, it is not a problem in practical use.
【0022】すなわち、本実施例で示したように、銅配
線と絶縁膜の間に5nm以上の窒化チタン膜を形成し、
この窒化チタン膜の窒素濃度が52原子%以上であれ
ば、従来と比較して、配線の抵抗率を低く抑えたまま、
はがれのない高信頼性の配線が実現できる。That is, as shown in this embodiment, a titanium nitride film having a thickness of 5 nm or more is formed between the copper wiring and the insulating film.
If the nitrogen concentration of the titanium nitride film is 52 atomic% or more, the resistivity of the wiring is kept low as compared with the related art,
Highly reliable wiring without peeling can be realized.
【0023】本実施例では、銅配線と絶縁膜の間に単層
の窒化チタンを形成したが、タングステン・プラグ30
0との接触抵抗を下げるために、この窒化チタニウムと
絶縁膜の間に、組成の異なる窒化チタンや純チタン、ま
たは他の導電膜を形成することも可能である。また上記
窒化チタンのバリア性を高めるために、窒化チタンに酸
素やシリコンなどの他元素を添加することも可能であ
る。In this embodiment, a single layer of titanium nitride is formed between the copper wiring and the insulating film.
In order to reduce the contact resistance with zero, it is possible to form titanium nitride, pure titanium, or another conductive film having a different composition between the titanium nitride and the insulating film. In order to enhance the barrier properties of the titanium nitride, other elements such as oxygen and silicon can be added to the titanium nitride.
【0024】<実施例2>図5は本発明の第2の実施例
を示す工程図である。<Embodiment 2> FIG. 5 is a process chart showing a second embodiment of the present invention.
【0025】まず、図5(a)に示したように、半導体
素子(図示せず)が形成されたシリコン基板100上
に、開口部を有する膜厚500nmの酸化シリコン膜か
らなる絶縁膜200を形成し、タングステン・プラグ3
00を選択CVD法によって形成して、上記開口部を充
填した。その後、従来のスパッタ条件である、スパッタ
パワー=8kW(1平方センチメートルあたりのパワー
密度16W),アルゴンガスに対する窒素ガスの流量比
(窒素/アルゴン流量比)=1の条件で、膜厚50nm
の第1の窒化チタン膜301を形成した後、試料をプラ
ズマ処理チャンバに搬送し、ICP(誘導結合型プラズ
マ)パワー=1kW(1平方センチメートルあたりのパ
ワー密度2W),RF(高周波)バイアス=100Vで
窒素プラズマ処理を2分間行った。First, as shown in FIG. 5A, an insulating film 200 made of a 500-nm-thick silicon oxide film having an opening is formed on a silicon substrate 100 on which a semiconductor element (not shown) is formed. Formed and tungsten plug 3
00 was formed by a selective CVD method to fill the opening. Thereafter, the film thickness is 50 nm under the conventional sputtering conditions of sputtering power = 8 kW (power density per square centimeter: 16 W), and the flow ratio of nitrogen gas to argon gas (nitrogen / argon flow ratio) = 1.
After the first titanium nitride film 301 is formed, the sample is transported to a plasma processing chamber, and ICP (inductively coupled plasma) power = 1 kW (power density per square centimeter 2 W), RF (high frequency) bias = 100 V Nitrogen plasma treatment was performed for 2 minutes.
【0026】その後、図5(b)に示したように膜厚40
0nmの銅膜302,スパッタパワー=8kW,窒素/
アルゴン流量比=1の条件でキャップ用窒化チタン膜3
03,微細加工時のエッチングマスクとして膜厚400
nmの酸化シリコン膜からなる第2の絶縁膜201を形
成した。Thereafter, as shown in FIG.
0 nm copper film 302, sputtering power = 8 kW, nitrogen /
Titanium nitride film 3 for cap under argon flow ratio = 1 condition
03, film thickness 400 as an etching mask for fine processing
A second insulating film 201 made of a silicon oxide film having a thickness of nm was formed.
【0027】次に、フォトリソグラフィー法,ドライエ
ッチング法を用いて所望のパターンをエッチングマスク
である第2の絶縁膜201に転写し、RFプラズマエッ
チング装置を用いて塩素ガスによりドライエッチングを
行い、図5(c)に示したような所望のパターニングさ
れた銅配線を得た。窒素プラズマ処理の時間を変えて同
様に処理し、数種類の半導体装置を作成した。Next, a desired pattern is transferred to the second insulating film 201 serving as an etching mask by using a photolithography method and a dry etching method, and is dry-etched by a chlorine gas using an RF plasma etching apparatus. The desired patterned copper wiring as shown in FIG. 5 (c) was obtained. The same processing was performed by changing the time of the nitrogen plasma processing, and several types of semiconductor devices were manufactured.
【0028】このようにして形成された試料の表面を光
学顕微鏡及びSEM(走査型電子顕微鏡)で観察したと
ころ、図6に示したようにプラズマ処理時間が2分以上
であれば、はがれのない高信頼性の銅配線を得ることが
できた。When the surface of the sample thus formed was observed with an optical microscope and an SEM (scanning electron microscope), it did not peel off if the plasma processing time was 2 minutes or more as shown in FIG. Highly reliable copper wiring was obtained.
【0029】すなわち、本実施例で示したように、従来
の窒化チタン膜の表面を窒素プラズマで処理すれば、従
来と比較して、はがれのない高信頼性の配線が実現でき
る。That is, as shown in this embodiment, if the surface of the conventional titanium nitride film is treated with nitrogen plasma, a highly reliable wiring without peeling can be realized as compared with the conventional case.
【0030】本実施例では、プラズマ処理用のガスとし
て純窒素を用いているが、純窒素のかわりにアンモニア
ガスなどの窒素原子を含むガスでも同様の効果が期待で
きる。さらに窒素または窒素原子を含むガスにアルゴン
ガスなどを添加し、スパッタエッチと窒素プラズマ処理
を同時に行うことも可能である。In this embodiment, pure nitrogen is used as the plasma processing gas. However, a similar effect can be expected with a gas containing nitrogen atoms such as ammonia gas instead of pure nitrogen. Further, it is also possible to add an argon gas or the like to nitrogen or a gas containing a nitrogen atom, and carry out the sputter etching and the nitrogen plasma treatment at the same time.
【0031】<実施例3>図7は本発明の第3の実施例
を示す工程図である。半導体素子(図示せず)が形成さ
れたシリコン基板100上に、開口部を有する膜厚40
0nmの絶縁膜200を形成し、絶縁膜200に設けら
れた開口部を選択CVD法により形成したタングステン
・プラグ300で充填し、開口部を有する膜厚500n
mの第2の絶縁膜201を形成した。次に開口部が設け
られた第2の絶縁膜201上にチタンのターゲットを用
いたスパッタ法により、DCパワー=4kW(1平方セ
ンチメートルあたりのパワー密度8W),アルゴンガス
に対する窒素ガスの流量比(窒素/アルゴン流量比)=2
の条件で膜厚50nmの第1の窒化チタン膜301と、
25℃で膜厚800nmの銅膜302をスパッタリング
法により順次形成した(図7(a))。<Embodiment 3> FIG. 7 is a process chart showing a third embodiment of the present invention. On a silicon substrate 100 on which a semiconductor element (not shown) is formed, a film 40 having an opening is formed.
An insulating film 200 having a thickness of 0 nm is formed, and an opening provided in the insulating film 200 is filled with a tungsten plug 300 formed by a selective CVD method.
m of the second insulating film 201 was formed. Next, a DC power = 4 kW (power density per square centimeter 8 W) and a flow rate ratio of nitrogen gas to argon gas (nitrogen) by sputtering using a titanium target on the second insulating film 201 provided with the opening. / Argon flow ratio) = 2
A first titanium nitride film 301 having a thickness of 50 nm under the following conditions:
A copper film 302 having a thickness of 800 nm was sequentially formed at 25 ° C. by a sputtering method (FIG. 7A).
【0032】次に、このウェハを真空を破らず熱処理用
チャンバに搬送し450℃で20分の熱処理を行った。
このようにして形成した試料をCMP(化学的機械研磨)
法により第2の絶縁膜201に設けた開口部以外の領域
の第1の窒化チタン膜301,銅膜302を除去するこ
とにより銅配線を形成した(図7(b))。上記第1の
窒化チタン膜301の成膜条件および膜厚を変えて同様
に処理し、数種類の半導体装置を作成した。Next, the wafer was transferred to a heat treatment chamber without breaking vacuum, and heat treated at 450 ° C. for 20 minutes.
The sample thus formed is subjected to CMP (chemical mechanical polishing).
The copper wiring was formed by removing the first titanium nitride film 301 and the copper film 302 in the region other than the opening provided in the second insulating film 201 by the method (FIG. 7B). The same processing was performed by changing the film forming conditions and the film thickness of the first titanium nitride film 301, and several types of semiconductor devices were manufactured.
【0033】このようにして形成した試料の表面および
断面を光学顕微鏡およびSEMで観察したところ、実施
例1で示した結果と同様に、窒素/アルゴン流量比が大
きく、DCパワーが低い条件で第1の窒化チタン膜30
1を形成すれば、はがれのない配線が形成できた。また
第1の窒化チタン膜301の膜厚と接着性の関連を調べ
たところ、第1の窒化チタン膜301の膜厚が5nm以
上であればはがれのない配線が形成できた。When the surface and the cross section of the sample thus formed were observed with an optical microscope and an SEM, as in the case of the result shown in Example 1, the flow rate of nitrogen / argon was large and the DC power was low. 1 titanium nitride film 30
By forming 1, a wiring without peeling could be formed. Further, when the relationship between the thickness of the first titanium nitride film 301 and the adhesiveness was examined, a wiring without peeling was formed when the thickness of the first titanium nitride film 301 was 5 nm or more.
【0034】すなわち、本実施例で示したように、銅配
線と絶縁膜の間に5nm以上の窒化チタン膜を形成し、
この窒化チタン膜の窒素/チタン組成比が52原子%以
上であれば、従来と比較して、はがれのない高信頼性の
配線が実現できる。That is, as shown in this embodiment, a titanium nitride film having a thickness of 5 nm or more is formed between the copper wiring and the insulating film.
If the nitrogen / titanium composition ratio of the titanium nitride film is at least 52 atomic%, a highly reliable wiring with no peeling can be realized as compared with the related art.
【0035】また本実施例では、銅配線と絶縁膜の間に
窒化チタンを1層形成したが、実施例1と同様に、この
窒化チタニウムと絶縁膜の間に、組成の異なる窒化チタ
ンや純チタン、または他の導電膜を形成することも可能
である。また上記窒化チタンのバリア性を高めるため
に、窒化チタンに酸素やシリコンなどの他元素を添加す
ることも可能である。In this embodiment, one layer of titanium nitride is formed between the copper wiring and the insulating film. However, similarly to the first embodiment, between the titanium nitride and the insulating film, titanium nitride having a different composition or pure titanium nitride is formed. It is also possible to form titanium or another conductive film. In order to enhance the barrier properties of the titanium nitride, other elements such as oxygen and silicon can be added to the titanium nitride.
【0036】[0036]
【発明の効果】本発明によれば、銅配線の抵抗率を上昇
させることなく、はがれのない高信頼性の銅配線を形成
することが可能となる。According to the present invention, it is possible to form a highly reliable copper wiring without peeling without increasing the resistivity of the copper wiring.
【図1】本発明の実施例1における半導体素子の製造工
程の要部断面図。FIG. 1 is a cross-sectional view of a main part of a manufacturing step of a semiconductor device in a first embodiment of the present invention.
【図2】銅配線の接着性のDCパワー,窒素/アルゴン
流量比依存性を示す図。FIG. 2 is a diagram showing the DC power and the nitrogen / argon flow rate ratio dependency of the adhesiveness of a copper wiring.
【図3】銅配線の接着性の窒化チタン中の窒素濃度依存
性を示す図。FIG. 3 is a graph showing the dependency of the adhesiveness of copper wiring on the nitrogen concentration in titanium nitride.
【図4】銅配線の接着性の第1の窒化チタン膜厚依存性
を示す図。FIG. 4 is a graph showing the dependence of the adhesiveness of a copper wiring on the thickness of a first titanium nitride film.
【図5】本発明の実施例2における半導体素子の製造工
程の要部断面図。FIG. 5 is a cross-sectional view of a principal part in a manufacturing step of the semiconductor element in the second embodiment of the present invention.
【図6】銅配線の接着性の窒素プラズマ曝露時間依存性
を示す図。FIG. 6 is a diagram showing the dependency of the adhesiveness of a copper wiring on exposure time to nitrogen plasma.
【図7】本発明の実施例3における半導体素子の製造工
程の要部断面図。FIG. 7 is a cross-sectional view of a main part of a manufacturing step of a semiconductor device in a third embodiment of the present invention.
100…半導体素子の形成された基体、200…第1の
絶縁膜、201…第2の絶縁膜、300…導電性物質で
埋め込まれた接続孔、301…第1の窒化チタン膜、3
02…銅膜、303…キャップ用窒化チタン膜。Reference numeral 100: a substrate on which a semiconductor element is formed; 200, a first insulating film; 201, a second insulating film; 300, a connection hole buried with a conductive substance; 301, a first titanium nitride film;
02: copper film, 303: titanium nitride film for cap.
Claims (5)
絶縁膜上もしくは上記絶縁膜に取り囲まれるように形成
された銅もしくは銅合金配線と、上記銅もしくは銅合金
配線の周面の少なくとも1面と上記絶縁膜との間に、上
記銅もしくは銅合金配線に接する領域の窒素濃度が52
原子%以上である窒化チタンを有することを特徴とする
半導体装置。An insulating film formed on a semiconductor substrate, a copper or copper alloy wiring formed on or surrounded by the insulating film, and at least a peripheral surface of the copper or copper alloy wiring. The nitrogen concentration in the region in contact with the copper or copper alloy wiring between one surface and the insulating film is 52%.
A semiconductor device comprising titanium nitride of at least atomic%.
原子%以上である領域の厚みが、5nm以上であること
を特徴とする請求項1に記載の半導体装置。2. The titanium nitride according to claim 1, wherein the nitrogen concentration is 52.
2. The semiconductor device according to claim 1, wherein the thickness of the region that is at least atomic% is at least 5 nm.
上記絶縁膜上もしくは上記絶縁膜に取り囲まれるように
銅もしくは銅合金配線を形成する工程と、上記銅もしく
は銅合金配線の周面の少なくとも1面と上記絶縁膜との
間に窒化チタンを形成する工程を少なくとも含み、上記
窒化チタンにおいて上記銅もしくは銅合金に接する領域
の窒素濃度を52原子%以上とすることを特徴とする半
導体装置の製造方法。A step of forming an insulating film on the semiconductor substrate;
Forming a copper or copper alloy wiring on the insulating film or being surrounded by the insulating film; and forming titanium nitride between at least one peripheral surface of the copper or copper alloy wiring and the insulating film. A method for manufacturing a semiconductor device, comprising at least a step, wherein a nitrogen concentration in a region of the titanium nitride in contact with the copper or copper alloy is set to 52 atomic% or more.
原子%以上である領域の厚みが、5nm以上であること
を特徴とする請求項3に記載の半導体装置の製造方法。4. The titanium nitride according to claim 1, wherein the nitrogen concentration is 52.
4. The method according to claim 3, wherein the thickness of the region that is at least atomic% is at least 5 nm.
上記絶縁膜上もしくは上記絶縁膜に取り囲まれるように
銅もしくは銅合金配線を形成する工程と、上記銅もしく
は銅合金配線の周面の少なくとも1面と上記絶縁膜との
間に窒化チタンを形成する工程を少なくとも含む半導体
装置の製造方法において、上記銅もしくは銅合金配線の
形成に先立ち、上記窒化チタン形成後に上記窒化チタン
の表面を窒素原子または窒素イオンを含むプラズマに曝
すことを特徴とする半導体装置の製造方法。5. A step of forming an insulating film on a semiconductor substrate;
Forming a copper or copper alloy wiring on the insulating film or being surrounded by the insulating film; and forming titanium nitride between at least one peripheral surface of the copper or copper alloy wiring and the insulating film. In a method of manufacturing a semiconductor device including at least a step, prior to the formation of the copper or copper alloy wiring, the surface of the titanium nitride is exposed to a plasma containing nitrogen atoms or nitrogen ions after the formation of the titanium nitride. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9182095A JPH1126461A (en) | 1997-07-08 | 1997-07-08 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9182095A JPH1126461A (en) | 1997-07-08 | 1997-07-08 | Semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1126461A true JPH1126461A (en) | 1999-01-29 |
Family
ID=16112270
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9182095A Pending JPH1126461A (en) | 1997-07-08 | 1997-07-08 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1126461A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271596B1 (en) * | 1999-01-12 | 2001-08-07 | Agere Systems Guardian Corp. | Damascene capacitors for integrated circuits |
| WO2024095887A1 (en) * | 2022-11-04 | 2024-05-10 | 東京エレクトロン株式会社 | Method for manufacturing semiconductor device, manufacturing device for semiconductor device, and semiconductor device |
-
1997
- 1997-07-08 JP JP9182095A patent/JPH1126461A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271596B1 (en) * | 1999-01-12 | 2001-08-07 | Agere Systems Guardian Corp. | Damascene capacitors for integrated circuits |
| WO2024095887A1 (en) * | 2022-11-04 | 2024-05-10 | 東京エレクトロン株式会社 | Method for manufacturing semiconductor device, manufacturing device for semiconductor device, and semiconductor device |
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