JPH1126471A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a structure in which a first semiconductor layer and a second semiconductor layer are connected to each other by a selective epitaxial growth method without breaking a wafer and observing a cross section. The connection between one semiconductor layer and the second semiconductor layer is confirmed. SOLUTION: A base layer 10 of a bipolar transistor made of single crystal silicon and ap ⁺ type polysilicon film 11 are connected to each other by a selective epitaxial growth method. The p ⁺ -type polysilicon film 11 is connected to the p ⁺ -type base electrode polysilicon film 7 and further to the p ⁺ -type polysilicon film 12, and the p ⁺ -type polysilicon film 12 has an opening 103.
It is exposed inside. On the other hand, the base layer 10 is exposed in the opening 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method using a selective epitaxial growth method.

[0002]

2. Description of the Related Art As a conventional technique of this kind, a bipolar transistor in which an intrinsic base is formed by a selective epitaxial growth method will be described. The prior art base forming method shown in FIG. 12 is based on IEEE Transactions.
on Electron Devices 1994
August issue, pages 1373-1378 (title: A supers
elf-aligned selectively grown SiGe base (SSSB) bip
olar transistor tabricated by cold-wall type UHV / C
VD technology). No. 5 is the one announced by the present inventors.

On a p ^- type silicon substrate (not shown), n
^{A +} type buried layer (not shown) is formed, and n
^A collector layer 3 composed of a-type silicon epitaxial layer is formed. Collector layer 3 is separated by a LOCOS oxide film (not shown) for element isolation, and becomes a collector region of a bipolar transistor. A channel stopper p ⁺ -type buried layer (not shown) is formed in a p ^-- type silicon substrate below the LOCOS oxide film separating adjacent transistors from each other. In order to lower the resistance of the collector region, an n ⁺ -type collector lead-out region (not shown) is formed adjacent to the n ⁺ -type buried layer. Thus, a silicon substrate is formed.

The surface of the silicon substrate is covered with a silicon oxide film 6. The silicon oxide film 6 has an opening 101 for exposing a part of the collector layer 3 and for forming a base.
And an opening (not shown) for exposing the collector lead-out region. The silicon oxide film 6 has p ⁺⁺
The polysilicon film 7 for the mold base electrode is selectively formed. The polysilicon film 7 for the p ⁺⁺ type base electrode has an opening 10
1 has a structure protruding in the horizontal direction from the end to the inside of the opening. The lower surface of the protruding portion of the p ⁺⁺ -type base electrode polysilicon film 7 is exposed and is not covered with anything. However, the side and top surfaces of the p ⁺⁺ -type base electrode polysilicon film 7 are covered with the silicon nitride film 9. In addition, a polysilicon film for a collector electrode (not shown) is formed on the collector lead region. This state is shown in FIG.

Here, an intrinsic base is formed on the above-mentioned eave-shaped structure by a selective epitaxial growth method. The formation conditions will be described later in the section of “Embodiments of the Invention”. By this selective epitaxial growth,
Base layer 10 made of flat p-type single-crystal silicon film on the collector layer 3 of the eaves-shaped opening 101 is formed on the lower surface of the exposed p ⁺⁺ type base electrode polysilicon film 7 at the same time, p-type A polysilicon film 11 is formed. This state is shown in FIG.

Further, selective epitaxial growth is continued. That is, the thicknesses of the base layer 10 and the p-type polysilicon film 11 increase, and the growth continues until the two are connected. These connections are grown slightly thicker to allow for room. As a result, the thickness of the base layer 10 in the region connected to the p-type polysilicon film 11 is smaller than that in the central region. This state is shown in FIG.
[D], and the base layer 10 made of a p-type single crystal silicon film can be used as an intrinsic base.

At this time, since the connection state between the base layer 10 and the p-type polysilicon film 11 cannot be directly confirmed, it is necessary to confirm the cross-sectional shape. That is, the transistor portion is cleaved, and a selective epitaxial growth state is observed with a scanning electron microscope (SEM). The wafer cleaved for observation is, of course, discarded. Observation of the cleavage cross-section by SEM at this stage guarantees the state of the selective epitaxial growth of another uncleaved wafer within the range of growth variation between wafers. Therefore, whether or not the base layer 10 is connected to the p ^++- type base electrode polysilicon film 7 via the p-type polysilicon film 11 in the uncleaved wafer cannot be known until the transistor is completed.

[0008]

The first problem in the prior art is as follows.
The problem is that it is not known whether the epitaxially grown intrinsic base is connected to the base electrode polysilicon until the final stage in the transistor manufacturing process. The reason is that when using a conventionally known method for manufacturing a transistor, immediately after a base is formed by an epitaxial growth method, a needle directly connected to a measuring instrument can be brought into contact with a wafer to make electrical measurement impossible. It is in.

The second problem is that immediately after the base is formed by the epitaxial growth method, in order to confirm the connection between the base and the polysilicon for the base electrode, it is necessary to cut the wafer and observe the cross section. The reason is the first
This is the same as the reason for the problem.

[0010]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, the present invention has the following two objects. . Eliminating the need to observe the cross section by breaking the wafer suppresses the cost increase due to the breaking. . Since it is not known whether the base is connected to the polysilicon for the base electrode until immediately before the transistor is completed, it is possible to avoid noticing a connection failure until the stage at which measurement can be performed.

[0011]

A semiconductor device according to the present invention has a structure in which a first semiconductor layer and a second semiconductor layer are connected to each other by a selective epitaxial growth method. A first probe pad made of a conductive layer connected to a semiconductor layer or made of the first semiconductor layer itself, and a conductive layer made of the conductive layer connected to the second semiconductor layer or the second semiconductor layer And a second probe pad made of the same.

A probe needle is brought into contact with each of the first probe pad and the second probe pad to check continuity. If there is continuity, the first semiconductor layer and the second semiconductor layer are connected. If there is no continuity, the first semiconductor layer and the second semiconductor layer are not connected. Thereby, it is possible to know whether or not the first semiconductor layer and the second semiconductor layer are connected without observing the cross section by breaking the wafer.

[0013] In addition, before and after the selective epitaxial growth method, a surface on which the first semiconductor layer is grown by the selective epitaxial growth method and a surface on which the second semiconductor layer is grown by the selective epitaxial growth method are subjected. May be provided with a plurality of structures having different intervals.

A probe needle is brought into contact with each of the first probe pad and the second probe pad to check continuity. It is assumed that a result is obtained in which there is conduction in a structure having a certain distance or more, and no conduction exists in a structure having a certain distance or less. Thereby, it is possible to know how much the first semiconductor layer and the second semiconductor layer have grown by the selective epitaxial growth method.

More specifically, the semiconductor device according to the present invention has a structure in which a base of a bipolar transistor made of single crystal silicon and a base electrode made of polysilicon are connected to each other by a selective epitaxial growth method. A first probe pad formed of the base itself, and a second probe pad formed by extending the base electrode on an insulating film.

A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device according to the present invention, and includes the following steps. . Forming a silicon oxide film on the LOCOS oxide film and the collector layer formed on the single crystal silicon substrate; . Forming a polysilicon film on the silicon oxide film; . Forming a silicon nitride film on the polysilicon film; . Forming a first opening in a part of the silicon nitride film on the collector layer, and forming a second opening in a part of the silicon nitride film on the LOCOS oxide film; . Removing the polysilicon film and the silicon oxide film under the first opening until the collector layer is exposed. . Using a selective epitaxial growth method for the polysilicon film exposed in the first and second openings and the collector layer exposed in the first opening, growing polysilicon in the polysilicon film And forming single-crystal silicon in the collector layer to form the first probe pad in the first opening and to form the second probe pad in the second opening. Process.

For comparison, steps of a conventional method for manufacturing a semiconductor device are listed. . Forming a silicon oxide film on the LOCOS oxide film and the collector layer formed on the single crystal silicon substrate; . Forming a polysilicon film on the silicon oxide film; . Forming a silicon nitride film on the polysilicon film; . Forming a first opening in a part of the silicon nitride film on the collector layer; . Removing the polysilicon film and the silicon oxide film under the first opening until the collector layer is exposed. . Using selective epitaxial growth for the polysilicon film exposed in the first opening and the collector layer, growing polysilicon in the polysilicon film and growing single crystal silicon in the collector layer Process.

As described above, the method of manufacturing a semiconductor device according to the present invention has the same number of steps as the conventional method. The reason for this is that the second opening in the present invention is formed by a process. In the present invention, the polysilicon of the second opening is formed at the same time as the first opening. In this case, the polysilicon is grown simultaneously with the polysilicon in the first opening.

In other words, in the semiconductor device and the method of manufacturing the same according to the present invention, an opening for measurement is formed in the polysilicon film used as the base electrode. In addition, the number of steps is not particularly increased. When the present invention is used, when checking whether or not the epitaxial base is connected to the electrode, it is not necessary to check by breaking the wafer.

[0020]

1 and 2 show a first embodiment of a semiconductor device according to the present invention. FIG. 1 is a longitudinal sectional view after a base is formed by a selective epitaxial growth method, and FIG. It is a longitudinal section before forming a base by selective epitaxial growth method.

An n ⁺ -type buried layer 2 a and a p ⁺ -type buried layer 2 for channel stopper are formed on the surface of the p ⁻ -type silicon substrate 1.
b is formed. Above them is a collector layer 3 made of an n ^- type silicon epitaxial layer. The collector layer 3 is separated into islands by the LOCOS oxide film 4. n
^{The +} -type collector lead-out region 5 is a collector region in which a base and an emitter are not formed in the future, and is heavily doped with impurities. A silicon oxide film 6 is further formed on the LOCOS oxide film 4 and the like. The silicon oxide film 6 has the following three types of openings.

The first opening 101 is formed right above the collector layer 3. An intrinsic base is formed in the opening 101. The second opening 102 is formed directly above the n ⁺ -type collector lead-out region 5. A collector electrode will be formed on the opening 102 in the future. The third opening 103 is a feature of the present invention, and is formed on the LOCOS oxide film 4.
Moreover, the shape has a submicron width (for example, 0.5 μm).
μm), and a plurality of them are formed in a direction parallel to the paper surface. The plurality of openings are collectively referred to as an opening 103.

On this silicon oxide film 6, there is a polysilicon film 7 for a p ⁺⁺ type base electrode. The polysilicon film 7 for the p ⁺⁺ -type base electrode protrudes into the opening 101 and has an eaves shape. Also, p
^{The ++} type base electrode polysilicon film 7 is buried.
On the opening 102, there is the polysilicon film 8 for an n ⁺⁺ type collector electrode. Then, the polysilicon film 7 for the p ⁺⁺ type base electrode and the polysilicon film 8 for the n ⁺⁺ type collector electrode
Is a silicon nitride film except for the lower surface of the eaves-shaped p ⁺⁺ type base electrode polysilicon film 7 protruding inside the opening 101 and the surface of the p ⁺⁺ type base electrode polysilicon film 7 above the opening 103. 9 covered. This state is shown in FIG.
It is.

Next, crystal growth is performed by the selective epitaxial growth method. At this time, the base layer 10 made of p-type single crystal silicon is formed on the collector layer 3 in the opening 101, and the p ⁺ -type base electrode polysilicon film 7 protruding into the opening 101 is formed with p-type polysilicon. Each of the films 11 is formed. The crystal is grown for as long as it seems that both are connected. At the same time, the opening 1
A p-type polysilicon film 12 is formed on the base electrode polysilicon film 03. This state is shown in FIG.

At this stage, that is, in the state shown in FIG. 1, it is confirmed whether or not the selectively formed base layer 10 is connected to the p ⁺⁺ type base electrode polysilicon film 7 via the p type polysilicon film 11. I do. That is, a region large enough to be probed as the opening 101, for example, 80 μm × 80 μm
Size. Similarly, the longitudinal dimension of the opening 103 is also about 80 μm, and several tens of submicron-width grooves are arranged (for example, groove width = 0.5 μm, groove interval =
If there are 80 openings at 0.5 μm), the area of the opening 103 is also about 80 μm × 80 μm, and the probe can be directly probed here as well. That is, conduction between the base layer 10 on the opening 101 and the p-type polysilicon film 12 on the opening 103 can be easily confirmed. In addition, the pattern creation for this check can be performed without adding any process to the process for fabricating a transistor normally used inside a circuit. By using this check pattern, the growth thickness of the base layer 10 is reduced, and the p-type polysilicon film 11 and the base layer 10 grown on the lower surface of the p ⁺⁺ type base electrode polysilicon film 7 are formed.
Can be immediately determined by the above-described electrical measurement.

Next, steps for manufacturing the state shown in FIG. 1 used for describing the first embodiment of the present invention will be described with reference to FIGS.

Referring first to FIG. Resistivity 10-2
P ^- type silicon substrate 1 with 0Ω · cm (100) plane orientation
The entire surface is oxidized to a thickness of 6000 angstroms, and a photoresist is patterned on the oxide film by a normal lithography process.
The O ₂ film is selectively etched with an HF-based etchant to remove the SiO ₂ film in a region where there is no photoresist, and then remove the photoresist. In order to reduce damage caused by ion implantation in the next step and to form a pattern for alignment in the subsequent lithography step, the SiO ₂ patterned p
^The -type silicon substrate 1 is oxidized by about 500 angstroms. Next, As ions are implanted to selectively form the n ⁺ buried layer 2a only in the region where the above-mentioned SiO ₂ film of about 6000 Å has been removed. An example of ion implantation conditions is 70 keV, 5 × 10 ¹⁵ cm ⁻² , and heat treatment after implantation is performed at 1100 ° C. for 3 hours to remove arsenic implanted to remove damage during ion implantation and reduce collector resistance. Spread. And the surface SiO
_{The two} films are entirely removed with an HE-based etchant. In this step, the same n ⁺ -type buried layer 2a can be formed by diffusing from a coating film containing a high concentration of arsenic by a heat treatment.
May be used. Next, a channel stopper p ⁺ type buried layer 2b is formed so that the p ⁻ type silicon substrate 1 on the lower surface of the LOCOS oxide film 4 formed for element isolation does not form an inversion layer. As an example of the forming conditions,
After the surface is oxidized by about 400 angstroms, boron is ion-implanted in a lithography step by using the photoresist as a mask while leaving the photoresist in an undesired region. As an example of the injection condition, 110 keV and 1 × 10
¹⁴ cm ^-2 and is as the heat treatment is one hour in 1000 ° C. nitrogen atmosphere. Next, after removing the entire surface of the oxide film with an HF-based etchant, a collector layer 3 made of an n ⁻ -type silicon epitaxial layer is grown. SiH ₄ or Si ₂ H ₂ Cl ₂ is used as a source gas, and the growth temperature is 1000 ° C. to 1100 ° C. PH ₃ is used as a doping gas. Thus, 1 × 10 ¹⁶ c
The thickness of the concentration region of m ⁻³ or less is 0.7 μm, and the average concentration from the surface to the transition region from the buried layer is about 1
An epitaxial layer of × 10 ¹⁶ cm ^-3 is obtained. Next, a 500 Å SiO ₂ film is formed on the surface,
A silicon nitride film is deposited to a thickness of about 1000 angstroms by the PCVD method. As a condition, a gas reaction of SiH ₂ Cl ₂ + NH ₃ at 700 to 900 ° C. is used. Next, patterning is performed by a lithography process, and using this resist as a mask material, the silicon nitride film is removed by dry etching. If dry etching is terminated when about 100 to 200 Å of the surface of the SiO ₂ film of about 500 Å below the silicon nitride film is removed, the silicon nitride film can be completely removed without damaging the base. The photoresist is removed. The LOCOS oxide film 4 is formed by performing selective oxidation using the silicon nitride film patterned in advance as a mask material. As an example of conditions for forming the LOCOS oxide film 4, an oxide film of about 8000 angstroms is formed in steam at 1000 ° C. for 4 hours. Next, the silicon nitride film used as a mask material at the time of oxidation is heated (about 130 ° C.) to phosphoric acid H ₃ PO _4.
Remove it completely by putting it inside. Next, normal LPCV
A silicon oxide film 6 is deposited on the surface by the D method. Its thickness is suitably about 600 Å to 2000 Å. Here, it was set to 1100 angstroms. This state is shown in FIG.

Next, referring to FIG. 4, the planar positional relationship of each part of the transistor will be described. End 4 ′ of Locos oxide film 4
There is. In addition, the position of patterning by photolithography when an opening is formed in the future is shown. That is, the opening 102 for the collector contact
And the opening 103a for the base / slit contact are opened by the same photolithography process. The opening 101b for the epitaxial base and the opening 103b for the base contact are formed by the same photolithography process. In the following description, a cross-sectional view of AA ′ including an opening 103a for the base / slit contact (FIG.
[A], FIG. 6 [a], FIG. 7 [a]) and a cross-sectional view of BB ′ not including the base / slit contact opening 103b (FIG. 5 [b], FIG. 6 [b], FIG. 7) [B]).

Next, reference is made to FIGS. 5A and 5B. An opening 102 for a collector contact and an opening 103a for a base slit contact are formed by ordinary photolithography and dry etching.
FIG. 5A is a vertical sectional view taken along line AA ′ of FIG.
[B] is a vertical sectional view taken along the line BB 'in FIG. During the dry etching of the silicon oxide film 6, since the silicon is not etched much, the opening 1 for the collector contact is formed.
In 02, only the silicon oxide film 6 can be removed.
On the other hand, in the opening 103a for the base / slit contact, the LOCOS oxide film 4 is also shaved. It is desirable that the shaved depth is not so large. The reason is that phosphorus is ion-implanted in a state where the photoresist is attached. The implantation depth is set to an acceleration energy that penetrates through the LOCOS oxide film 4 in the region of the base / slit contact opening 103a and does not allow phosphorus to be implanted into the p ⁻ type silicon substrate 1. The dose is as large as possible within the range where crystal defects can be removed by annealing. An example of the implantation conditions taking these into consideration is 70 keV and 5 × 10 ¹⁵ cm ⁻² . Next, after removing the photoresist, heat treatment is performed at 1000 ° C. for 30 minutes to recover crystal defects caused by ion implantation. The collector extraction region 5 was formed by the ion implantation and the heat treatment.

Next, please refer to FIG. 6A and FIG. 6B. FIG. 6A is a longitudinal sectional view taken along the line AA ′ of FIG. 4 in a state in which the p ⁺⁺ -type base electrode polysilicon film 7 and the n ⁺⁺ -type collector electrode polysilicon film 8 are formed.
FIG. 6B is a vertical sectional view taken along line BB ′ of FIG. Following FIG. 5, an undoped polysilicon film is deposited by a normal LPCVD method. The film thickness is the base thickness in FIG.
1 of the slit width of the opening 103a for the slit contact
/ 2 or more. For example, one of the openings 103a for the base / slit contact is 0.5 μm × 8
0 μm, and it is assumed that 80 of these are arranged at intervals of 0.5 μm. At this time, the thickness of the non-added polysilicon film needs to be 0.25 μm or 2500 Å or more. Here, the description is continued on the assumption that the film thickness is 3000 Å. Next, a region to be left as the p ⁺⁺ type base electrode polysilicon film 7 is opened by ordinary photolithography, and
The photoresist is removed by ion implantation under the conditions of keV and 5 × 10 ¹⁵ cm ⁻² . Further, only the region left as the polysilicon film 8 for the n ⁺⁺ -type collector electrode is opened by photolithography again, and phosphorus is applied thereto at 50 keV and 5 ×.
The photoresist is removed by ion implantation under the condition of 10 ¹⁵ cm ^-2 . The implanted impurities are activated by a heat treatment (for example, 900 ° C. and 30 minutes). Further, a polysilicon film 7 for a p ⁺⁺ type base electrode and a polysilicon film 8 for an n ⁺⁺ type collector electrode were formed by a combination of photolithography and dry etching.

Next, please refer to FIG. 7A and FIG. 7B. Next, the opening 101b for the epitaxial base and the opening 103b for the base contact in FIG. 4 are patterned by photolithography, and the insulating film and the polysilicon are dry-etched. This state is shown in FIG. 7A (cross section taken along the line AA ′ in FIG. 4) and FIG.
[B] (cross section taken along the line BB 'in FIG. 4). Subsequently, a silicon nitride film 9 is deposited by the LPCVD method, and the openings 101b and 103 are etched back by dry etching.
The side wall of the silicon nitride film 9 is formed on the side surface b. Further H
The silicon oxide film 6 in the opening 101b is removed using an F-based etchant, exposing the collector layer 3. Thus, the structure of FIG. 1 was formed.

Next, a second embodiment of the present invention will be described with reference to the drawings. In the second embodiment, the number of steps for creation is slightly increased as compared with the check pattern described in the first embodiment. However, it has a feature that it can be checked whether the thickness of the base layer 10 is within a desired range.

FIGS. 8 and 9 are longitudinal sectional views of a check pattern according to a second embodiment of the present invention. The difference between the present embodiment and the first embodiment is that the silicon oxide films 6a and 6b present between the collector layer 3 and the p ⁺⁺ type base electrode polysilicon film 7 have different thicknesses. It is that you are. Here, it is assumed that the silicon oxide film 6b is thicker than the silicon oxide film 6a. Formation of an intrinsic base layer in a bipolar transistor is the most important step in determining characteristics. In other words, the "impurity concentration" in the base and its "thickness"
Are the electrical characteristics such as hFE (current amplification factor), BVCEO (base open collector-emitter breakdown voltage), BVCBO (collector-base breakdown voltage), BVEBO (emitter-base breakdown voltage), and fT (cut-off frequency). Have a big impact. Therefore, in this embodiment, in the region where the silicon oxide film is thin (that is, 6a), the intrinsic base layer 1 is formed.
0a is connected to the base electrode polysilicon film 7,
In a region where the silicon oxide film thickness is large (that is, 6b), if the intrinsic base layer 10b is not connected to the p ⁺⁺ type base electrode polysilicon film 7, the thickness of the intrinsic base epitaxial layer is It can be confirmed that is within a certain range.

Referring now to FIG. The resistivity is 1
An n ⁺ -type buried layer 2 a and a channel stopper p ⁺ are formed on a part of the surface of the p ⁻ -type silicon substrate 1 of 0 to 15 Ωcm.
The mold buried layer 2b is formed by impurity diffusion from the surface. On the surfaces of the p ^- silicon substrate 1, the n ⁺ -type buried layer 2a and the channel stopper p ⁺ -type buried layer 2b, there is a collector layer 3 made of an n ^-- type silicon epitaxial layer formed by an epitaxial growth method. The transistors are electrically isolated by the collector layer 3 being separated in an island shape by the LOCOS oxide film 4. A portion of the collector layer 3 surrounded by the LOCOS oxide film 4 where a collector electrode is to be formed in the future has an n ⁺ -type collector lead-out region 5 to which impurities are added at a high concentration. A silicon oxide film 6 is provided on the collector layer 3, the LOCOS oxide film 4, and the collector extraction region 5. Four openings are formed in the silicon oxide film 6. The opening 102 formed on the collector lead-out region 5 and the opening 1 formed on the LOCOS oxide film 4
03 is the same as in the first embodiment. In the second embodiment, two types of openings 101 and 104 are further provided on the collector layer 3, and the thicknesses of the silicon oxide films 6a and 6b of the openings 101 and 104 are different. (Here, the film thickness is 6
It is described that a is thicker than 6b. Except for the vicinity of the opening 102 on the collector lead-out region 5, the p ⁺⁺ type base electrode polysilicon film 7 exists on the silicon oxide films 6a and 6b. In particular, p at openings 101 and 104
^++- type base electrode polysilicon film 7 has openings 101 and 10
The point that protrudes into the inside of 4 and has an eaves shape is
This is the same as the first embodiment. In the opening 102,
In contact with n ⁺ type collector lead-out region 5, there is an n ^{+ +} type collector electrode polysilicon film 8. And the opening 10
Except in 1,104, the surface of the collector layer 3, silicon oxide film 6a, 6b side of the p ⁺⁺ type base electrode polysilicon film 7 on the lower surface and the aperture 103 of the p ⁺⁺ type base electrode polysilicon film 7 The entire surface is covered with the silicon nitride film 9. This state is shown in FIG.

Next, selective epitaxial growth is performed on this structure. Selective means that nothing is deposited on a silicon oxide film or silicon nitride film, but a crystal grows on a crystal (that is, a single crystal grows on a single crystal and a polycrystal grows on a polycrystal). It is. Here, the single crystal growth rate on the collector layer 3 in the eaves-shaped openings 101 and 104 and the polycrystal growth rate on the lower surface of the p ⁺⁺ type base electrode polysilicon film 7 are generally different. This growth rate ratio is determined by growth conditions (raw material gas, growth pressure, temperature, etc.) and the type of crystal to be grown. Here, as in the first embodiment, it is assumed that a silicon crystal is grown using a cold wall type UHV / CVD apparatus at a growth temperature of 605 ° C. and disilane (Si ₂ H ₆ ) as a source gas. For selective growth under these conditions,
The above-mentioned growth rate ratio between the single crystal and the polycrystal is almost “1” (actually, the growth rate of the polycrystal is slightly lower than that of the single crystal). Single crystal growth rate / polycrystal growth rate = about 6 /
The following description is recommended as 5. If the thickness of the base layer formed by the epitaxial growth method varies greatly, the variation in the characteristics of the transistor also increases with the variation. Here, it is assumed that the thickness of the base layer is in a range between 500 angstroms and 600 angstroms. When the above-described growth rate ratio of 6: 5 is used, while the base layer 10a made of a silicon epitaxial layer grows on the collector layer 3 by 500 angstroms, the lower surface of the p ⁺⁺ type base electrode polysilicon film 7 is p-type. Type polysilicon film 11a grows to about 417 angstroms. Therefore, the silicon oxide film 6a
Is less than about 917 angstroms, base layer 10a is connected to p-type polysilicon film 11a.
Similarly, while the base layer 10b made of a silicon epitaxial layer grows on the collector layer 3 by 600 angstroms, the p-type polysilicon film 11b is deposited on the lower surface of the p ⁺⁺ type base electrode polysilicon film 7 by 500 angstroms. I do. Therefore, when the silicon oxide film 6b has a thickness of 600 Å or more, it is connected to the p-type polysilicon film 11b. That is, in the second embodiment, the silicon oxide film 6a in the opening 101 is 917 Å, and the silicon oxide film 6 in the opening 104 is 917 Å.
By setting b to 1100 angstroms,.
When a needle for measurement is brought into contact with the openings 101 and 103, conduction is confirmed. On the other hand, when there is no conduction when the needle is brought into contact with the openings 104 and 103, the thickness of the epitaxial layer is between 500 angstroms and 600 angstroms. Can be determined. . Between the openings 101 and 103 and the opening 10
If continuity is confirmed in both of the regions 4 and 103, it can be understood that the variation in the thickness of the epitaxial layer is larger than 600 Å in the larger one. . If neither the openings 101 and 103 nor the openings 104 and 103 are conductive, it is determined that the thickness of the epitaxial layer is smaller than 500 angstroms.

Next, a third embodiment will be described. Figures 10 and 11
Please refer to. In the present embodiment, the openings 101 and 104
However, it does not have an eaves structure. However, as is clear from FIG. 10, the connection with the electrode changes according to the difference in the thickness of the epitaxial layer as in the second embodiment.

Although the present invention has been described with reference to the case where silicon is epitaxially grown, other materials such as SiG
Needless to say, the present invention can be applied to the case where e is epitaxially grown.

[0038]

According to the semiconductor device of the present invention, a first probe pad connected to the first semiconductor layer and a second probe pad connected to the second semiconductor layer are provided. So, by contacting the probe needles with the first probe pad and the second probe pad, respectively, and confirming the continuity, without breaking the wafer and observing the cross section, the first semiconductor layer and The connection with the second semiconductor layer can be confirmed.

In addition, a plurality of planes on which the first semiconductor layer is grown by the selective epitaxial growth method and the second semiconductor layer is grown by the selective epitaxial growth method have different distances before the selective epitaxial growth method is applied. In the case of having the structure of (1), the degree of growth by the selective epitaxial growth method is confirmed by contacting the probe needle with the first probe pad and the second probe pad of each structure to confirm conduction. Can be measured.

According to the method of manufacturing a semiconductor device according to the present invention, the second opening is formed simultaneously with the first opening, and the polysilicon in the second opening is grown simultaneously with the polysilicon in the first opening. Thus, the semiconductor device according to the present invention can be manufactured without increasing the number of steps. According to the method for manufacturing a semiconductor device of the present invention, the second opening is formed on the LOCOS oxide film, so that the semiconductor device of the present invention can be manufactured without increasing the occupied area.

In other words, the present invention has the following first and second effects.

The first effect is that the base formed by the selective epitaxial growth method can be confirmed to be connected to the base electrode polysilicon film immediately after the epitaxial growth without breaking the wafer without increasing the number of steps. . The reason is that by forming a groove in the insulating film below the base electrode polysilicon film, even if the base electrode polysilicon film is dry-etched, the polysilicon remains in a form buried in this groove, This is because the measurement can be performed by directly applying the needle.

The second effect is that by preparing the insulating film between the base electrode polysilicon film and the silicon collector layer in a plurality of thicknesses, variations in the epitaxially grown base layer in the wafer surface can be reduced. Measurement can be performed without destroying the wafer. The reason is that there are various intervals between the base electrode polysilicon film and the collector layer which are separated by insulating films having different thicknesses.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention, after a base is formed by a selective epitaxial growth method.

FIG. 2 is a longitudinal sectional view showing the first embodiment of the present invention and before forming a base by a selective epitaxial growth method.

FIG. 3 is a longitudinal sectional view showing a manufacturing process in the first embodiment of the present invention.

FIG. 4 is a plan view illustrating a manufacturing process according to the first embodiment of the present invention.

5A and 5B show a manufacturing process in the first embodiment of the present invention. FIG. 5A is a vertical sectional view taken along line AA ′ in FIG. 4, and FIG. 5B is a vertical sectional view taken along line BB ′ in FIG. FIG.

6A and 6B show a manufacturing process according to the first embodiment of the present invention. FIG. 6A is a vertical sectional view taken along line AA ′ in FIG. 4, and FIG. 6B is a vertical sectional view taken along line BB ′ in FIG. FIG.

7A and 7B show a manufacturing process according to the first embodiment of the present invention. FIG. 7A is a longitudinal sectional view taken along line AA ′ in FIG. 4, and FIG. 7B is a longitudinal sectional view taken along line BB ′ in FIG. FIG.

FIG. 8 is a longitudinal sectional view showing a second embodiment of the present invention after a base is formed by a selective epitaxial growth method.

FIG. 9 is a longitudinal sectional view showing a second embodiment of the present invention and before forming a base by a selective epitaxial growth method.

FIG. 10 shows a third embodiment of the present invention and is a longitudinal sectional view after a base is formed by a selective epitaxial growth method.

FIG. 11 is a longitudinal sectional view showing a third embodiment of the present invention and before forming a base by a selective epitaxial growth method.

FIG. 12 is a longitudinal sectional view showing a manufacturing process in the prior art, and the process proceeds in the order of FIGS. 12A, 12B, 12C, and 12D.

[Explanation of symbols]

Reference Signs List 1 p ⁻ type silicon substrate 2 an ⁺ type buried layer 2 b p ⁺ type buried layer for channel stopper 3 Collector layer composed of n ⁻ type silicon epitaxial layer 4 Locos oxide film 5 n ⁺ type collector lead-out region 6 silicon oxide film 6 a silicon oxide Film 6b silicon oxide film 7 p ⁺⁺ type polysilicon film for base electrode 8 n ⁺⁺ type polysilicon film for collector electrode 9 silicon nitride film 10 epitaxially grown intrinsic base layer 10a epitaxially grown intrinsic base layer 10b epitaxially grown intrinsic Base layer 11 p-type polysilicon film 11a p-type polysilicon film 11b p-type polysilicon film 12 p-type polysilicon film 101 opening 101b opening for base epitaxial 102 opening for collector contact 102 opening 103a base slit Opening 104 opening for opening 103b base contact for contact

Claims (11)

[Claims] 1. A semiconductor device having a structure in which a first semiconductor layer and a second semiconductor layer are connected to each other by a selective epitaxial growth method, comprising a conductive layer connected to the first semiconductor layer or A first probe pad composed of the first semiconductor layer itself and a second probe pad composed of a conductive layer connected to the second semiconductor layer or composed of the second semiconductor layer itself. A semiconductor device, comprising: 2. A method according to claim 1, wherein a surface on which the first semiconductor layer is grown by the selective epitaxial growth method and a surface on which the second semiconductor layer is grown by the selective epitaxial growth method are subjected to the selective epitaxial growth method. 2. A structure comprising a plurality of structures having different distances from each other.
13. The semiconductor device according to claim 1. 3. A semiconductor device having a structure in which a base of a bipolar transistor made of single crystal silicon and a base electrode made of polysilicon are connected to each other by a selective epitaxial growth method, wherein a first probe made of the base itself is used. A semiconductor device comprising: a pad; and a second probe pad formed by extending the base electrode on an insulating film. 4. A plurality of structures having different distances between a surface on which the base is grown by the selective epitaxial growth method and a surface on which the base electrode is grown by the selective epitaxial growth method before the selective epitaxial growth method is performed. 4. The semiconductor device according to claim 3, comprising: 5. A method for manufacturing a semiconductor device according to claim 3, wherein a silicon oxide film is formed on a LOCOS oxide film and a collector layer formed on a single-crystal silicon substrate, and the silicon oxide film is formed on the silicon oxide film. Forming a silicon nitride film on the polysilicon film; forming a first opening in a part of the silicon nitride film on the collector layer; and forming a first opening on the LOCOS oxide film. Forming a second opening in a part of the silicon nitride film; removing the polysilicon film and the silicon oxide film under the first opening until the collector layer is exposed; Using selective epitaxial growth for the polysilicon film exposed in the opening and the collector layer exposed in the first opening, polysilicon is grown on the polysilicon film. Growing the single-crystal silicon on the collector layer to form the first probe pad in the first opening and to form the second probe pad in the second opening. A method for manufacturing a semiconductor device, comprising: 6. A partial region to be operated as a transistor is formed by an epitaxial growth method, and in this step, an epitaxial layer has a transistor connected to a region used as an electrode. A semiconductor device, wherein a part of an electrode is exposed. 7. The semiconductor device according to claim 6, further comprising an electrode buried in a sub-micron-width slit groove formed on the element isolation region. 8. The semiconductor device according to claim 6, wherein the distance between the electrode and the base of the epitaxial growth layer is plural. 9. In addition to the transistors used in the circuit,
9. A semiconductor device comprising the transistor according to claim 6, 7 or 8 for checking. 10. A method of manufacturing a semiconductor device, comprising: using the semiconductor device according to claim 6, confirming connection between an epitaxial layer and an electrode immediately after epitaxial growth. 11. The semiconductor device according to claim 8, wherein
A method for manufacturing a semiconductor device, comprising: estimating a film thickness of an epitaxial layer by measuring a plurality of the transistors.