JPH11266009A - Method for manufacturing group III-V compound semiconductor device - Google Patents

Abstract

(57) Abstract: To improve the yield of a group III-V compound semiconductor device having an etch stopper layer. The amount of source gas supplied during growth of the stopper layer is adjusted so that the etching density of the stopper layer is 3000 cm ^-2 or less when the upper layer is etched.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a compound of the group V
An etch stopper layer made of a compound semiconductor containing
The present invention relates to a method for manufacturing a group III-V compound semiconductor device having a semiconductor laminated structure sandwiched between compound semiconductor layers containing As as a group element.

[0002]

2. Description of the Related Art Generally, III-V compound semiconductor devices are formed on a III-V compound semiconductor substrate. Recently, in order to realize high-speed operation, InP is used as a substrate, and InAlAs, InGaAs,
A high electron mobility transistor (hereinafter referred to as HEMT) formed by stacking semiconductor layers such as InP.
ytransistor) has been proposed.

FIG. 6 is a sectional view showing a basic structure of a HEMT having a recess etch stopper layer made of InP. The HEMT shown in FIG. 6 includes a non-doped InAlAs semiconductor layer 102, a non-doped InGaAs semiconductor layer 103, and a semi-insulating substrate 101 made of InP.
Non-doped InAlAs semiconductor layer 104, InAlAs semiconductor layer 105 doped with an n-type impurity, non-doped InAlAs semiconductor layer 106, non-doped InAlAs
P semiconductor layer 107, InA doped with n-type impurities
An lAs semiconductor layer 108 and an InGaAs semiconductor layer 109 doped with an n-type impurity are stacked.

However, the n-type InAlAs semiconductor layer 108
The n-type InGaAs semiconductor layer 109 is formed on the non-doped InP semiconductor layer 107 by a recess groove 112.
Is divided into two areas. Further, ohmic electrodes 110 and 111 are formed on each of the divided n-type InGaAs semiconductor layers 109, respectively.
A Schottky electrode 113 is formed on the semiconductor layer 107.

In such a layer structure, non-doped In
The AlAs semiconductor layer 102 is a buffer layer, a non-doped In layer.
The GaAs semiconductor layer 103 is an electron transit layer, non-doped In
AlAs semiconductor layers 104 and 106 are n-type InAlAs
A spacer layer for more effectively performing selective impurity doping during the growth of the semiconductor layer 105;
The AlAs semiconductor layer 105 is an electron supply layer, undoped In
The P semiconductor layer 107 is a recess etch stopper layer, an n-type I
The nAlAs semiconductor layer 108 and the n-type InGaAs semiconductor layer 109 each function as a resistance reduction layer. The ohmic electrodes 110 and 111 serve as a source electrode and a drain electrode, respectively, and the Schottky electrode 11
3 is a gate electrode.

[0006] In the HEMT shown in FIG.
At the hetero interface between the nGaAs semiconductor layer 103 and the non-doped InAlAs semiconductor layer 104, the two-dimensional electron gas layer 11 is formed.
4 are formed. Source electrode 110 and drain electrode 11
When a voltage is applied between the two-dimensional electron gas layer 114 and
The current flows through. Then, by applying a voltage to the gate electrode 112, the two-dimensional electron gas concentration under the gate changes, so that a transistor operation can be performed.

A semiconductor layer from under the gate to the electron transit layer (in the case of the HEMT shown in FIG. 6, non-doped InAlA
s semiconductor layer 104 to non-doped InP semiconductor layer 107
It is known that when the n-type impurity concentration in the semiconductor layer is constant, the threshold voltage of the HEMT changes in proportion to the square of the thickness of the semiconductor layer. Therefore, how accurately the depth of the recess groove 112 is formed is a key point in improving the characteristics of the HEMT. Therefore, in the HEMT shown in FIG.
The n-type InGaAs semiconductor layer 109 and the n-type InAlAs semiconductor layer 108 are partially etched to form recess grooves 112.
Is formed, the non-doped InP semiconductor layer 107 is inserted so that the progress of etching is stopped at the surface of the non-doped InP semiconductor layer 107. The HEMT shown in FIG. 6 is described in Japanese Patent Application No. 4-290917.

[0008]

Generally, metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE) are used for crystal growth of compound semiconductors.
However, when it is necessary to grow a crystal material containing P, the MOCVD method is generally used in many cases. This MO
In the case where the HEMT shown in FIG. 6 is formed by using the CVD method, since the growth temperature is high in the MOCVD method, reevaporation of As from the deposit attached to the reaction furnace occurs in each step.

When forming the non-doped InP semiconductor layer 107, the flow rate of the phosphine gas as a source gas is set to several tens to several hundreds of sccm (standard cubic centimeter / minu).
te: 1000 sccm = 1 slm) to grow InP. However, at this time, the re-evaporated As enters the InP. That is, As is mixed into the non-doped InP semiconductor layer 107 formed as the recess etch stopper layer.

On the other hand, since the n-type InGaAs semiconductor layer 109 and the n-type InAlAs semiconductor layer 108 are etched to form the recess groove 112, the etching rate for the As-based semiconductor is much faster than the etching rate for the P-based semiconductor. A highly selective etchant is used. However, as described above, the non-doped InP semiconductor layer 107 as the recess etch stopper
, The etching often does not stop at the InP semiconductor layer 107 in the step of forming the recess groove 112. Etching loss of the InP layer 107 usually occurs in a pinhole shape.

At this time, the etching may be performed up to the n-type InAlAs layer 105. n-type InAlAs layer 10
Reference numeral 5 denotes an electron supply layer. When the electron supply layer is etched into a pinhole shape, electrons are not supplied to the two-dimensional electron gas layer 114 from the vicinity of the pinhole. That is, 2
Since the number of electrons supplied to the two-dimensional electron gas layer 114 decreases, the resistance value of the two-dimensional electron gas layer 114 increases. As a result, the threshold voltage of the HEMT changes,
The high-frequency characteristics of T also deteriorate, and the desired device characteristics cannot be obtained.

Further, since the etching of the electron supply layer occurs only when the etching loss reaches the electron supply layer,
Even HEMTs formed on the same wafer have variations in device characteristics. As described above, the conventional method of manufacturing the group III-V compound semiconductor device having the recess etch stopper layer has a problem that the yield in manufacturing the semiconductor device is low.

The present invention has been made to solve such a problem, and an object of the present invention is to improve the yield of a group III-V compound semiconductor device having a recess etch stopper layer.

[0014]

In order to achieve the above object, the present invention provides a method of supplying a first source gas containing As onto a III-V compound semiconductor substrate by metal organic chemical vapor deposition. Forming a first group III-V compound semiconductor layer by a metalorganic chemical vapor deposition method on the first group III-V compound semiconductor layer. A second step of forming a second III-V compound semiconductor layer by supplying a source gas; and a third step of containing As on the second III-V compound semiconductor layer by metal organic chemical vapor deposition.
A third step of forming a third group III-V compound semiconductor layer by supplying a source gas of the third type; and a third step of forming a third group III-V compound semiconductor using an etchant for selectively etching the group III-V compound semiconductor containing As. A fourth step of partially etching the group V compound semiconductor layer to expose the surface of the second group III-V compound semiconductor layer, the method comprising the steps of: The supply amount of the second source gas is adjusted in the second step so that the density at which the second III-V compound semiconductor layer is etched in the step is 3000 cm ^-2 or less. Further, the first III-V compound semiconductor layer is an InAlAs layer, and the second III-V compound semiconductor layer is an InP layer. Further, the phosphine gas is used as the second source gas, and the supply amount of the phosphine gas is increased from 1 slm to 5 s in a temperature range of 610 ° C. to 670 ° C. in the second step.
lm (standard litter / minute). Alternatively, the second III-V compound semiconductor layer is formed of an InGaP layer or an InGaP layer.
This is an AlP layer. The III-V compound semiconductor substrate is an InP substrate. Alternatively, a III-V compound semiconductor substrate is a GaAs substrate.

Also in the second step, As evaporates from the deposits adhering to the inside of the reactor. However, since the evaporation amount of As is determined by the temperature, if the temperature is constant, the amount of As in the atmosphere may be considered to be constant. Therefore,
By adjusting the supply amount of the second source gas containing P but not containing As, the partial pressure ratio of P / As in the atmosphere can be controlled. On the other hand, during the growth of the second group III-V compound semiconductor, P generated by the decomposition of the second source gas and evaporated As are taken in. Therefore, the amount of As mixed into the second III-V compound semiconductor can be reduced by increasing the supply amount of the second source gas and increasing the P / As partial pressure ratio. Second
If the amount of As contained in the III-V compound semiconductor layer decreases, even if the third III-V compound semiconductor layer is selectively etched in the fourth step, the second III-V compound semiconductor layer can be removed. Can be suppressed in the density at which is etched. If this density can be suppressed, the progress of etching to the semiconductor layer formed below the second III-V compound semiconductor layer can be suppressed. In particular, by setting the etching density of the second III-V compound semiconductor layer to 3000 cm ^-2 or less, it is possible to form a III-V compound semiconductor device in which variation in device characteristics is within an allowable range.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a III-V compound semiconductor device according to the present invention will be described in detail with reference to an example of a method for manufacturing a HEMT having a recess etch stopper layer. FIG. 1 and FIG. 2 are cross-sectional views showing the main steps in manufacturing this HEMT.

First, a semi-insulating substrate made of InP (III
-V group compound semiconductor substrate) on which non-doped InA
lAs semiconductor layer (for example, carrier concentration of 10 ¹⁵ cm ⁻³ ,
0.2 μm thick) 2, non-doped InGaAs semiconductor layer (for example, carrier concentration 10 ¹⁵ cm ⁻³ , thickness 0.01
5 μm) 3, non-doped InAlAs semiconductor layer (for example, carrier concentration 10 ¹⁵ cm ⁻³ , thickness 0.003 μm)
4. InAlAs semiconductor layer doped with n-type impurities (for example, carrier concentration 4.5 × 10 ¹⁸ cm ⁻³ , thickness 0.014 μm: first III-V compound semiconductor layer)
5, a non-doped InAlAs semiconductor layer (for example, a carrier concentration of 10 ¹⁵ cm ⁻³ and a thickness of 0.005 μm) 6, a non-doped InP semiconductor layer (for example, a carrier concentration of 10 ¹⁵
cm ^-3 , thickness 0.005 μm: second III-V compound semiconductor layer) 7, InAlA doped with an n-type impurity
an s semiconductor layer (for example, a carrier concentration of 10 ¹⁵ cm ⁻³ and a thickness of 0.02 μm: a third group III-V compound semiconductor layer) 8 and an InGaAs semiconductor layer (for example, a carrier concentration of 10 ¹⁵ cm 3) doped with an n-type impurity ^-3 , thickness 0.01μ
m) The crystals 9 are sequentially grown and stacked (see FIG. 1A).

Each of these layers is grown by MOCVD. The growth temperature is set at 610-670 ° C. Group III source gases include trimethylindium (T
MI), triethylindium (TEI), trimethylaluminum (TMA), triethylaluminum (T
EA), trimethylgallium (TMG), and triethylgallium (TEG) are used. In addition, a hydride of arsine (AsH ₃ ), phosphine (PH ₃ ), or the like is used as the group V source gas.

In particular, as a source gas for the n-type InAlAs semiconductor layer 5, a mixed gas of trimethylindium or triethylindium, trimethylaluminum or triethylaluminum, and arsine as a first source gas is used. The non-doped InP semiconductor layer 7
As the raw material gas, a mixed gas of trimethylindium or triethylindium and phosphine as the second raw material gas is used. As a source gas for the n-type InAlAs semiconductor layer 9, a mixed gas of trimethylindium or triethylindium, trimethylaluminum or triethylaluminum, and arsine as a third source gas is used.

FIG. 3 is a diagram showing optimum conditions for crystal growth of the non-doped InP semiconductor layer 7. The vertical axis indicates the phosphine flow rate, and the horizontal axis indicates the growth temperature. The hatched area surrounded by the straight lines A, B, and C indicates the optimum condition. In order to satisfy this optimum condition, the non-doped InP semiconductor layer 7 is grown in a temperature range of 610 to 670 ° C. and a phosphine flow rate of 1 to 5 slm.

Next, following the step shown in FIG. 1A, two ohmic electrodes 10 and 11 are formed on the uppermost n-type InGaAs semiconductor layer 9 with a space therebetween (FIG. 1).
(B)). Each ohmic electrode 10 and 11 is Ti /
After depositing Pt / Au, it is formed by lift-off.

Next, the two ohmic electrodes 10 and 11
The n-type InGaAs semiconductor layer 9 and the n-type InAlAs semiconductor layer 8 in the region sandwiched between the layers are selectively wet-etched sequentially to partially expose the surface of the non-doped InP semiconductor layer 7. Thus, the recess groove 12 is formed (see FIG. 2A). Here, as an etchant, A
An etchant with a high selectivity, in which the etching rate for the s-based semiconductor is much faster than the etching rate for the P-based semiconductor, is used. For example, a sulfuric acid-based or citric acid-based etchant can be used.

Next, a Schottky electrode 13 is formed on the exposed surface of the non-doped InP semiconductor layer 7 (FIG. 2).
(B)). This Schottky electrode 13 is made of WSiN /
After vapor deposition of Ti / Pt / Au, it is formed by lift-off. Thus, the HEMT is completed.

Even in the layer structure shown in FIG. 2B, the non-doped InAlAs semiconductor layer 2 is a buffer layer, the non-doped InGaAs semiconductor layer 3 is an electron transit layer, the non-doped InAlAs semiconductor layers 4 and 6 are n-type InAlAs semiconductor layers. 5, a spacer layer for more effectively performing selective impurity doping during the growth of the n-type InAlAs
The semiconductor layer 5 is an electron supply layer, a non-doped InP semiconductor layer 7
The recess etch stopper layer, the n-type InAlAs semiconductor layer 8 and the n-type InGaAs semiconductor layer 9 respectively act as resistance reducing layers. Further, each ohmic electrode 10 and 11 becomes a source electrode and a drain electrode, respectively,
The Schottky electrode 13 becomes a gate electrode.

The non-doped InGaAs semiconductor layer 3
A two-dimensional electron gas layer 14 is formed at the hetero interface between the semiconductor layer 4 and the non-doped InAlAs semiconductor layer 4. Therefore,
When a voltage is applied between the source electrode 10 and the drain electrode 11, a current flows through the two-dimensional electron gas layer 14.
Then, by applying a voltage to the gate electrode 12,
The transistor operation can be performed by changing the two-dimensional electron gas concentration under the gate.

Next, the non-doped InP semiconductor layer 7 acting as a recess etch stopper layer will be further described. By forming the InP semiconductor layer 7 so as to satisfy the optimum condition shown in FIG. 3, the performance of the InP semiconductor layer 7 as a recess etch stopper layer is significantly improved. This is shown in the following experimental results.

First, the phosphine flow rate is set to 0.2 to 5 sl.
m, and I grown at each phosphine flow rate.
A HEMT having the nP semiconductor layer 7 was formed. The growth temperature is 610 ° C. The performance evaluation of each InP semiconductor layer 7 as an etch stopper was performed as follows. First, n-type InGaAs was formed using a citric acid-based etchant.
The s-semiconductor layer 9 and the n-type InAlAs layer 8 are removed. Subsequently, the InP semiconductor layer 7 is etched for another 2 minutes using the same etchant. Then, the surface of the InP semiconductor layer 7 after the etching was observed with a microscope, and a pinhole-shaped etching loss density was observed.

FIG. 4 is a diagram showing the relationship between the phosphine flow rate and the etching loss density at this time. The vertical axis is the etching loss density, and the horizontal axis is the phosphine flow rate. It can be seen that as the phosphine flow rate is increased, the density of the etching loss decreases rapidly. In particular,
Etching density at a phosphine flow rate of 1 slm is 3
2,000 cm ^-2 , and when the flow rate is further increased,
The etch-through density was reduced to 600 cm ^-2 . In
The etch pit density (EDP) of the P substrate is 10,000 cm
^-2 phosphine flow rate 1s
It can be said that the value of the etching loss density of lm is a level that does not cause any practical problem.

Conventionally, the flow rate of phosphine supplied during the growth of the InP semiconductor layer 7 was several tens to several hundreds sccm. This phosphine flow rate is increased to 1 sl
By setting m or more, the performance of the InP semiconductor layer 7 as a recess etch stopper layer can be remarkably improved.

The increase in the phosphine flow rate causes a decrease in the density of etched holes due to the following reasons. Since the evaporation amount of As is determined by the growth temperature,
If the growth temperature is constant, the amount of As in the atmosphere may be considered to be constant. Therefore, increasing the phosphine flow rate increases the partial pressure ratio of P / As in the atmosphere. On the other hand, at the time of InP growth, P generated by the decomposition of phosphine and evaporated As are taken in.
Therefore, when the phosphine flow rate is increased and the partial pressure ratio of P / As is increased, the amount of As mixed into the InP semiconductor layer 7 decreases. If the amount of As contained in the InP semiconductor layer 7 is reduced, the density at which the InP semiconductor layer 7 is etched can be suppressed even when etching is performed using an etchant that selectively etches an As-based semiconductor.

Next, the growth temperature is increased by 10 ° C., and the InP semiconductor layer 7 grown at each growth temperature is
The same evaluation as described above was performed. The curve c shown in FIG.
The phosphine flow rate at which the pinhole-shaped etching loss density generated in the InP semiconductor layer 7 grown at each growth temperature is about 3000 cm ^-2 is shown. From this curve c,
As the growth temperature rises, the etch-through density becomes 3
It can be seen that the phosphine flow rate of about 000 cm ^-2 has increased. When the growth temperature is 670 ° C., the phosphine flow rate needs to be 5 slm in order to make the etching loss density about 3000 cm ⁻² .

As the growth temperature increases, the amount of As evaporating from the deposits in the reactor increases. Therefore, it is necessary to increase the phosphine flow rate in order to keep the P / As partial pressure ratio constant. However, when the growth temperature is 610
In the range of 流量 670 ° C., by making the phosphine flow rate higher than the flow rate shown by the curve c, the etching loss density can be made 3000 cm ⁻² or less.

Next, a hole measurement was performed on the HEMT having the InP semiconductor layer 7 grown at each growth temperature. For growth at 610-670 ° C., the mobility is 9000 c
m ² V ⁻¹ s ⁻¹ (the sheet carrier concentration is about 2 × 10 ¹²
(value in cm ⁻² ). However, 670
For growth above ℃, the mobility decreased sharply. It is considered that the reason for this is that, as the growth temperature increases, mutual diffusion occurs at the interface of the grown layer structure, and the steepness of the hetero interface deteriorates. Further, the n-type InA which is an electron supply layer
It is possible that the impurities in the lAs semiconductor layer 5 have diffused to the non-doped InGaAs semiconductor layer 3 which is the electron transit layer by high-temperature growth. In any case, the mobility drops sharply at a temperature of 670 ° C. or higher, which is not suitable for growing a device such as a HEMT that requires a high-speed operation.

On the other hand, at a growth temperature of 610 ° C. or less, FIG.
When the HEMT shown in (B) is formed, the InAlAs crystal grows three-dimensionally. This occurs because the InAlAs crystal contains Al having a short diffusion length at the surface as a group III crystal. Actually, InAl grown at 610 ° C. or lower
When the surface of the As crystal was observed with an atomic force microscope, irregularities of 10 nm or more were observed on the surface. When the InAlAs semiconductor layer 6 is grown at 610 ° C. or lower, an InP crystal is grown on such a surface, and the InP semiconductor layer 7 is grown.
Will be formed.

However, since the InP semiconductor layer 7 is a recess etch stopper layer, it is designed to have a thickness of about 5 nm in order to operate the HEMT at high speed. In the case of InP growth, the diffusion length of atoms on the surface is larger than that of InAlAs. For this reason, the state in which the InP semiconductor layer 7 cannot completely cover the protrusion of InAlAs,
A state occurs in which the film thickness of the semiconductor layer 7 is distributed in the plane. Therefore, if the growth is performed at 610 ° C. or lower, problems such as a decrease in the performance of the InP semiconductor layer 7 as a recess etch stopper layer and inability to obtain desired transistor characteristics occur.

As described above, the growth temperature is set at 610 to
By setting the temperature to 670 ° C., deterioration of transistor characteristics can be prevented, and desired transistor characteristics can be obtained.

As described above, the InP semiconductor layer 7 having sufficient performance as a recess etch stopper layer at 670 ° C.
Requires a phosphine flow rate of 5 slm or more. On the other hand, the optimal hydrogen carrier gas flow rate of the MOCVD apparatus used for studying the present embodiment was 18 slm. Further, the flow rate of the hydrogen carrier gas is generally set within a flow rate range of about 10 to 50 slm so that the uniformity of the film thickness and the composition is optimized.

Therefore, supplying an excessively large amount of phosphine is not desirable because it may change the carrier gas itself and change the optimum condition of uniformity. Actually, in the case of the HEMT shown in FIG.
The above phosphine flow rate had an effect. From the above, it is considered that the practical phosphine flow rate is also about 1 to 5 slm.

Next, the phosphine flow rate was changed in the range of 1 to 5 slm, and the InP grown at each phosphine flow rate was changed.
A HEMT having the semiconductor layer 7 was formed, gate processing was performed, and transistor characteristics were evaluated. The growth temperature is 650
° C. FIG. 5 is a diagram showing the relationship between the phosphine flow rate and the threshold voltage distribution at this time. The vertical axis is the threshold voltage, and the horizontal axis is the phosphine flow rate. In addition,
The design threshold voltage is -0.5V.

According to FIG. 3, the phosphine flow rate at which the pinhole-shaped etching loss density is 3000 cm ⁻² or less is around 3 slm. This phosphine flow rate is shown in FIG.
The threshold value distribution coincides with the flow rate at which the threshold value suddenly decreases. As a result, the etching loss density of the InP semiconductor layer 7 acting as the recess etch stopper layer is reduced to 3
It can be seen that a HEMT having transistor characteristics as designed can be formed by setting it to 000 cm ^-2 or less. Therefore, when the optimum condition shown in FIG.
By forming the P semiconductor layer 7, the performance of the InP semiconductor layer 7 as a recess etch stopper layer is remarkably improved, so that the production yield can be improved.

Although the case where the recess etch stopper layer is formed of InP has been described here, other III
-V compound semiconductors, such as InGaP and InAlP
Are grown so that the etch-through density becomes 3000 cm ^-2 or less, they have the same effect as InP as a recess etch stopper layer. Although the HEMT shown in FIG. 2B has grown on the InP substrate 1, the same applies to the case where the HEMT has grown on a GaAs substrate. Further, in the present embodiment, the InP semiconductor layer 7 is used as a stopper layer at the time of recess etching, but it goes without saying that the InP semiconductor layer 7 can be used as a stopper for etching performed for other purposes.

As described above, the decrease in the selectivity of the InP semiconductor layer 7 during the recess etching is caused by the incorporation of As during the growth of InP. On the other hand, detachment of As from the deposits adhering to the inside of the reactor becomes remarkable when the temperature inside the reactor becomes 600 ° C. or higher. Therefore, in order to suppress As from being mixed into the InP semiconductor layer 7, it is considered that lowering the growth temperature is also effective. However, in the MOCVD method, an organic metal gas is used as a group III source gas, so that high-temperature growth is indispensable for growing a high-purity crystal. In particular, InAlAs crystals grow three-dimensionally at low temperatures. For this reason, when the growth temperature is lowered, as described above, problems such as a decrease in the performance of the InP semiconductor layer 7 as the recess etch stopper layer and the inability to obtain desired semiconductor characteristics occur.

Further, the InAlAs crystal is grown at a high temperature of 610 ° C. or higher, and the growth temperature is once lowered to a level at which As evaporation does not occur, and then InP crystal growth is performed. A method is also conceivable. However, it takes at least several minutes to several tens of minutes to change and stabilize the substrate temperature by the MOCVD method. During this time, it is necessary to keep supplying the group V source gas in order to protect the surface of the grown crystal.

However, a small amount of impurities are mixed in the arsine and phosphine which are the group V source gases. For this reason, there is a risk that impurities may be adsorbed on the growth surface due to a long interruption of the growth. In addition, during the interruption of growth, the surface state changes with time because group III atoms evaporate from the growth surface. It is difficult to control these phenomena, and it is difficult to manufacture a semiconductor device having desired characteristics with good reproducibility by a method using growth interruption.

On the other hand, in the present embodiment, the above-mentioned problem does not occur because the growth temperature can be set to a high temperature of 610 to 670 ° C., and it is not necessary to interrupt the growth. Therefore, according to the present embodiment, it is possible to increase the yield in manufacturing a semiconductor device as compared with the case where the above method is used.

[0046]

As described above, according to the present invention, the third
Etching the III-V compound semiconductor layer of
The second III-V compound semiconductor layer is formed by adjusting the supply amount of the second source gas such that the density at which the second III-V compound semiconductor layer is etched becomes 3000 cm ^-2 or less. . This makes it possible to stabilize the wet etching technique, so that a III-V compound semiconductor device having desired device characteristics can be manufactured with good reproducibility. That is, according to the present invention, III as designed
-A group V compound semiconductor device can be manufactured with high yield.

[Brief description of the drawings]

FIG. 1 HEMT having a recess etch stopper layer
FIG. 7 is a cross-sectional view showing main steps in manufacturing the device.

FIG. 2 is a cross-sectional view showing a step that follows the step of FIG. 1;

FIG. 3 is a diagram showing optimum conditions for crystal growth of a non-doped InP semiconductor layer.

FIG. 4 is a graph showing a relationship between a phosphine flow rate and an etching density when etching a non-doped InP semiconductor layer grown at different phosphine flow rates.

FIG. 5 is a diagram showing a relationship between a phosphine flow rate and a threshold voltage distribution of a HEMT having a non-doped InP semiconductor layer grown at different phosphine flow rates.

FIG. 6: HEMT having a recess etch stopper layer
1 is a cross-sectional view showing a basic configuration of FIG.

[Explanation of symbols]

1 .... a semi-insulating substrate made of InP, 2 .... non-doped I
nAlAs semiconductor layer, 3 ... non-doped InGaAs semiconductor layer, 4 ... non-doped InAlAs semiconductor layer, 5 ...
an InAlAs semiconductor layer doped with an n-type impurity,
6: Non-doped InAlAs semiconductor layer, 7: Non-doped InP semiconductor layer, 8: InAlAs semiconductor layer doped with n-type impurity, 9 ... InGaAs semiconductor layer doped with n-type impurity, 10, 11, ohmic electrode, 12 ... Recessed groove, 13 ... Schottky electrode, 14
... two-dimensional electron gas layer.

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Takachi Enoki 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation

Claims (6)

[Claims] 1. A first step of forming a first III-V compound semiconductor layer by supplying a first source gas containing As onto a III-V compound semiconductor substrate by metal organic chemical vapor deposition. Supplying a second source gas containing P and not containing As onto the first III-V compound semiconductor layer by metal organic chemical vapor deposition to form a second III-V compound semiconductor layer. Forming a third source gas containing As on the second group III-V compound semiconductor layer by metal organic chemical vapor deposition to form a third source gas;
A third step of forming a III-V compound semiconductor layer of the above, and partially etching the third III-V compound semiconductor layer using an etchant for selectively etching a III-V compound semiconductor containing As. To the second III-
A fourth step of exposing the surface of the group V compound semiconductor layer, the method comprising the steps of: exposing the surface of the group V compound semiconductor layer to the third group; and etching the second III-V compound semiconductor layer in the fourth step. A method of manufacturing a group III-V compound semiconductor device, wherein the supply amount of the second raw material gas is adjusted in the second step so that the density is 3000 cm ^-2 or less. 2. The III-V device according to claim 1, wherein said first III-V compound semiconductor layer is an InAlAs layer, and said second III-V compound semiconductor layer is an InP layer. Method for manufacturing group III compound semiconductor device. 3. The phosphine gas according to claim 2, wherein the second source gas is phosphine gas, and the supply amount of the phosphine gas is 1 slm to 5 slm in the temperature range of 610 ° C. to 670 ° C. in the second step.
(Standard letter / minute). A method for manufacturing a group III-V compound semiconductor device, comprising: 4. The method for manufacturing a III-V compound semiconductor device according to claim 1, wherein the second III-V compound semiconductor layer is an InGaP layer or an InAlP layer. 5. The method for manufacturing a III-V compound semiconductor device according to claim 1, wherein the III-V compound semiconductor substrate is an InP substrate. 6. The method for manufacturing a III-V compound semiconductor device according to claim 1, wherein the III-V compound semiconductor substrate is a GaAs substrate.