JPH11271404A - Self-test method and self-test device in a circuit reconfigurable by a program - Google Patents

Abstract

(57) [Summary] [PROBLEMS] For a circuit reconfigurable by a program capable of performing a test having a high failure detection rate with respect to all open, short, and bridge faults of all wiring portions inside a reconfigurable component. It is an object to provide a test method and a self-test apparatus. SOLUTION: In a circuit constituted by a plurality of reconfigurable components, which are a plurality of reconfigurable logic circuit components, and a connection component capable of reconfiguring a connection between the plurality of logic circuit components. The self-test circuit and the connection component are programmed in the reconfigurable component, and the programmed self-test circuit detects a failure of each of the reconfigurable components and the device. is there.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test for manufacturing a reconfigurable circuit having programmable logic circuits and wiring, and a test in the field, which is independent of a specific logic circuit or mounting test function. The present invention relates to a method and an apparatus for realizing a test with a high failure detection rate at a low cost by systematic test pattern generation.

[0002]

2. Description of the Related Art Conventionally, when realizing an emulator used for design verification of a large-scale circuit, or realizing an apparatus capable of responding quickly and flexibly to changes in specifications and functions, a reconfigurable circuit in which logic circuits and wiring are programmable. It is effective to use a device equipped with possible components. That is, when testing a reconfigurable component, a method of testing a variable logic block portion by programming a test circuit in the reconfigurable component has been conventionally proposed.

[0003]

However, in the above conventional example, it is not possible to test all possible open, short, and bridges in all wiring parts, including a programmable connection circuit in a component. There is.

Conventionally, when testing a reconfigurable circuit, an LSI tester is used to test individual components before mounting, a board tester is used to test actual wiring on a board, or a specific test is performed. After programming a logic circuit or function, a functional test is performed.

[0005] In the above-mentioned conventional test method, a component before mounting can be tested, and a test can be executed for a specific circuit element required by a programmed circuit. The detection rate is not sufficient.

Therefore, in the above-mentioned conventional example, when a reconfigurable component is reconfigured, a failure may become apparent, and when a failure detection rate for a functional test in a programmed circuit is low, the test is performed. Even with the above circuit configuration, a failure may become apparent during the operation of the reconfigurable component.

Further, in the above conventional example, there is a problem that there is no test method other than the function test for the programmed circuit regarding the test of the apparatus while the reconfigurable component is in use. That is, after the operation of the reconfigurable component, it is extremely difficult to execute a test using a test pattern having a high fault detection rate using an LSI tester or a board tester, and only an insufficient fault detection rate is obtained. There is no problem.

According to the present invention, there is provided a self-test method for a circuit reconfigurable by a program capable of performing a test having a high failure detection rate with respect to all open, short, and bridge faults in all wiring portions inside a reconfigurable component. And a self-test apparatus.

Also, the present invention provides a method for mounting a reconfigurable component on a device, and then independently of a circuit programmed for use of the reconfigurable component, a stuck-at fault of the entire device, an open connection, It is an object of the present invention to provide a self-test method and a self-test device for a circuit that can be reconfigured by a program capable of performing a test with a high fault detection rate for a short circuit and a bridge fault of a wiring.

Further, the present invention is to execute a test having a high fault detection rate without using a dedicated test device such as an LSI tester or a board tester while using a reconfigurable component of a reconfigurable circuit. It is an object of the present invention to provide a self-test method and a self-test apparatus for a circuit that can be reconfigured by a program capable of performing the following.

Further, the present invention provides a method for detecting a failure in a circuit including a target board, a board, and a device after using a reconfigurable component of the reconfigurable circuit and before reprogramming a different function. It is an object of the present invention to provide a self-test method and a self-test apparatus for a circuit that can be reconfigured by a program capable of performing a test with a high rate.

[0012]

SUMMARY OF THE INVENTION The present invention comprises a plurality of reconfigurable components which are a plurality of reconfigurable logic circuit components;
In a circuit configured by a connection component capable of reconfiguring connection between the plurality of logic circuit components, a self-test circuit and the connection component are programmed in the reconfigurable component, and the program The failure of each of the reconfigurable components and the device is detected by the self-test circuit thus performed.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing the internal configuration of a reconfigurable circuit 100a to be tested in the present invention.

FIG. 2 is a diagram showing a self-test apparatus 100 in a circuit 100a reconfigurable by a program according to an embodiment of the present invention.

The self-test apparatus 100 programs a reconfigurable component with a test circuit, and then the programmed test circuit tests other reconfigurable components. A self-test is performed.

The self-testing apparatus 100 on a board or device reconfigurable by a program (in the following description, “circuit” is used to mean both the board and the device) is specifically shown in FIG. A test pattern generator TPG is programmed in FPGA _m which is one of reconfigurable logic circuit components FPGA _i in a circuit (board or device) having the circuit configuration shown, and a reconfigurable logic circuit different from FPGA _i Parts FPGA _{1 to} FPGA _m-1 ,
The expected value comparison circuit CMP is programmed in the FPGA _{m + 1 to} FPGA _n , and the reconfigurable logic circuit component performs a self test by the test pattern generator TPG and the expected value comparison circuit CMP.

In addition, the self-test apparatus 100 includes reconfigurable connection components (reconfigurable connection circuits SW _{i1 to} S
The connection patterns for testing are sequentially programmed also _in the control pins Ci1 to Cin of (Win), and the circuit is self-tested by the test pattern generator TPG and the expected value comparison circuit CMP for each of the connection patterns. is there.

When the above embodiment is applied to a single reconfigurable component, the reconfigurable logic circuit component FPG shown in FIG.
By using A and associating connection circuits between logic circuits as reconfigurable connection parts SW, the same self-test as described above can be realized.

Next, a method of generating a test pattern in the above embodiment will be described.

FIG. 3 is a diagram showing a crossbar switch circuit SWX (N, M) which models the circuit to be tested in the above embodiment.

Crossbar switch circuit SWX (N, M)
Is a crossbar-shaped network with N pins. First, a method of generating a test pattern set P1 having a length of 2L bits will be described.

One test pattern is composed of 2L bits, and half (L bit) of the constituent bits are 0 and the other half (L bit) is 1. And the set PS0
(L) is a test pattern set (test pattern sequence) having all of the test patterns as elements, and this test pattern set PS0 (L) is input.

The number of elements of the test pattern set PS0 (L) is _2L C _L because it is the number of combinations for selecting L positions from a 2L bit string.

Next, from the test pattern set PS0,
(0, ... 0,1, ..., 1), (1, ... 1,0, ..., 0)
In the 2L bits forming one test pattern, two test patterns of a test pattern in which 0 consecutive L times and a test pattern in which 1 consecutive L times (the change from 0 to 1 is 1) A test pattern set PS1 is generated excluding two test patterns of a test pattern that exists only once and a test pattern that has a change from 1 to 0 only once.

[0025] When determining the respective values of the L bits, the number of elements of the test pattern set PS1 PN (= _2L C _L -
If 2) and the number of pins is N, the value of L is selected so as to satisfy the condition of N ≦ PN. L thus determined
PN test patterns are generated for each input pin X of the crowbar switch circuit SWX (N, M) shown in FIG.
, XN are given different test pattern strings, and the test pattern strings given to the input pins X1,..., XN are used as failure detection test patterns of the crossbar switch circuit SWX (N, M).

For example, if L = 2, the set PS0
The number of elements in (2) is ₄ C ₂ = 6, and the set PS0 (2) = ｛(0,0,1,1), (0,1,
0,1), (0,1,1,0), (1,0,1,0),
(1,1,0,0), (1,0,0,1),｝.

The set PS (2) is obtained by removing (0,0,1,1) and (1,1,0,0) from the set PS0 (2). 0,1,0,1), (0,1,
(1,0), (1,0,1,0), (1,0,0,
1) and｝.

By giving each element of the set PS (2) to a different pin, it is possible to execute a test of a connection component having four or less terminals.

The generated test pattern (test pattern for fault detection) needs to satisfy the following conditions. A test pattern that inputs 0 and 1 to each pin in time series. A test pattern that inputs a change of 0 → 1 and also inputs a change of 1 → 0 for each pin. For any two of the above pins,
(0,1) and (1,0) are set. That is, any two pins Xi, Xj are selected from all the pins, the patterns given to these two pins Xi, Xj are Pi, Pj, and the k-th logical value is Vi (k), Vj (k ), (Vi (k), Vj (k)) = (0, 1), and (Vi (k), Vj
(K)) = a pattern sequence that may be (1, 0).

Each test pattern (test pattern for failure detection) is set to include half of 1 and 0, so that the condition is always satisfied. Also, as described above, (0, ...
Since the two test patterns 0, 1,... 1) and (1,... 1, 0,..., 0) are excluded, the condition is always satisfied.

Since any two test pattern sequences are always different, any two terminals Xi, Xj
(I and j are not equal), Xi = 0, Xj =
A test pattern that becomes 1 always exists in the test pattern series.

The test pattern given to the terminal Xi and the test pattern given to the terminal Xj have the same number of 1s and 0s depending on the conditions. Therefore, if there is a test pattern of Xi = 0 and Xj = 1, Xi = 1 will always be obtained. , Xj = 0 exist in the series. Therefore, the condition is satisfied.

That is, the pattern sequence given to terminal Xi is P
Assuming that the pattern sequence given to i and the terminal Xj is Pj, the pattern sequences Pi and Pj satisfy the following three conditions because they are pattern sequences generated by the test pattern generator TPG. i) the condition that the length is 2L; ii) the condition that the L logical values are 0, and the other L logical values are 1; and iii) the condition that the pattern sequences Pi and Pj are different.

The k-th logical values of the pattern series Pi and Pj are Vi (k) and Vj (k) (1 ≦ k ≦ 2L), respectively. (Vi (k), Vj (k)) are (1, 0),
It takes one of the values (0, 0), (1, 1), and (0, 1). These numbers are respectively represented as A, B,
C and D.

Vi Vj Number of elements 10 A = n ≧ 100 B = L−n 11 C = L−n 0 1 D = n ≧ 1 According to the above condition iii), at least one or more Vi
(K) and Vj (k) are different. That is, Vi (k) =
1, Vj (k) = 0 or Vi (k) = 0, Vj
There is one or more k where (k) = 1. Then, Vi
It is assumed that there are n (n is 1 or more) k where (k) = 1 and Vj (k) = 0.

That is, iV) A = n ≧ 1. Since the number of 0s of Pj is L according to the assumption of ii), V) A + B = L. Similarly, the number of 1 of Pi is L
Vi) A + C = L. Similarly, since the number of 1s in Pj is L, Vii) C + D = L. From iv) and V), Viii) B = L-n, from iv) and Vi), iX) C = Ln, and from Vii) and iX), X) D = n Become. That is, Vi (k) = 1, Vj
If (k) = 0, then Vi (k ′) = 0, V
j (k ') = 1 sometimes, and these are the same number.

By the way, it is possible to detect a stuck-at fault (a fault whether the theoretical value is fixed to 0 or 1) depending on the condition.

Further, an open fault can be detected depending on conditions. Furthermore, when a fixed value is given as an expected value of an input pin corresponding to a portion programmed to be unconnected, when a test pattern that satisfies the condition is input,
Short-circuit failure can also be detected.

When a switch of a logic circuit is realized by CMOS and one of the transistors fails, for example,
Since only one of the operations of 1 → 0 and the operation of 0 → 1 may be particularly defective, the transition of 1 → 0 and 0 →
One transition is required.

Depending on the conditions, it is possible to detect a bridging fault at any two terminals.

Since the circuit to be tested according to the above embodiment is a programmable connection switch within and between reconfigurable components (a programmable connection switch between reconfigurable components), the test for the crossbar switch is performed. The above description in pattern generation has generality.

In the above embodiment, the test pattern generator T
By programming the PG and the expected value comparison circuit CMP into reconfigurable logic circuit components, a self-test of the reconfigurable circuit can be performed. In addition, by providing the test pattern generated by the test pattern generator TPG as a control signal for the reconfigurable connection component, the reconfigurable connection component can be tested.

Next, a test pattern generator TPG and an expected value comparison circuit C for detecting a failure of each reconfigurable component and device.
MP will be described.

First, specific means for configuring the test pattern generator TPG with a shift register will be described.

First, one test pattern contains the same number of 0s and 1s, and changes from 0 to 1 or 1 from all the test patterns in which 0 and 1 are variously combined. A test pattern sequence, which is a set of test patterns excluding a test pattern in which a change from “0” to “0” occurs only once and is a set of test patterns different from each other, is classified.
That is, classification is performed into a set of test pattern sequences obtained by shifting.

The set of test pattern sequences classified into classes is defined as PC1, PC2,. .. Of the test pattern sequence set PC1, PC2,... Whose number is equal to the test pattern length 2L.
, PCi2,..., PCin, an arbitrary test pattern sequence P1∈PCi1, P2∈PCi2,.
By selecting nＰPCin, n shift registers with P1, P2,..., Pn as initial values are configured. These n shift registers are the test pattern generator TPG.

FIG. 4 is a diagram showing the test pattern generator TPG in the above embodiment.

The test pattern generator TPG includes shift registers SR1 to SRn.

[0049] That is, if the initial value P1~Pn shift register SR1~SRn is as _{follows, P1 = (V1 1, V1} 2, ..., V1 2L) P2 = (V2 1, V2 2, .., V2 _2L ) Pn = (Vn ₁ , Vn ₂ ,..., Vn _2L ) FIG. 4 shows the setting of initial values to the n shift registers SR1,. Note that Vi _j = 0 or 1
And 1 ≦ i ≦ n.

The shift register SR1 has a set of test pattern sequences PCi1 = ｛(V1 ₁ , V1 ₂ ,..., V
_{1 2L), (V1 2,} V1 3, ..., V1 1), ......, (V
_{1 2L,} V1 1, ..., is to shift the V1 _2L-1)}. The shift register SR2 has a set PC of test pattern strings.
_{i2 = {(V2 1, V2} 2, ..., V2 2L), (V2 2,
_{V2 3, ..., V2 1)} , ......, (V2 2L, V2 1, ...,
V2 _2L-1 )｝. Further, the shift register SRn has a set of test pattern strings PCin =
｛(Vn ₁ , Vn ₂ ,..., Vn _2L ), (Vn ₂ , Vn
_{3, ..., Vn 1),} ......, (Vn 2L, Vn 1, ..., Vn
_2L-1 ) Shifts｝.

FIG. 5 is a diagram showing a test pattern sequence generated at each output pin of the test pattern generator TPG when the shift register is synchronously shifted 2L times in the embodiment.

As shown in FIG. 5, test patterns having a length of 2 L bits and different from each other are used as test pattern generators TPG.
Is generated for each pin. These generated test patterns are the test pattern series described above. It should be noted that, Xi _j is,
This is an output pin of the test pattern generator TPG.

According to the above embodiment, as shown in FIG.
A test pattern generator TPG for 2L × n pins is generated. A set of test pattern sequences PCi1, PCi2,...
As a result of selecting PCin, if 2L × n <N (that is, if a test pattern sequence for all pins N cannot be generated), the value of L is increased by 1 and a method similar to the above test pattern generation method is performed. Just repeat.

If the test pattern generator TPG is constituted by the shift registers SR1 to SRn, the test pattern generator TPG with the smallest circuit scale can be realized.

For example, when L = 3, 2L = 6, and the entire test pattern sequence PS (3) obtained is: PS (3) = ｛(0,0,1,0,1,1), (0,
1,0,0,1,1), (1,0,0,0,1,1),
(0,0,1,1,0,1), (0,1,0,1,0,
1), (1,0,0,1,0,1), (0,1,1,
0,0,1), (1,0,1,0,0,1), (1,
1,0,0,0,1), (0,0,1,1,1,0),
(0,1,0,1,1,0), (1,0,0,1,1,1)
0), (0, 1, 1, 0, 1, 0), (1, 0, 1,
0,1,0,), (1,1,0,0,1,0), (0,
1,1,1,0,0), (1,0,1,1,0,0),
(1,1,0,1,0,0)}.

When these are classified by the shift operation, the following four classes can be generated.

PC1 = ｛(0,0,1,0,1,1),
(0,1,0,1,1,0), (1,0,1,1,0,
0), (0,1,1,0,0,1), (1,1,0,
0,1,0), (1,0,0,1,0,1)} PC2 = {(0,1,0,0,1,1), (1,0,
0,1,1,0), (0,0,1,1,0,1),
(0,1,1,0,1,0), (1,1,0,1,0,
0), (1,0,1,0,0,1)} PC3 = {(1,0,0,0,1,1), (0,0,
1,1,1,0), (0,1,1,1,0,0),
(1,1,0,0,0,1)} PC4 = {(0,1,0,1,0,1), (1,0,
1,0,1,0)｝ The number of elements among PC1 to PC4 is as follows: test pattern length = 2
Since PC1 and PC2 are equal to L = 6, P
C1 and PC2 are selected as a test pattern set. That is, PCi1 = PC1, PCi2 = PC2. P
An arbitrary test pattern, for example, a leading element is selected from C1 and PC2, and is selected by shift registers SR1 and SR2.
And the initial value. That is, P1 = (0, 0, 1,
0,1,1) and P2 = (0,1,0,0,1,1) are the initial values of the shift register. The initial value of each bit of the shift register is V11 = 0, V12 = 0, V13 = 1,
V14 = 0, V15 = 1, V16 = 1, and V21 =
0, V22 = 1, V23 = 0, V24 = 0, V25 =
1, V26 = 1. Shift registers SR1 and SR2
Thus, a test pattern for 12 pins can be generated.

FIG. 6 is a diagram showing test patterns generated by shift registers SR1 and SR2 when 2L = 6 in the above embodiment.

The expected value comparison circuit CMP is configured in a counterpart reconfigurable component connected to a reconfigurable component configured as a test pattern generator TPG, and is provided with a corresponding shift register SR1 to SRn and an initial value. It comprises a value setting circuit, a comparison circuit, and an expected value compression circuit.

The shift registers SR1 to SRn in the expected value comparison circuit CMP perform a shift operation in synchronization with the shift register of the test pattern generator TPG to perform successive comparison. If necessary, the result of the successive approximation is compressed by a compression circuit. Then, the expected value comparison circuit CMP can be easily configured by a circuit that implements the exclusive OR.

In general, the expected value to be set varies depending on the state of the reconfigurable connection component. However, in the above embodiment, the test pattern itself is automatically generated. By generating the state of the test pattern generator, not only the test pattern and the connection test pattern of the test pattern generator TPG, but also the test pattern generator TP
G, the expected value comparison circuit CMP can be realized by one type of circuit configuration.

In the above embodiment, when the self-test is performed after the use of the reconfigurable component, the circuit is provided with means for programming a test pattern generator TPG and an expected value comparison circuit CMP, and a test mode is provided. In the test mode, the test pattern generator TPG or the expected value comparison circuit CM
By sequentially programming P (circuit reconfiguration), a self-test can be realized.

That is, a circuit constituted by a plurality of reconfigurable components, which are a plurality of reconfigurable logic circuit components, and a connection component capable of reconfiguring the connection between the plurality of logic circuit components. A first program stage, a test execution stage, a repetition stage,
The method may include a step of reprogramming and a step of executing the same steps as the first program step, the test execution step, the repetition step, and the reprogramming step for the connection component.

In the above-mentioned first program stage, one test pattern includes the same number of 0s and 1s, and 0s and 1s.
From all the test patterns that are variously combined,
A test pattern in a test pattern sequence that is a set of test patterns excluding a test pattern in which a change from 0 to 1 or a change from 1 to 0 occurs only once, and is a set of test patterns different from each other. The test pattern generator to be generated
This is a first programming stage of programming one reconfigurable component and programming an expected value comparator in another reconfigurable component. The test execution step is a test execution step of executing a test using the test pattern generator and the expected value comparator each time the test pattern generator sequentially programs the test patterns one by one.

In the repetitive repetition step, when all the test patterns in the test pattern sequence have been programmed, the next reconfigurable component is selected, and the first reconfigurable component is selected for the selected reconfigurable component. A repetition step of executing the step and the test execution step, and selecting the reconfigurable parts, repeating the first program step, and the test execution step. The reprogramming step is a reprogramming step of reprogramming the test pattern generator and the expected value comparator into the reconfigurable component when the test execution step is completed for all reconfigurable components. .

The method of reconfiguring the circuit while the reconfigurable component is in use may be any of the well-known methods, such as a method having a plurality of program ROMs, a method of downloading from a host, and the like. It should just be selected according to.

FIG. 7 is a diagram showing a configuration example of the board B1 as a reconfigurable circuit to be tested in the above embodiment.

The connection reconfigurable parts SW0, SW1,...
Is for connecting a plurality of reconfigurable logic circuit components FPGA. One reconfigurable logic circuit component F
Focusing on PGA, 44 groups (5 bit width each)
Is connected to another reconfigurable logic circuit component FP via 180 connection reconfigurable components SW (5 bits each width).
Connected to GA.

FIG. 8 shows the configuration of the reconfigurable board B for testing the reconfigurable board B1 in the above embodiment.
1 is a block diagram showing an example in which a self-test apparatus 101 is configured.

The test pattern generator TPG in the self-test apparatus 101 is a reconfigurable component in which the test pattern generation circuit is programmed, and the expected value comparison circuit CMP
The expected value comparator and the compressor are reconfigurable components that are programmed.

FIG. 9 is a flowchart showing the operation in the above embodiment.

One Reconfigurable Logic Circuit Component FPGA
_i is selected as a test pattern generator TPG, the shift registers SR1 to SR22 are programmed, and another reconfigurable logic circuit component FPGA is programmed as an expected value comparator CMP (S1). One of the connection part test patterns is programmed into the control pin of the connection part (S2). The test pattern generator TPG and the expected value comparator CMP are started in synchronization, and a test result comparison is executed as test pattern generation (S3). It is determined whether or not all the test patterns given to the connection parts have been completed. If not completed (S4), the test patterns given to the connection parts are changed (S5), and the process returns to step S2. It is determined whether or not all the reconfigurable logic circuit components FPGA have been programmed as the test pattern generator TPG (S6), and if completed, the test is terminated (S6).
8) If not finished, reconfigurable logic circuit component FPG not programmed as test pattern generator TPG
A is selected (S7), and the process returns to step S1.

As described above, the reconfigurable logic circuit components are sequentially programmed as the test pattern generator TPG,
Each of the above tests can be realized by programming another reconfigurable component as the expected value comparator CMP.

FIG. 10 is a diagram showing an example of test pattern generation when the bit length of the test pattern is 2L = 10 bits in the above embodiment.

When 2L = 10, the number of test patterns is
A _2L C _L -2 = 250, 250 pieces of the test pattern is generated. This test pattern is classified into a set PCi1,..., PCi22 of 22 test pattern sequences in order to make a test pattern for the number of pins of the reconfigurable component = 220, and a set PCi1,. P
From among Ci22, P1 @ PCi1,..., P22 @ P
Select Ci22. The result of the selection is the test pattern shown in FIG. 10, and FIG. 10 shows only the initial values of the 22 shift registers. In addition, ten pins correspond to each shift register, and as a result, a test pattern for the number of pins of the reconfigurable component = 220 can be obtained.

FIG. 11 is a diagram specifically showing an example of a test pattern sequence in which the number of pins generated is 22 and the bit length of the test pattern is 10 in the above embodiment.

When the shift registers SR1 to SR22 storing the initial values P1 to P22 shift ten times, a test pattern sequence having a test pattern bit length = 10 bits can be supplied to the 220 pins. FIG. 11 shows a test pattern sequence having a length of 10 bits set to each pin of the reconfigurable logic circuit by shifting in this manner.

[0078] Figure 12, the expected value generation circuit SR1 in the above embodiment, ... SRi and an expected value comparator CMP, the result compression circuit expected value comparator _{CMP 0, CMP 1, ......,} CM
It is a diagram illustrating a configuration example of the P _i.

The expected value generation circuits SR1,..., SRi are circuits for generating a test pattern of the same sequence as the test pattern sequence generated by the test pattern generator TPG.
1,..., Are circuits realized by programming as SRi.

The expected value comparator CMP is realized by exclusive OR. Result compression is performed by a compressor expected value comparator CMP1,..., CMPi for compressing each time series, and a compressor expected value comparator CMP0 for further compressing those results.
It is composed of steps. As a result, when there is a failure on the board, a failure detection result is output to the test result output pin shown in FIG. 12, and the failure of the board can be detected by observing the output failure detection result. .

The expected value generation shift registers SR1 to SR1
SRn corresponds to a test pattern generated by the connected test pattern generator TPG.

FIG. 13 is a diagram showing the relationship between the number of test pattern bits 2L and the number of pins N in the above embodiment.

According to the above-described embodiment, in a test of a circuit that can be reconfigured by a program, all possible open / short faults of a wiring and a bridge fault between two arbitrary wirings can be detected. .

If a mechanism for programming the self-test circuit of the above embodiment is added, a dedicated test device such as an LSI tester or a board tester may be used instead of a dedicated test device such as an LSI tester or a board tester. And the same failure can be detected.

In this specification, the “circuit” as a test object includes both a board and a normal device.

[0086]

According to the first aspect of the present invention, in a test of a circuit that can be reconfigured by a program, an open failure of all programmable connection forms between components can be performed independently of a circuit or a function to be programmed. A self-test for detecting a stuck-at fault and a bridge fault between two arbitrary wirings can be performed, so that the effect of improving the reliability of a circuit reconfigurable by a program can be achieved.

According to the second aspect of the present invention, since the number of test patterns 2L and the number of pins N have the relationship shown in FIG. 13, the test pattern of wiring between multi-pin components can be reduced with a short test pattern length. The effect of being able to generate | occur | produce can be produced.

According to the third aspect of the present invention, there is an effect that the circuit can be realized with a sufficiently small circuit scale that can be mounted on a reconfigurable logic circuit.

According to the fourth aspect of the present invention, a low-cost and highly-reliable test can be executed in a short time while a reconfigurable component of a circuit is being used or before the reconfiguration. In other words, this program mechanism has an effect that it can be easily realized by a conventional technique such as download from a host or a ROM for configuring a test circuit.

[Brief description of the drawings]

FIG. 1 is a diagram showing an internal configuration of a reconfigurable circuit 100a to be tested in the present invention.

FIG. 2 is a diagram showing a self-test apparatus 100 in a circuit 100a reconfigurable by a program according to an embodiment of the present invention.

FIG. 3 is a diagram showing a crossbar switch circuit SWX (N, M) obtained by modeling the test target circuit of the embodiment.

FIG. 4 is a diagram showing a test pattern generator TPG in the embodiment.

FIG. 5 is a block diagram showing the configuration of the embodiment,
FIG. 9 is a diagram showing a test pattern sequence generated at each output pin of a test pattern generator TPG when shifting synchronously L times.

FIG. 6 is a diagram showing test patterns generated by shift registers SR1 and SR2 when 2L = 6 in the embodiment.

FIG. 7 is a diagram showing a configuration example of a board B1 as a reconfigurable circuit to be tested in the embodiment.

FIG. 8 shows a reconfigurable board B1 in the embodiment.
FIG. 3 is a diagram showing an example in which a reconfigurable board B1 is configured as a self-test device 101 in order to test.

FIG. 9 is a flowchart showing an operation in the embodiment.

FIG. 10 is a diagram illustrating an example of generation of a test pattern when the bit length of the test pattern is 2L = 10 bits in the embodiment.

FIG. 11 shows that the number of generated pins is 2 in the embodiment.
FIG. 2 is a diagram specifically illustrating an example of a test pattern sequence in which the bit length of the test pattern is 10.

FIG. 12 shows an expected value generating circuit SR1,
... and SRi, illustrates the expected value comparator CMP, the result compression circuit expected value comparator CMP _0, CMP _1, ......, a configuration example of the CMP _i.

FIG. 13 is a diagram showing a relationship between the number of bits 2L of a test pattern and the number of pins N in the above embodiment.

[Explanation of symbols]

100a: Reconfigurable circuit by program, 100, 101: Self-test device, FPGA: Reconfigurable logic circuit component, CMP: Expected value comparison circuit, SW _{i1 to} SW _in : Reconfigurable connection circuit, Ci1 ~ Cin: control pin, SWX (N, M): crossbar switch circuit, P1: test pattern set, TPG: test pattern generator, SR1 to SRi: shift register as expected value generation circuit, PC1, PC2, ... test A set of pattern sequences.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Ken Takeya 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation

Claims (4)

[Claims] 1. A circuit comprising a plurality of reconfigurable components, which are a plurality of reconfigurable logic circuit components, and a connection component capable of reconfiguring a connection between the plurality of logic circuit components. A program step of programming the self-testing circuit and the connection component in the reconfigurable component; and performing a fault in each of the reconfigurable components and the device by the programmed self-testing circuit. A fault detection step for detecting;
A self-test method for a circuit reconfigurable by a program, comprising: 2. The failure detection step according to claim 1, wherein the number of 0s and the number of 1s are included in one test pattern,
Among all test patterns in which 0 and 1 are variously combined, a set including test patterns excluding a test pattern in which a change from 0 to 1 or a change from 1 to 0 occurs only once is an element. A test pattern sequence generating step of generating a test pattern sequence as a set of test patterns different from each other; and a test pattern sequence applying step of sequentially applying the generated test pattern sequence to each pin of a circuit to be tested. Detecting a stuck-at fault of all the pins, an open fault and a short-circuit fault of all programmable wires, and a bridge fault between all two programmable wires by applying the test pattern sequence; A self-test method for a circuit reconfigurable by a program, the method comprising: 3. A circuit constituted by a plurality of reconfigurable components, which are a plurality of reconfigurable logic circuit components, and a connection component capable of reconfiguring a connection between the plurality of logic circuit components. In one test pattern, the same number of 0s and 1s are included in one test pattern,
Among all test patterns in which 0 and 1 are variously combined, a set including test patterns excluding a test pattern in which a change from 0 to 1 or a change from 1 to 0 occurs only once is an element. Test pattern sequence generating means for generating a test pattern sequence that is a set of test patterns different from each other; and an expected value comparison circuit for detecting a failure between each of the reconfigurable components and the device. A self-test apparatus for a circuit reconfigurable by a program, wherein the pattern sequence generating means and the expected value comparison circuit are programmed in the reconfigurable component. 4. A circuit comprising a plurality of reconfigurable components, which are a plurality of reconfigurable logic circuit components, and a connection component capable of reconfiguring a connection between the plurality of logic circuit components. In the self-test method, the same number of 0s and 1s are included in one test pattern,
Among all test patterns in which 0 and 1 are variously combined, a set including test patterns excluding a test pattern in which a change from 0 to 1 or a change from 1 to 0 occurs only once is an element. Program a test pattern generator that generates test patterns in a test pattern sequence that is a set of test patterns different from each other into one reconfigurable component, and program an expected value comparator into another reconfigurable component. A first program step of executing a test by the test pattern generator and the expected value comparator each time the test pattern generator sequentially programs the test patterns one by one; When all the test patterns in the test pattern sequence have been programmed, the next reconfigurable part is selected, and the first reconfigurable part is selected from the first reconfigurable part.
Performing the program step and the test execution step, selecting the reconfigurable parts, and repeating the first program step and the test execution step; and repeating the test step for all the reconfigurable parts. Re-programming the test pattern generator and the expected value comparator into the reconfigurable component when the execution stage is completed; the first program stage and the test execution for the connection component Performing the same steps as the reprogramming step, the repetition step, and the reprogramming step, wherein the circuit is reconfigurable by a program that tests for open, short, and bridging faults of all possible wires on the device. Self-test method in.