JPH11273263A - Digital information reproducing apparatus and digital information recording / reproducing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce cost and improve reliability by applying PR4ML in a recording / reproducing apparatus using NRZI precode. SOLUTION: BMC86, ACS88 and PMU9
0, a first Viterbi decoder comprising BMC8
7. The parallel processing is performed by supplying the odd-numbered sequence and the even-numbered sequence of the reproduction signal equalized by PR4 to the second Viterbi decoder constituted by the ACS 89 and the PMU 91, respectively. By providing a register 92 and exclusive OR circuits 93 and 94 at the subsequent stage, reproduced data DET_0 and DET_1 are generated using outputs DET_0 and DET_1 of each Viterbi decoder. With the above configuration, PR4ML can be applied to a recording / reproducing apparatus such as a D1-VTR using an NRZI precode, and a reduction in cost and an improvement in reliability can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital information reproducing apparatus and a digital information recording / reproducing system using an NRZI code as a recording modulation code, such as a digital VTR of the D1 system.

[0002]

2. Description of the Related Art PRML (Partial Respo) is a decoding method combining a partial response and a maximum likelihood decoding method.
As one type of nse maximum likelihood, PR4ML in which a partial response class 4 (hereinafter referred to as PR4) and a Viterbi decoder are combined is known. This PR4ML is put to practical use in digital VTRs such as a DVC (Digital Video Cassette) and a digital betacam, and realizes a drastic reduction in error rate as compared with conventional binary identification based on Nyquist's first standard. .
Here, PR4 is an equalization method in which an equalization characteristic applied to a reproduction signal reproduced from a recording medium is PR (1, 0, -1).

[0003] The reason that PR4ML is preferably used is that
The equalization characteristic of R4 has no DC component and is close to the transfer characteristic of magnetic recording, and a Viterbi decoder capable of high-speed operation can be easily configured by performing parallel processing. That is, in PR4ML, when decoding data based on a reproduction signal reproduced from a recording medium, it is easy to configure a Viterbi decoder configured to obtain an odd sequence and an even sequence by independent processing. It is.

Conventionally, when a partial response is used, it has been premised that precoding as recording modulation coding is performed in order to suppress error propagation. PR4
, A precoding called interleaved NRZI is performed. The input data to be recorded is a [k],
Assuming that data called an intermediate sequence actually recorded on the recording medium is b [k], this precode can be expressed as follows.

B [k] = mod 2 (b [k−2] + a [k]) (1) Here, mod 2 indicates a modulo-2 operation. According to the conventional thinking, performing the precoding of the interleaved NRZI suppresses the error propagation and has an effect of making the odd sequence and the even sequence independent of each other. According to this operation, a Viterbi decoder capable of high-speed operation, which performs parallel processing by arranging two simple ternary two-state Viterbi decoders, has been described.

For this reason, when a recording format other than interleaved NRZI, for example, NRZI (Non Return to Zero Inverted) precoding is used, even if PR4ML is applied, a Viterbi decoder that performs parallel processing can be easily implemented. It was thought that it could not be configured. In such a case, it was considered that error propagation was inevitable. The NRZI precode is represented by the following equation (2).

B [k] = mod2 (b [k−1] + a [k]) (2)

[0008]

Under such a concept, PR4ML has not been applied to a recording / reproducing apparatus which uses a recording format based on the precoding of NRZI even when the format is extended. . As such a recording / reproducing apparatus, for example, a commercial digital V
There are a digital VTR of the D1 system conforming to the TR standard, a data recorder using a DIR format defined based on a recording format of the D1 system, and the like. For this reason, in these recording / reproducing devices, there is a problem that it is difficult to reduce costs and improve reliability.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a digital information reproducing apparatus and a digital information recording / reproducing system which realize a reduction in cost and an improvement in reliability when a recording format based on the precoding of NRZI is used. Is to do.

[0010]

According to a first aspect of the present invention, there is provided a digital information reproducing apparatus for reproducing recorded data based on a reproduced signal reproduced from a recording medium, wherein an NRZI code is used as a recording modulation code, and First having a configuration
And a second Viterbi decoder are provided in parallel, the reproduced signal is equalized under predetermined equalization characteristics, the equalized signal is divided into an even sequence and an odd sequence, and each is divided into a first Viterbi decoder. Supply to a decoder and a second Viterbi decoder;
A digital information reproducing apparatus for decoding an NRZI code based on an output of a first Viterbi decoder and an output of a second Viterbi decoder.

According to the present invention, in a digital information recording / reproducing system for recording / reproducing digital information, a recording / modulation code generating means for converting data to be recorded into an NRZI code, and a recording / reproducing means for recording / reproducing the NRZI code. A first Viterbi decoder and a second Viterbi decoder having the same configuration in parallel, and an equalizer for PR4 equalizing a reproduced signal supplied from the recording / reproducing unit. Equalizing under the equalization characteristic, dividing the equalized signal into an even sequence and an odd sequence, supplying them to a first Viterbi decoder and a second Viterbi decoder, respectively, A digital information recording / reproducing system which decodes an NRZI code based on the output of the second Viterbi decoder.

According to the above-described invention, PR4ML can be applied even when an NRZI code is used as a recording modulation code.

For this reason, even when the NRZI code is used as the recording modulation code, it is possible to generate highly reliable decoded data which is a feature of PR4ML.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, in describing the present invention, a conventional concept will be described for easy understanding.

<Partial Response> According to Nyquist's first criterion using an equalization method for suppressing intersymbol interference, a response to a unit pulse is represented by the following equation (3). That is, the amplitude is set to 1 only at the center of the response t = 0, and at other times, the clock period T
_The amplitude is set to 0 at each time point separated by ₀ (see FIG. 1A).
FIG. 1B shows an example of the frequency characteristic based on the Nyquist's first reference. 1A and 1B show the case where the roll-off rate is set to 1.0.

P (t) = 1 (t = 0) = 0 (t = nT ₀ , n is other than 0) (3) On the other hand, if the partial response is strictly defined, a predetermined code is used. It is an equalization characteristic in which inter-interference continues for several bits. That is, in the partial response PR (λ, μ, ν), the response to the unit pulse is represented by the following equation (4), and T ₀
It has amplitudes of λ, μ, and ν at intervals.

P (t) = λ (t = 0) = μ (t = T ₀ ) = ν (t = 2T ₀ ) = 0 (t = nT ₀ , n is other than ₀ , 1, 2) (4) As a partial response that is actually frequently used, there is a class 4 of the partial response. this is,
PR (1, 0, -1) with the notation is introduced a delay operator D of T ₀ hours, (1 + D) × ( 1-D) = 1-D
^It can be expressed as ² . 2A and 2B show the unit impulse response and frequency characteristics of PR4.

[0018] As described above <decoded in PR4>, PR (1,0, -1 ) because the 1-D ^2, the output c of the equalizer [k], the most recent data in the data sequence to be reproduced b [k] and recording data b [k−
2] and can be expressed as follows.

C [k] = b [k] −b [k−2] (5) An example of b [k] and c [k] according to equation (5) is shown below.

B [k]: 1 0 0 1 0 0 0 0 1 1 0 0 1 1 1 1 1 0 1 c [k]: ** -1 +1 0 -1 0 0 +1 +1 -1- Since 1 +1 +1 0 0 0 -1 0 b [k] takes one of the values 1 and 0, the value of c [k] is calculated in the following three cases according to the equation (5). It can be seen that they can be divided.

When b [k-2] = 0, b [k] = 1: c [k] = 1 (6) When b [k-2] = 1, b [k] = 0: c [ k] =-1 (7) When b [k-2] = b [k]: c [k] = 0 (8) Therefore, b [bit by bit] based on the value of c [k] k] is determined as follows.

C [k] = − 1 → b [k] = 0 (9) c [k] = 0 → b [k] = b [k−2] (10) c [k] = + 1 → b [ k] = 1 (11) By such identification, it is possible to decode the recording data b [k] from the output of the equalizer that performs the equalization process according to PR4.

<Error Propagation in PR4> Next, c
The case where [k] includes an error will be described. As an error that can be included in c [k], when c [k] = + 1 is erroneously output as “c [k] = 0”, c [k] = 0 is erroneously output as “c [k] = -1 "or" c [k] = + 1 "and c [k] =-1 is incorrectly output as" c
[K] = 0 "is output. c
When [k] includes these three types of errors, equations (6) to
The effect on b [k] decoded according to (8) will be described.

First, in an example of the correspondence between b [k] and c [k], b [k] decoded when c [k] includes these three types of errors is shown below. here,
Of the data in b [k] and c [k], those that are erroneous are indicated with # below.

In the case of: c [k]: ** -1 +1 0 -1 0 0 0 +1 -1 -1 +1 0 0 0 0 -10 # #b [k]: 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 # # #; c [k]: * * -1 +1 +1 -1 0 0 +1 +1 -1 -1 +1 +1- 1 0 0 -1 0 # # b [k]: 1 0 0 1 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 # # # # For #; c [k]: * * 0 +1 0 -1 0 0 +1 +1 0 -1 +1 +1 0 0 0 -1 0 # *% $ # b [k]: 1 0 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0 1 # # # # Hereafter, b [k], b [k + 2], b [k + 4]... Are even-numbered columns, b [k + 1], b [k + 3], b [k + 5].
.. is divided into odd columns and each is considered. At this time, in the even-numbered column or the odd-numbered column where the error has occurred, the error is output until c [k] =-1 or c [k] = + 1 is correctly output and b [k] = 0,1 is correctly determined. Propagate. That is, once an error occurs, the subsequent c
Even if [k] = 0 is correctly output, error propagation continues.

For example, in the case of the above example, the error data (c [k] =-1) which occurs first in c [k] in the case of
→ One bit position (*) following c [k] = 0)
), C [k] = 0 is correctly output, but b [k] is incorrect (b [k] = '0' → b [k]
= '1') has occurred. 1 following the bit position
Even at the bit position (with% added), c
Although [k] = 0 is correctly output, an error (b [k] = '0' → b [k] = '1') has occurred in b [k].

At the next bit position (added by ＄) following the bit position indicated by%, c [k] = + 1 is correctly output. At this bit position, b [k] is correctly obtained.

Therefore, the worst pattern in which the error propagates over the most bit positions is that b [k] is 000000, when c [k] = 0 is continuously output in even or odd columns, Or 11
This is a case where a DC pattern like 1111 is recorded. In the case where such a DC pattern is recorded for an even-numbered column or an odd-numbered column, if an error occurs once in the output of c [k], an error occurs again and c [k] = + 1 or −1 is output. B [k] to be decoded until
, Error propagation occurs continuously.

[0029] In the recording / reproducing system assuming the PR4 <precoded in PR4>, in the recording to be data such as user data, which is inverse characteristic of the 1-D ² 1 / (1-
D ² ) is multiplied to generate an intermediate sequence, and if this intermediate sequence is recorded on a recording medium, the output of the equalizer that performs PR4 equalization becomes independent, thereby suppressing error propagation. It is known that it can be done. A recording / reproducing apparatus that performs such precoding will be described with reference to FIG. Input data a [k] (that is, data to be recorded such as user data) is input to the precoder 10. The precoder 10 adds 1 / (1) to the input data a [k].
-D ² ) to generate an intermediate sequence b [k] and supply it to the recording / reproducing system 11 having, for example, a magnetic head, a magnetic disk, and the like. Thereby, the intermediate sequence b
[K] is recorded on the recording medium.

On the other hand, the reproduction system has an equalizer 12,
The equalizer 12 performs PR4 equalization on the reproduction signal reproduced from the recording medium, generates an equalized reproduction signal c [k], and supplies it to the binary discriminator 13. Binary classifier 13
Is a bit-by-bit input data a based on the equalized reproduction signal c [k] according to the equation (14) described later.
Play [k].

The precoding performed by the precoder 10 will be described in more detail. Such a precode is expressed as follows.

B [k] = mod2 (b [k−2] −a [k]) (12) Since addition and subtraction are equivalent in the remainder system of 2, equation (12) is Can also be expressed as

B [k] = mod2 (b [k−2] + a [k]) (13) According to the precode, when a [k] = 0, b
[K] = b [k−2], while when a [k] = 1, b [k] is the inverse of b [k−2]. That is, the determination of the value of b [k] is b [k−
2] is involved. Therefore, this precoding is equivalent to a process of dividing the input data a [k] into every other into an odd series and an even series, and performing NRZI conversion on each of the odd series and the even series. Such a precode is an interleaved NRZI precode.

The recording / reproducing operation based on the precoding of the interleaved NRZI will be described more specifically.
As an example, consider the following input data a [k].

A [k]: 101 1 0 1 0 0 1 1 1 1 1 1 1 0 0 0 1 0 In this a [k], the interleaved N according to the equation (13)
The intermediate sequence obtained by applying the RZI precoding has the same data sequence as b [k] described above.

B [k]: 1 0 0 1 0 0 0 0 1 1 0 0 1 1 1 1 1 1 0 0 The output c [k of an equalizer that performs PR4 equalization corresponding to such b [k] ] Is the same data string as the above c [k]. According to (Expression (5)), the following is obtained.

C [k]: ** 0 +1 0 -1 0 0 +1 +1 0 -1 +1 +1 0 0 0 -1 0 As described above, interleaved as shown in Expression (13) In the NRZI precode, b [k] is obtained by inverting b [k−2] when a [k] = 1. That is, when a [k] = 1, b [k−2] and b [k]
C [k] = + 1 or -1 because the relationship with satisfies any of the above equations (6) and (7). Also, a
When [k] = 0, the relationship between b [k−2] and b [k] corresponds to the above equation (8), and c [k] = 0. Therefore, if the reproduced data is obtained directly from c [k] according to the following equation (14), the error can be prevented from propagating.

A ′ [k] = mod2 (c [k]) (14)
As described above, the binary classifier 13 in FIG.
The operation according to is performed. In equation (14), a '[k] is
This indicates that the data is reproduction data for the input data a [k] (accordingly, if there is no reproduction error, a '[k] matches a [k]).

In such a case, an error-containing c
[K] will be described with reference to the example used in the above description. That is, c [k] = + 1 is erroneously described as “c [k] =
0 is output, c [k] = 0 is erroneously described as “c
[K] = − 1 ”or“ c [k] = + 1 ”, and c [k] = − 1 is incorrectly output as“ c [k] =
The case where "0" is output will be described. Of the data in b [k] and c [k], those that are erroneous are indicated with # below.

In the case of: c [k]: ** -1 +1 0 -1 0 0 0 +1 -1 -1 +1 0 0 0 0 -10 # # a '[k]: 1 0 1 1 0 1 0 0 1 1 1 1 1 0 0 0 0 1 0 # #; c [k]: * * -1 +1 +1 -1 0 0 +1 +1 -1 -1 +1 +1- 1 0 0 -1 0 # # a '[k]: 1 0 1 1 1 1 0 0 1 1 1 1 1 0 0 1 0 0 1 0 # # In case of #; c [k]: * * 0 +1 0 -1 0 0 +1 +1 0 -1 +1 +1 0 0 0 -1 0 # # a '[k]: 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 1 0 # # Thus, in any case, the erroneously output c
Only a '[k] corresponding to [k] becomes an error, and no error propagation occurs.

<PR4ML and Precoding> PR4ML on the premise of precoding by interleaved NRZI
Is originally configured as a Viterbi decoder that performs decoding based on a state transition diagram as shown in FIG. Here, the state transition diagram includes transitions between several states defined by a plurality of data values that affect the output of the equalizer in the recording data to be decoded, and newly added to the Viterbi decoder. It shows the relationship between the supplied equalizer output and the value of data for one clock to be newly decoded corresponding to the equalizer output.

Further, in this case, since a state transition occurs irrespective of the state one clock before and the reproduction signal value, it can be divided into an odd series and an even series, and each series is shown in FIGS. 5A and 5B. It can be seen that they follow the state transition diagram of the quaternary and two states shown respectively. Accordingly, by arranging two 4-level 2-state Viterbi decoders that perform decoding based on a 4-level 2-state state transition diagram, a Viterbi decoder that performs PR4ML by performing two-parallel processing can be configured. . Further, in FIG. 5A and FIG.
= C11 = 0, C01 = + 1, C10 = -1, so in an actual configuration, a ternary 2-state Viterbi decoder may be used instead of a 4-level 2-state Viterbi decoder. However, the following description is based on the premise that two quaternary two-state Viterbi decoders are arranged to perform parallel processing in order to maintain generality.

Generally, PRML is based on a state transition diagram corresponding to a partial response characteristic in an equalizer, and calculates a state transition sequence having the highest possibility (likelihood) that actually occurred by a calculation process based on a reproduced signal. This is a decoding method for performing decoding by selecting. A Viterbi decoder that realizes PRML has a branch metric calculation circuit (hereinafter, referred to as BMC) that calculates a value of a branch metric described later based on an amplitude reference level and an actual equalizer output. Further, an addition / comparison / selection circuit (hereinafter, referred to as ACS) that selects the most likely transition by performing a predetermined operation as described later based on the value of the branch metric.
). Further, it has a path memory circuit (hereinafter, referred to as PMU) for generating decoded data as a maximum likelihood decoded sequence based on the result of the selection performed by the addition / comparison / selection circuit.

FIG. 6 shows an example of a configuration in which two quaternary two-state Viterbi decoders are arranged to perform parallel processing. Here, BMC2
2, the ACS 24 and the PMU 28 decode an even number sequence, for example, and the BMC 23, the ACS 25 and the PMU 29 decode an odd number sequence, for example. B
The MC 22 is supplied with, for example, a reproduction signal value Z_0 of an even-number sequence, calculates a value of a branch metric described later based on Z_0, and supplies the calculated value to the ACS 24.

The ACS 24 selects a state transition with a higher likelihood (likely) based on the output of the BMC 22,
The selection signals SEL0 and SEL1 are set to P in accordance with the selection result.
Supply to MU28. PMU 28 has SEL0 and S
The operation according to EL1 is performed, and SEL0 and the signal obtained by inverting SEL1 by the inverting circuit 26 are received as initial values. On the other hand, BMC23, ACS25, PMU
29 and the inverting circuit 27, respectively.
22, ACS 24, PMU 28 and inverting circuit 26, respectively.

The BMCs 22 and 23 and the ACS 24
And 25 and the components used as PMUs 28 and 29 will be described in more detail. First, B
The MC will be described with reference to FIG. The BMC has four branch metrics BMij (i = 0,
1, j = 0, 1) is calculated. BMij corresponds to the Euclidean distance between the latest equalizer output Z and the amplitude reference level Cij.

BM00 = (Z−C00) ² (16) BM01 = (Z−C01) ² (17) BM10 = (Z−C10) ² (18) BM11 = (Z−C11) ² (19) Amplitude reference level For C00 to C11, a fixed value determined in consideration of the signal quality of the reproduction signal and the like may be used. In recent years, however, it has been difficult to make the amplitude reference level follow fluctuations due to the amplitude, offset, and the like of the reproduction signal. Done. Such control is also called adaptation of the amplitude reference level. Such control is performed by, for example, updating a new amplitude reference level as a weighted average of an initial value preset as an amplitude reference level and a reproduced signal value, for example, every clock. The present invention can be applied to a case where such an amplitude reference level is controlled.

In FIG. 7, subtraction circuits 30, 40, 50
And 60 are supplied with an equalizer output Z (Z_0 or Z_1 in FIG. 6). Then, the subtraction circuits 30, 4
0, 50 and 60 are the amplitude reference levels C0
A subtraction value is calculated by subtracting 0, C01, and C10 from the equalizer output Z, and the subtraction value is stored in registers 31 and 4 in the subsequent stage.
1, 51 and 61 respectively. Register 3
1, 41, 51 and 61 calculate the supplied subtraction value at the timing according to the clock,
2, 42, 52 and 62. Square calculation circuit 3
2, 42, 52, and 62 calculate the square of the supplied subtraction value, and respectively perform BM00, BM01, and BM.
10 and BM11 are calculated.

Then, BM00, BM01, BM10 and BM11 are supplied to registers 33, 43, 53 and 63 at the subsequent stage, respectively. The registers 31, 41, 51, and 61 store the BM00,
BM01, BM10 and BM11 are output. In the above processing, the equalizer output Z and the amplitude reference level C
00 to C11, subtraction values Z-C00 to Z-C11, and branch metrics BM00 to BM11 are treated as, for example, 8-bit data.

Next, the ACS will be described with reference to FIG. The ACS adds the path metrics MT0 and MT1 respectively corresponding to the states S0 and S1 and the above-described branch metric according to the following equations (15) to (18) according to the following equations (15) to (18). MM
ij (i = 0, 1, j = 0, 1) is calculated.

MM00 = BM00 + MT0 (20) MM01 = BM01 + MT0 (21) MM10 = BM10 + MT1 (22) MM11 = BM11 + MT1 (23) Here, each MMij represents the likelihood (likelihood) of the transition from the state Si to the state Sj. Value. In FIG. 8, the addition circuits 70, 71, 72 and 7
3 are supplied with BM00, BM10, BM01 and BM00, respectively. As will be described later, MT0 is supplied to the adders 70 and 71, while MT1 is supplied to the adders 72 and 73. Then, the adders 70, 71, 72 and 73 respectively calculate the equation (2)
0) to (23), the addition values MM00 to MM11 are calculated.

Further, the magnitude comparison processing of MM0j and MM1j is performed as shown in the following equations (24) and (25).

SEL0 = MM00> MM10 (24) SEL1 = MM01> MM11 (25) Among them, the expression (24) corresponds to j = 0. M
If M00 is greater than MM10 and the inequality on the right is true, the likelihood of the transition S1 → S0 is
Since the likelihood is higher than 0 → S0, the transition S1 → S0 is selected. That is, SEL0 = '1' is the transition S1
→ Corresponds to selection of S0. Conversely, SE
When L0 = '0', the transition S0 → S0 is selected. j
Equation (25) corresponding to = 1 can be considered in the same way, and SEL1 = '1' corresponds to the selection of the transition S1 → S1, and if SEL1 = '0', the transition S0 → S1 is selected.

In FIG. 8, MM00 and MM10 are supplied to a comparison circuit 74, and the comparison circuit 74 performs a process according to equation (24) and outputs SEL0. On the other hand, MM01
And MM11 are supplied to the comparison circuit 75, and the comparison circuit 75
Performs the processing according to equation (25) and outputs SEL1.
SEL0 and SEL1 are connected to the path memory circuit 17 in the subsequent stage.
And to the selection circuits 76 and 77, respectively. The selection circuits 76 and 77 perform processing according to the following equations (26) and (27).

MT0 = MM00 ×! SEL0 + MM10 × SEL0 (26) MT1 = MM01 ×! SEL1 + MM11 × SEL1 (27) That is, the selection circuit 76 updates the value of MT0 by using MMi0 determined to have a higher likelihood as a new path metric MT0 based on SEL0. Further, the selection circuit 77 converts the MMi1 determined to have a higher likelihood based on SEL1 into a new path metric MT.
The value of MT1 is updated by setting it to 1.

The updated values of MT0 and MT1 are supplied to storage circuits 78 and 79, respectively. Storage circuit 78,
79 temporarily holds the value to be supplied, and further, at timings according to the clock, adders 70 and 71, respectively.
The signals are supplied to adders 72 and 73. Adder circuits 70 to 7
3 calculates the supplied value by the equation (20) to (2) with respect to the value of the branch metric supplied in the subsequent clock.
Used in the calculation of 3).

By the way, in order to correctly perform the magnitude comparison between the added values by the equations (24) and (25), the added value M
When calculating the values of M00 to MM11, it is not always necessary to use the values of the path metrics MT0 and MT1 themselves, and the difference between the values of MT0 and MT1 is the sum MM00.
It suffices if it is correctly reflected on the values of MM11. For this reason,
Instead of MT0 and MT1 in Equations (20) to (23), for example, a value obtained by subtracting a common value from MT0 and MT1 may be used. In this way, ACS
Can be reduced, the number of bits of components in the ACS can be reduced, and
Circuit configuration can be reduced.

As described above, actually, C00 = C11
= 0, three types of amplitude reference levels may be used,
A ternary two-state Viterbi decoder may be used. In this case, since Equations (16) and (19) calculate exactly the same value, BMC calculates only three types of branch metric values according to Equations (16), (17), and (18). What is necessary is just to comprise. Further, since BM11 = BM00, the ACS is calculated by the following equation (2) instead of the equation (23).
3) 'should be calculated.

MM11 = BM11 + MT1 (2
3) 'As described above, it is sufficient that the BMC calculates the values of three types of branch metrics, and only three types of branch metrics are handled in ACS. Therefore, in a ternary two-state Viterbi decoder, There is an advantage that the circuit configuration is simplified.

Next, the PMU will be described with reference to FIG. According to the outputs of SEL0 and SEL1, the PMU determines the path PM0 [k] that reaches the state S0 by the latest transition as shown in the following equations (28) and (29).
And the path PM1 [k] reaching the state S1 by the latest transition
And generate As described later, in FIG. 9, PM0 [k]
The configuration for generating PM1 [k] is shown in the upper part, and the configuration for generating PM1 [k] is shown in the lower part. Further, the number of memory stages is set to N.

PM0 [k] = PM0 [k−1] ×! SEL0 + PM1 [k-1] × SEL0 (where k = 1, 2,... N) (28) PM1 [k] = PM0 [k-1] ×! SEL1 + PM1 [k-1] × SEL1 (where k = 1, 2,..., N) (29) According to equation (28), for PM0 [k], at time k, SEL0 is “1”. At this time, parallel loading, that is, processing of loading the path of PM1 up to time point k-1 in parallel to PM0 is performed. When SEL0 = '0', the serial shift, that is, the process of shifting the path up to time point k-1 by one and holding it is performed. On the other hand, with respect to PM1, SEL1 becomes '1' at time k in accordance with equation (29).
, Serial load is performed and SEL1 is '0'
At the time of parallel loading.

[0062] In FIG. 9 generates the PM0 configuration, the register _{81 1, 81 2 ··· 81 N} -1, the selector 81
_1, 81 and ₂ · · · 81 _N-1 are alternately arranged, further comprising disposed selectors 81 _N-1 of the subsequent stage in the register 81 _N includes a shift register of total N stages. Similarly, the configuration for generating PM1 is based on the registers 83 ₁ and 83 ₂
.. 83 _N-1 and selectors 84 ₁ , 84 _2.
And _N-1 are alternately arranged, furthermore, formed by the register 83 _N is arranged downstream of the selector 84 _N-1, including a shift register of the total N stages. Then, the selectors 81 ₁ , 81
₂ ··· 81 _N-1 to the selection signal SEL0 is supplied, also, the selector _{84 1, 84 2 ··· 84 N} -1 to the selection signal SEL1 is supplied. Serial shift or parallel load is performed according to these selection signals.

The first-stage registers 81 ₁ and 83 ₁
Are supplied with initial values INIT0 and INIT1, respectively. As these initial values, appropriate signals are externally supplied as follows according to the state transition diagram shown in FIG. 5A or 5B (see FIG. 6). First, PM0
The initial value supplied to the first stage of the register 81 ₁ in the configuration for generating be described. When S0 → S0 is selected among the transitions to the state S0, SEL0 = '0' from the above equation (24). In addition, from the state transition diagram of FIG. 4, the decoded value at this time is '0'. When S1 → S0 is selected, SEL0 = “1” from the above equation (24).
It is. In addition, from the state transition diagram of FIG. 4, the decoded value at this time is “1”. Therefore, since the latest decoded value always matches SEL0, SEL0 may be supplied to the register 81 ₁ as the initial value INIT0.

Next, a description will be given initial value supplied to the first stage of the register 83 ₁ in the configuration for generating the PM1. When S0 → S1 is selected from among the transitions to the state S1, SEL0 = '0' from the above equation (25). In addition, from the state transition diagram of FIG. 4, the decoded value at this time is “1”. When S1 → S0 is selected, the above equation (2)
From 5), SEL0 = '1'. In addition, from the state transition diagram of FIG. 4, the decoded value at this time is '0'. Therefore, the latest decoded value is always the value obtained by inverting SEL1.
A signal obtained by inverting the L1 may be supplied as an initial value INIT1 to register 84 _1. As described above,
Signals as shown in FIG. 6 are set as initial values INIT0 and INIT1.

The present invention negates based on the concept behind the configuration of the commonly used Viterbi decoder as described above, and declares a NRZI precoded D1 digital VTR. And DIR-format data recorders also use interleaved NRZI
As simple as the pre-coded system of
An object of the present invention is to provide a Viterbi decoder capable of high-speed operation.

The concept for reaching the present invention will be described from two viewpoints. First, according to the Viterbi decoding method, an identification result is determined (that is, maximum likelihood decoding is performed) as a result of a state transition without inconsistency by the above-described processing based on a reproduced signal. For this reason, when the Viterbi decoding method is used, no error propagation occurs even if precoding is not performed.

The idea that error propagation will occur at the time of decoding unless precoding (for example, as described above, precoding based on interleaved NRZI for PR4) according to the partial response characteristic is based on a bit-by-bit multi-valued threshold value It is only a remnant of the era where identification (for example, realized by a recording / reproducing system as described above with reference to FIG. 3) was assumed. Any Viterbi decoder that decodes the actually recorded data sequence b [k] can be configured irrespective of the partial response characteristics used in the equalizer. If this concept is not correct, PR (1,2,1), PR (1,1,1,1), PR (1,2,1) according to the characteristics of the recording / reproducing system as shown below.
(1,1, -1, -1) and PR (1,2,0,-
By using 2, 1), etc., various research presentations and results based on the comparative studies will not be realized.

[1] Osawa, Okada, Wakamiya, Okamoto "(1,
7) Improvement of error characteristics of PRML system for RLL code ", MR94-62 (1994) [2] Osawa, Okada, Okamoto, Saito" (1, 7) Performance comparison of various PRML systems for RLL code and 8/9 code, M
R95-61 (1994) [3] T. Nakahara, K. Arai, A, Fukumoto, S. Masuhara, "Par
tial-Response Maximum-Likelihood Detection Method
for Magneto-Optical Recording "Jpn.J.App
l. Phys. Vol. 36 (1997) pp. 549
−556 (1997) As a second viewpoint, the reason that the odd sequence and the even sequence become independent in PR4 is not due to the precoding of the interleaved NRZI, but to PR (1,0,
It should be noted that this is the property of the equalization characteristic of -1). When precoding is not performed, PR (1,0,
FIG. 10 shows a state transition diagram of four values and four states under -1). Again, since the input a [k-1] one clock before does not affect the output c [k], independent state transitions as shown in FIGS. 11A and 11B are performed for each of the odd series and the even series. Decoding can be performed according to the figure.

Here, the state transition diagrams shown in FIGS. 10 and 11 are not based on the precoding based on the interleaved NRZI, so that the state transition diagrams shown in FIG. 4 and FIG. The relationship with the decoded value is different.

FIG. 12 shows an example of a specific configuration for performing parallel processing in accordance with the state transition diagrams for the odd-numbered sequence and the even-numbered sequence shown in FIGS. 11A and 11A, respectively. Here, as BMCs 86 and 87, BMC22 in FIG.
The same thing as 23 can be used. AC
As S88 and 89, those similar to the BMCs 24 and 25 in FIG. 6 can be used. In addition, PMU9
As 0 and 91, those similar to the PMUs 28 and 29 in FIG. 6 can be used.

According to the state transition diagrams shown in FIGS. 11A and 11B, the transition to the state S0, S0 →
In both S0 and S1 → S0, the decoded value is “0”
It is. On the other hand, S0 → S1 is a transition to state S1.
In both of S1 and S1 → S1, the decoded value is “1”. Therefore, the initial value supplied to the first-stage register in the configuration for generating PM0 is always set to '0'.
The initial value supplied to the first-stage register in the configuration for generating may be always '1'.

The configuration shown in FIG. 6 is a state transition diagram (FIG. 4) showing the relationship between data a [k] to be recorded before precoding by interleaved NRZI and possible state transitions. And FIG. 5). Therefore, the final stage register 81
PM0 and PM1 output from _N and 83 _N are
If there is no decoding error, the result matches a [k].

On the other hand, of the configuration shown in FIG.
The configuration before the PMUs 90 and 91 is a state transition diagram showing the relationship between a [k] as data recorded on the recording medium and possible state transitions without considering the precode (FIGS. 10 and 11). Reference). Therefore, DET_0 and DET_1 output from the registers at the last stage of PMUs 90 and 91
Is an intermediate sequence pre-coded by NRZI or the like, for example.

Therefore, after the PMUs 90 and 91,
It is necessary to add a configuration for performing decoding corresponding to the precode. In FIG. 12, a register 92 and exclusive OR circuits 93 and 94 are configured to perform decoding corresponding to precoding by NRZI. That is, DET_
0 is supplied to exclusive OR circuits 93 and 94. DET_1 is supplied to the exclusive OR circuit 93 and the register 92. The register 92 operates at a timing according to the clock signal, and supplies the supplied data to the exclusive OR circuit 94 with a delay of one clock. With this configuration, the processing according to the following equations (30) and (31) is performed, whereby the exclusive OR circuits 93 and 9 are performed.
4 are reproduced data DEC_0 [k] and DEC_1 [k], respectively.

DEC_0 [k] = DET_0 [k] + DET_0 [k−1] (30) DEC_1 [k] = DET_0 [k] + DET_0 [k] (31) An example of verification of the validity and effect of the present invention will be described below. Will be described. Betacam SX (Sony DNW-450)
And reproduces signal data by recording and reproducing pseudo random data having a cycle of 2048 bits at 60 to 85 Mbps. This reproduction signal data is pre-equalized by an analog equalizer and supplied to a PLL to extract a synchronous clock.

Further, the above-mentioned reproduction signal data is A / D-converted by a digital oscilloscope (LeCroy LC534M) connected so as to operate using the synchronous clock as a sampling clock, and the data obtained as a result of the A / D conversion is digitally converted.・ Load to the internal memory of the oscilloscope. Then, GPIB (G
Simulation was performed by transferring data to a work station (Sony NWS-5000TF) via an eneral purpose interface bus).

Here, the relationship between the recording data rate and the shortest recording wavelength is as follows.

Recording Rate (Mbps) 60 65 70 75 80 85 Shortest Recording Wavelength (μm) 0.64 0.59 0.55 0.51 0.48 0.45 FIG. 13 shows the simulation results, with the horizontal axis representing the recording data rate and the vertical axis representing the bit error rate. .
LMS (Least Mean Square) equalizes to Nyquist's first standard with a 15-tap transversal filter whose tap coefficient is determined by an algorithm, performs binary identification on the equalized signal, and decodes NRZI based on the identification result. The result obtained is PR (1) _BF1 shown by a black square and a solid line.

Next, the 1-D ² partial response is calculated, equalized under the equalization characteristic of PR4, ternary identification is performed on the equalized signal, and NRZI decoding based on the identification result is performed. The result obtained is PR (1,0, -1) _BF1 indicated by a circle and a dotted line.

Further, the results obtained when the Viterbi decoder according to the embodiment of the present invention described above with reference to FIG. 12 and the like are used are represented by PR (1,0,
-1) _VF1.

After performing ternary identification, PR (1,0, −1) _B obtained by decoding NRZI based on the identification result
In F1, since error propagation occurs, P
In some cases, the error rate is higher than R (1) _BF1. However, when decoding is performed using the Viterbi decoder according to the embodiment of the present invention (ie, PR
The error rate of (1,0, -1) _VF1) is PR
The error rate is about 1/10 of (1, 0, -1) _BF1. As described above, the validity and effect of the present invention could be confirmed.

[0082]

As described above, the present invention provides an NRZI
Is reproduced as follows. That is, two Viterbi decoders having the same configuration are provided in parallel, the reproduced signal is equalized under equalization characteristics such as PR4, and the equalized signal is divided into an even-numbered sequence and an odd-numbered sequence. Is supplied to two Viterbi decoders, and further, using the outputs of these two Viterbi decoders, decoding corresponding to the precoding by NRZI is performed to reproduce user data and the like.

For this reason, application of the Viterbi decoder is not considered at the time of determining the recording format, and the NRZI code is used as the recording modulation code.
For a digital VTR such as a 1-system VTR or a DIR data recorder, a reproduction system can be configured using a two-parallel Viterbi decoder using PR4 equalization. Therefore, for example, as described above with reference to FIG. 13 and the like, the reliability of these recording and reproducing devices can be improved.

In addition, since the two-parallel Viterbi decoder using PR4 equalization can be applied, it is possible to realize a format extension with upward compatibility at low cost while maintaining reliability.

Further, since there are many parts that can use the components of an existing Viterbi decoder used when an interleaved NRZI code is used as a recording modulation code, it can be easily applied to an actual device. .

[Brief description of the drawings]

FIG. 1 is a schematic diagram for explaining an Nyquist equalization characteristic based on a first reference.

FIG. 2 is a schematic diagram for explaining an equalization characteristic of PR4.

FIG. 3 is a schematic diagram for explaining a recording / reproducing apparatus for performing precoding of interleaved NRZI.

FIG. 4 is a schematic diagram for explaining a PR4ML state transition diagram when an interleaved NRZI precoding is performed.

FIG. 5 is a schematic diagram for explaining a PR4ML two-parallel state transition diagram when interleaved NRZI precoding is performed.

FIG. 6 is a block diagram for describing PR4ML two-parallel processing on the premise of an interleaved NRZI precode.

FIG. 7 is a block diagram illustrating an example of a configuration of a BMC.

FIG. 8 is a block diagram illustrating an example of an ACS configuration.

FIG. 9 is a block diagram illustrating an example of a configuration of a PMU.

FIG. 10 is a schematic diagram illustrating a state transition diagram of PR4ML when precoding is not performed.

FIG. 11 is a schematic diagram for explaining a PR4ML two-parallel state transition diagram when precoding is not performed;

FIG. 12 shows a case where P is not precoded.
It is a block diagram for demonstrating R4ML two parallel processing.

FIG. 13 is a schematic diagram for explaining the validity and effect of the present invention.

[Explanation of symbols]

86, 88: BMC, 88, 89: ACS, 9
0, 91: PMU, 92: Register, 93, 9
4 Exclusive OR circuit

Claims (8)

[Claims] 1. A digital information reproducing apparatus for reproducing recorded data based on a reproduced signal reproduced from a recording medium, comprising: a first Viterbi decoder having the same configuration using an NRZI code as a recording modulation code; Two Viterbi decoders in parallel, equalize the reproduced signal under predetermined equalization characteristics, divide the equalized signal into an even-numbered sequence and an odd-numbered sequence, each of which is divided into the first Viterbi decoder and the second A second Viterbi decoder for decoding the NRZI code based on the output of the first Viterbi decoder and the output of the second Viterbi decoder. 2. The method according to claim 1, wherein the first Viterbi decoder and the second Viterbi decoder perform calculations for separately referring to four amplitude reference levels based on the equalized reproduced signal. A branch metric calculation circuit for calculating four branch metric values, and means for storing two path metric values equal to the number of states, wherein the first one of the four branch metric values is And the first path metric value of the two path metric values is added to calculate a first addition value, and the first branch metric value of the four branch metric values is calculated. The value of the second branch metric and the value of the first path metric among the values of the two path metrics are added to calculate a second addition value, and the value of the four branch metrics is calculated. Third in A third added value is calculated by adding the value of the branch metric and the value of the second path metric of the two path metric values, and calculating the third added value of the four branch metric values. 4 and the value of the second path metric of the two path metric values are added to calculate a fourth added value. The first added value and the second And generates a first selection signal based on the comparison result, and selects one of the first addition value and the second addition value based on the comparison result. Then, the value of the first path metric is updated by using the new value of the first path metric, the third added value is compared with the fourth added value, and the third added value is compared with the fourth added value. 2 is generated, and based on the comparison result, the second An addition value / comparison / selection circuit that updates one of the values of the second path metric by selecting one of the addition value of 3 and the fourth addition value to obtain a new value of the second path metric. And a path memory circuit for updating a path as a series of decoded values according to the first selection signal and the second selection signal. 3. The digital information reproducing apparatus according to claim 1, wherein the predetermined equalization characteristic is PR4. 4. The method according to claim 3, wherein the first Viterbi decoder and the second Viterbi decoder perform a calculation that individually refers to three amplitude reference levels based on the PR4 equalized reproduction signal. A branch metric calculation circuit for calculating three branch metric values; and means for storing two path metric values equal to the number of states. 1 and the value of the first path metric among the values of the two path metrics are added to calculate a first addition value, and the value of the three branch metrics is calculated. And the first path metric value of the two path metric values is added to calculate a first addition value, and the three branch metric values are calculated. Within The third branch metric value and the value of the second path metric of the two path metric values are added to calculate a third added value, and the value of the three branch metric values is calculated. Are added to the value of the first branch metric and the value of the second path metric among the values of the two path metrics to calculate a fourth added value. The second addition value is compared, a first selection signal is generated based on the comparison result, and the first addition value and the second addition value are calculated based on the comparison result. The value of the first path metric is updated by selecting one of them and setting it as a new value of the first path metric. The third added value is compared with the fourth added value, and the comparison result is obtained. A second selection signal is generated based on the comparison result, and based on the comparison result, Adding one of the third added value and the fourth added value to obtain a new second path metric value to thereby update the value of the second path metric; A digital information reproducing apparatus comprising: a selection circuit; and a path memory circuit that updates a path as a series of decoded values according to the first selection signal and the second selection signal. 5. The decoding of the NRZI code according to claim 1, wherein the output of the first Viterbi decoder at a time point k and the output of the second Viterbi decoder at a time point k are converted into a remainder system of 2. A digital information reproducing apparatus characterized in that the digital information reproducing apparatus performs the processing by adding and subtracting. 6. The decoding of the NRZI code according to claim 1, wherein the output of the first Viterbi decoder at a time point k and the output of the second Viterbi decoder at a time point k−1 are two remainders. A digital information reproducing apparatus characterized by performing the addition by a system. 7. The method according to claim 1, wherein the first Viterbi decoder and the second Viterbi decoder are configured such that each branch metric referred to in calculation of a branch metric follows the amplitude of a reproduced signal. A digital information reproducing apparatus. 8. A digital information recording / reproducing system for recording / reproducing digital information, a recording / modulation code generating means for converting data to be recorded into an NRZI code, a recording / reproducing means for recording / reproducing the NRZI code, Equalizing means for PR4 equalizing a reproduced signal supplied from the reproducing means, a first Viterbi decoder and a second Viterbi decoder having the same configuration are provided in parallel, and the reproduced signal is provided with a predetermined equalization characteristic. , And divides the equalized signal into an even-numbered sequence and an odd-numbered sequence.
And the second Viterbi decoder and decodes the NRZI code based on the output of the first Viterbi decoder and the output of the second Viterbi decoder. Digital information recording and reproduction system.