JPH11282416A - Driving circuit for plasma display panel, driving method thereof, and plasma display panel device - Google Patents

Abstract

(57) [Summary] PDP is an aggregate of many cells. When the cells are discharged all at once during the sustain period, the instantaneous current flowing through the bus electrode and the circuit common to each cell becomes very large even though the discharge current of each cell is small. Therefore, the loss due to the resistance drop of the mother electrode and the circuit impedance increases, and the voltage drop causes a decrease in margin. When the discharge current flowing in one cell is considered, if the peak current is large, the ultraviolet light for exciting the phosphor is saturated with the current, so that the luminous efficiency is reduced. SOLUTION: A first discharge for performing a first discharge during a half cycle is provided.
And a sustain pulse having a second voltage value for performing the second discharge.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AC plasma display panel (hereinafter, referred to as an AC-PDP), and more particularly, to a surface discharge AC-PDP driving circuit and a driving method thereof.

[0002]

2. Description of the Related Art Various studies have been made on PDPs as thin televisions or display monitors. Among them, one of the AC-PDPs having a memory function is a surface discharge type AC-PDP.
The structure of P will be described with reference to FIG.

FIG. 15 is a perspective view showing a structure of a conventional surface discharge type AC-PDP.
C-PDP is disclosed, for example, in Japanese Patent Application Laid-Open Nos. 7-140922 and 7-287548. In FIG. 15, a surface discharge type AC-PDP 101 is shown.
Includes a front glass substrate 102 serving as a display surface, and a rear glass substrate 103 facing the front glass substrate 102 with a discharge space interposed therebetween. Then, the front glass substrate 10
On the surface of the second discharge space side, n pairs of the first electrode 104 and the second electrode 105 are formed so as to extend n each. However, as shown in FIG. 15, when metal auxiliary electrodes (bus electrodes) 104a and 105a are provided on a part of the surface of the first and second electrodes 104 and 105, the metal electrodes are also included. Each of them is a “first electrode 104”,
It can also be called “second electrode 105”. In addition, the first,
The second electrodes 104 and 105 are connected to the row electrodes 104 and 10 respectively.
Also called 5. In the AC-PDP, a dielectric layer 106 is formed so as to cover both row electrodes 104 and 105. Further, as shown in FIG. 15, on the surface of the dielectric layer 106, a dielectric material made of MgO (magnesium oxide) is used.
The film 107 may be formed by a method such as an evaporation method. In this case, the dielectric layer 106 and the MgO film 107 are collectively referred to as a “dielectric layer 106A”.

On the other hand, m third electrodes 108 (hereinafter referred to as “column electrodes 1”)
08 ”) is formed to extend so as to be orthogonal to the row electrodes 104 and 105, and between adjacent column electrodes 108.
The partition 110 is formed to extend in parallel with the column electrode 108. The partition wall 110 serves to separate the discharge cells and also serves as a support for supporting the PDP so as not to be crushed by the atmospheric pressure. The red, green, and red colors are respectively formed on the surface of each column electrode 108 and the side wall surface of the partition 110.
The phosphor layers 109 that emit blue light are provided in a stripe pattern in order.

[0005] The front glass substrate 102 having the above structure
And the rear glass substrate 103 are sealed to each other, and a discharge gas such as a Ne-Xe mixed gas or a He-Xe mixed gas is sealed in a space between the two glass substrates 102 and 103 at a pressure lower than the atmospheric pressure. I have. In the surface discharge type AC-PDP having such a structure, the row electrodes 10
The discharge space defined by 4, 105 and the column electrode 108 becomes one discharge cell of the PDP, that is, a pixel.

Next, a specific driving method of the conventional PDP will be described with reference to FIGS. FIG. 16 is a diagram schematically showing a configuration of a driving portion of the plasma display device 50. PD of the plasma display device 50
As P, a PDP having the structure shown in FIG. 15 is used. That is, P
The DP 10 is disposed along the display line direction (first direction), at least one of which is a dielectric (the dielectric layer 1 in FIG. 15).
06 or 106A) (FIG. 1)
5 corresponds to the first electrode 104. Hereinafter, a plurality of display electrode pairs each including a “X electrode” and a second electrode (corresponding to the second electrode 105 in FIG. 15; hereinafter, referred to as a “Y electrode”) are provided.

As shown in FIG. 16, a PDP 10 has n number of X electrodes Xi (a numeral i (i: 1 to 1) following a reference numeral “X”).
n), hereinafter also referred to as “X electrodes Xi”) are formed in parallel with each other. N Y electrodes Yi paired with this X electrode Xi (the notation method is X electrode X
i, hereinafter also referred to as “Y electrode Yi”) is formed adjacent to and parallel to the X electrode Xi. That is,
The X electrode Xi and the Y electrode Yi form a display electrode pair Xi, Yi of the first block. Then, the X electrode Xi or the Y electrode Yi
Is connected to a drive circuit 14 or a Y electrode driver circuit 15 for applying a predetermined signal (potential) to each of the electrodes Xi and Yi. X drive circuit 14
It comprises an electrode driver circuit 141 and a drive IC 142.

The column electrodes W are parallel to each other along a direction (second direction) orthogonal to the direction in which the display electrode pairs X and Y are arranged.
1 to Wm (hereinafter also collectively referred to as “W electrode”) are sequentially formed, and one end of each W electrode is connected to the drive circuit 18. The drive circuit 18 includes a W driver 181 and a drive IC 182.

The driving circuit 14, the Y electrode driver circuit 15,
The drive circuit 18 is connected to a power supply circuit 41, and power is supplied from the power supply circuit 41. Each drive circuit operates by inputting a control signal from the control circuit 40.

As one of the driving methods for the AC-PDP, there is a driving method disclosed in, for example, JP-A-7-160218. FIG. 17 shows one of the driving methods.
FIG. 7 is a timing chart showing a driving waveform in a subfield period. In the following description, n Xs in FIG.
The electrodes are called “row electrodes Xi” (i: 1 to n), and n Y electrodes
The electrodes are driven by a single drive signal, and the n electrodes are collectively referred to as “row electrodes Y”. The m W electrodes are referred to as “column electrodes Wj” (j: 1 to m).

The subfield (SF) shown in FIG.
One of the frames (F) for displaying an image is divided into a plurality of periods. In this case, the subfield is further divided into a “reset period”, an “address period”, and a “sustain discharge period (display period)”. Is divided into three.

First, in the "reset period", the display history at the end of the immediately preceding subfield is erased, and priming particles for increasing the discharge probability in the subsequent address period are supplied. Specifically, the display history is erased by applying a full write pulse of a voltage value that can cause a self-erasing discharge described later at the time of its fall between all the row electrodes Xn and the row electrodes Y.

Next, in the "address period", only the cells to be selected and displayed in the matrix are selectively discharged by the operation of the drive IC 142 for the X electrode and the drive IC 182 for the W electrode, and writing is performed on the cells. . Specifically, as shown in FIG. 17, first, a scan pulse Vxg is sequentially applied to the row electrode Xi under the control of the IC 142, and in a cell to be turned on, a scan pulse is applied between the column electrode Wj and the row electrode Xi. An address discharge, which is a write discharge, is generated. At this time, a sub-scanning pulse Vysc is applied to the row electrode Y. Vxg + Vys is applied to the row electrodes Xi and Y.
A potential difference of c will be applied. This potential difference is a potential difference in which discharge does not start by itself, but discharge (transition) occurs immediately between the row electrodes Xi and Y triggered by the previous address discharge. Thus, on the surface of the dielectric layer 106A (see FIG. 15) of the cell, an amount of positive or negative charge capable of performing a sustain discharge only by applying a sustain pulse later is accumulated.

On the other hand, in the cell in the unlit state, no address discharge is caused, so that no write sustain discharge occurs between the row electrodes Xi and Y of the cell, and no charge is accumulated.

When the address period ends, a sustain discharge period starts. In the sustain discharge period, the driving IC of the electrode X is not controlled, and in this period, the voltage is applied to the electrode X only by the X driver 141. By applying a sustain pulse between the row electrodes Xi and Y, the sustain discharge of the written cell is continued during the sustain discharge period. Note that the potential of the column electrode Wj during the sustain discharge period is set to about Vs / 2 when the voltage value of the sustain pulse between the row electrodes Xi and Y is Vs. This is a driving method for enabling sustain discharge to start stably at the time of transition from the address period to the sustain discharge period.

Here, the operation during the sustain discharge period will be described in detail with reference to FIG. First, the row electrodes 104, 10
A discharge is generated by applying a sustain voltage pulse between the five. The ultraviolet light generated by this discharge is applied to the phosphor layer 1 of FIG.
By exciting 09, the discharge cells emit light. During this discharge, the electrons and ions generated in the discharge space
Row electrodes 104, 1 having polarities opposite to the respective polarities
05 and accumulates on the surface of the dielectric layer 106A on the row electrodes 104 and 105. The charges such as electrons and ions accumulated on the surface of the dielectric layer 106A in this manner are called "wall charges". Since the amount of the wall charge depends on the externally applied voltage value, the potential formed by the wall charge cannot be higher than the externally applied voltage.

Since the electric field formed by the wall charges acts in a direction to weaken the applied electric field, the discharge rapidly disappears with the formation of the wall charges. When a voltage pulse of which polarity is reversed is applied between the row electrodes 104 and 105 after the discharge has disappeared, an electric field in which the applied electric field and the electric field due to the wall charges are superimposed is substantially applied to the discharge space. Therefore, a discharge can be caused again. As described above, once a discharge occurs, a discharge can be generated by applying an applied voltage (hereinafter referred to as a “sustain voltage”) lower than the voltage at the start of the discharge. , A discharge can be constantly maintained by applying a sustain voltage pulse (hereinafter, also referred to as a “sustain pulse”) whose polarity is sequentially inverted. That is, the sustain discharge continues.

According to the above-described operation principle, it can be said that the effective voltage is mainly the externally applied voltage, and the wall charge works as an auxiliary to the discharge at the rise of the applied pulse. Therefore, this discharge is referred to as “discharge mainly composed of an externally applied voltage”.

On the other hand, when the externally applied voltage is very high, the wall charges may form a potential higher than the discharge starting voltage. In this case, at the time of falling of the applied pulse, discharge may occur only by the wall charges. in this way,
The discharge that occurs when no voltage is applied from the outside is called "self-erasing discharge". Since the effective voltage of such a discharge is mainly composed of wall charges, it is referred to as “discharge mainly composed of wall charges”. In addition, at the time of discharging mainly by wall charges, an externally applied voltage may be applied in a direction in which the discharging becomes larger, so that
Here, including the case where an external voltage is applied,
The term “discharge mainly composed of wall charges” will be defined.

The prior art constituted by "discharge mainly composed of an externally applied voltage" is disclosed in JP-A-9-62225 and JP-A-8-278.
Although many are disclosed, such as 766, there are no many techniques for actively utilizing “discharge mainly composed of wall charges”. Slightly, Japanese Patent Application Laid-Open No. 8-314405, the invention of the prior application by the present inventors, and Japanese Patent Application No. 9-2714.
At 58, a driving method for positively generating "mainly wall-charged discharge" is shown.

(Reactive Power Recovery Circuit) Since the AC-PDP is a capacitive load, when charging / discharging the PDP, the reactive power (in proportion to the square of the voltage value of the driving voltage pulse and the capacitance component of the panel). Power that does not contribute to discharge or light emission)
Occurs. Therefore, since the capacitive load of the panel increases with an increase in the panel size of the PDP, the reactive power in the total power consumption becomes so large that it cannot be ignored.

Therefore, a technique for recovering the reactive power is disclosed in, for example, Japanese Patent Application Laid-Open No. 8-152865 and Japanese Patent Publication No. 56-30730. FIG. 18 is a diagram showing a driving circuit of a plasma display device having a reactive power recovery circuit (hereinafter also referred to as a “recovery circuit”) disclosed in the former publication. The drive circuit shown in FIG. 18 is a circuit that simulates the operation during the sustain discharge period. During this period, the drive IC 142 in FIG. 16 is in a conductive state, and the X electrodes are directly connected to the X driver. . Therefore, in terms of the circuit, the X electrode and the Y electrode are composed of the capacitance component CP.
In the sustain discharge period, the drive circuit including the reactive power recovery circuit is the circuit shown in FIG. That is, a PDP 201 having a capacitance component CP and a pulse generation circuit 200 having FETs 204 to 207 as switching elements are provided.
12, 213, the coil 208, the resistor 209, and the diodes 210, 211
It is connected in parallel with DP201 (accordingly, capacitance component CP). For this reason, the recovery circuit 202 is also called a parallel resonance type reactive power recovery circuit. In the plasma display device, the energy accumulated in the capacitance component CP after the discharge of the PDP 201 is once absorbed by the coil 208, and this energy is immediately recharged in a direction opposite to the polarity of the previous discharge for a subsequent discharge. FET2
04 to 207, 212, and 213 are drive-controlled. In this way, the plasma display device of FIG. 18 uses the recovery circuit 202 to recover and reuse the discharge energy of the capacitance component CP.

On the other hand, FIG.
FIG. 2 is a diagram showing a driving circuit of a plasma display device having a reactive power recovery circuit 302 disclosed in Japanese Patent No. 2798 and Japanese Patent Application Laid-Open No. 63-101897. As shown in FIG. 19, the plasma display device has a capacitance component CP.
And a pulse generation circuit having switches 304 to 307, and a recovery circuit 302 including switches 312 to 315, coils 308 and 309, and capacitors 310 and 311. As shown in FIG. 19, since the recovery circuit 302 is connected in series to both ends of the capacitance component CP (that is, PDP), it is also called a series resonance type reactive power recovery circuit. In the plasma display device, by appropriately controlling the switches 312 to 314, the energy stored in the capacitance component CP after the discharge is temporarily transferred to the capacitors 310 and 311 via the coils 308 and 309.
After the recovery, the capacity component CP is recharged at a predetermined timing using the energy.

The recovery circuit 302 of the series resonance type shown in FIG.
As compared with the parallel resonance type recovery circuit 202 of FIG. 18, the number of components is large and the component space is large, so the cost is high. On the other hand, since the driving method is to charge the capacitors 310 and 311 once with the discharge energy, There is an advantage that the degree of freedom in designing the drive voltage pulse (particularly, the application timing) is large, and therefore, the discharge can be easily controlled.

[0025]

(Brightness distribution) As described above, since the discharge mainly composed of an externally applied voltage is discharged by applying a predetermined potential, the discharge intensity is limited by the discharge voltage specific to the cell. Would. Therefore, there is a problem in that the cells having a low discharge start voltage have high luminance, and the cells having a high discharge start voltage have low luminance, causing display unevenness.

(Macro-Peak Current) A PDP is an aggregate of many cells. When the cells are discharged all at once during the sustain discharge period, the instantaneous current flowing through the bus electrode and the circuit common to each cell becomes very large even if the discharge current of each cell is small. Therefore, the loss due to the resistance drop of the mother electrode and the circuit impedance increases, and the voltage drop causes a decrease in margin.

In particular, in the case of driving only by a discharge mainly composed of an externally applied voltage, a cell corresponding to a cell having a high discharge starting voltage (difficult to discharge) is controlled by applying a voltage corresponding thereto. Discharge current flows. Therefore, the larger the firing voltage distribution of each cell in the panel is,
The loss due to the resistance drop of the mother electrode and the circuit impedance increases.

(Micro peak current) Even when considering the discharge current flowing through one cell, the smaller the discharge current, the better.
If the peak current is large, the ultraviolet light for exciting the phosphor is saturated with respect to the current, so that the luminous efficiency is reduced. Also in this case, when the discharge start voltage distribution of each cell in the panel is large, a voltage is set for a cell having a high discharge start voltage. In addition, the discharge itself has a large loss.

(Voltage Margin) Therefore, based on the above idea, the optimal discharge can be said to be a state where each cell is arranged with a minimum necessary discharge current. However, this means that the discharge is weakened, which may lead to a decrease in margin. In particular, at the beginning of the sustain discharge period, the space discharge is small and the discharge start voltage is high, and the discharge is hardly sustained. Further, considering that the display history is reset at the end of the sustain discharge period, a stable margin cannot be obtained with a weakened discharge.

(Circuit Configuration) Further, when a self-erasing discharge is induced using a parallel resonance type recovery circuit, there is a problem in the conventional circuit configuration itself. This is because in the parallel resonance type driving circuit, there is no pause between the pulses for maintaining a voltage suitable for the self-erase discharge mainly composed of wall charges, so that the self-erase discharge hardly occurs. In addition, when a voltage pulse is applied as an auxiliary to induce a discharge mainly composed of wall charges,
The above-described conventional parallel resonance type driving circuit alone is not possible, and a different power supply and switch must be used to generate a pulse for inducing.

Therefore, the present invention has been made based on the above-described concept, and has as its first object to provide a driving method which has a wider selection range of discharge and has no luminance unevenness.

It is a second object of the present invention to provide a driving method in which the peak of the current is reduced to reduce the loss due to the resistance of the mother electrode and the circuit impedance, that is, the discharge efficiency and the luminous efficiency are improved.

A third object of the present invention is to provide a driving method which does not impair the voltage margin even when the sustain discharge is weakened and the luminance distribution is reduced and the peak current is dispersed.

It is a fourth object of the present invention to provide an AC-PDP driving circuit in which a self-erasing discharge is easily generated by providing a pause between pulses even in a parallel resonance type reactive power recovery circuit.

It is a fifth object of the present invention to provide an AC-PDP drive circuit capable of forming a voltage pulse to be applied as a supplement in order to use a self-erasing discharge even better in a parallel resonance type reactive power recovery circuit. .

[0036]

According to a first aspect of the present invention, there is provided a method for driving a plasma display panel, wherein a first voltage value for performing a first discharge and a second discharge value for performing a first discharge during a half cycle. It is driven by a sustain pulse having a second voltage value.

According to a second aspect of the present invention, there is provided a driving method of a plasma display panel, wherein a sustain pulse is formed by switching between a voltage generated by a reactive power recovery circuit for recovering reactive power and a voltage from a power supply. is there.

According to a third aspect of the present invention, in the method for driving a plasma display panel, the reactive power recovery circuit is a parallel type reactive power recovery circuit connected in parallel to the interelectrode capacitance of the plasma display panel.

According to a fourth aspect of the present invention, in the driving method of the plasma display panel, the reactive power recovery circuit is a series type reactive power recovery circuit connected in series to the interelectrode capacitance of the plasma display panel.

A driving method of a plasma display panel according to a fifth aspect of the present invention includes a power supply having a plurality of different voltage outputs, and switching these plurality of different voltages to form a sustain pulse.

According to a sixth aspect of the present invention, in the driving method of the plasma display panel, the first discharge and the second discharge are mainly composed of an externally applied voltage, and the discharge timings of a plurality of cells are dispersed. Then, the first voltage value and the second voltage value are set.

According to a seventh aspect of the present invention, in the method of driving a plasma display panel, the second voltage value is equal to or higher than the minimum sustain voltage, and the first voltage value is equal to or lower than the discharge starting voltage.

In the driving method of a plasma display panel according to the present invention, the first discharge and the second discharge are a combination of a discharge mainly composed of an externally applied voltage and a discharge mainly composed of wall charges. The first voltage value and the second voltage value are set such that the same cell is dispersed in a plurality of discharges during the half cycle of the above.

According to a ninth aspect of the present invention, in the method for driving a plasma display panel, the second voltage value is set to be approximately 1/10 or less of the first voltage value.

According to a tenth aspect of the present invention, in the method of driving a plasma display panel, the sustain pulse is formed by switching between a voltage generated by a reactive power recovery circuit for recovering reactive power and a voltage from a power supply. The discharge is generated while the voltage generated by the power recovery circuit continuously increases and when the voltage is supplied from the power supply, and the discharge is dispersed a plurality of times during a half cycle of the sustain pulse.

In the driving method of a plasma display panel according to the eleventh aspect of the present invention, the sustain pulse has only the first voltage value at the beginning of the sustain discharge period.

According to a twelfth aspect of the present invention, at the end of the sustain discharge period, the sustain pulse has only the first voltage value.

A plasma display device according to a thirteenth aspect of the present invention includes a plasma display panel driven by the plasma display panel driving method according to any one of the first to twelfth aspects.

According to a fourteenth aspect of the present invention, the plasma display device is connected in parallel to the interelectrode capacitance of an AC-type plasma display panel using both a discharge mainly composed of an externally applied voltage and a discharge mainly composed of wall charges. A resonance coil for recharging the inter-electrode capacitance to the opposite polarity with a resonance current generated at the time of discharging, a reactive power recovery circuit including a plurality of recovery switches, a power supply, and a power supply for connecting both ends of the inter-electrode capacitance to the power supply. In a driving circuit for a plasma display panel having a pulse generation circuit including a main switch, a pause period of approximately zero potential difference is provided between pulses for applying an externally applied voltage and for inducing a discharge mainly including wall charges.

A plasma display device according to a fifteenth aspect of the present invention is the plasma display panel device according to the fourteenth aspect, wherein a resonance current generated at the time of discharging the inter-electrode capacitance is supplied to the main switch of the pulse generating circuit during the idle period. It is obtained by recharging the interelectrode capacitance after refluxing through the electrode.

A plasma display device according to a sixteenth aspect of the present invention is the plasma display panel device according to the fourteenth aspect, wherein a return switch is provided in parallel with the resonance coil during the idle period so that resonance generated when the interelectrode capacitance is discharged. It is obtained by refluxing the current through the reflux switch and then recharging the interelectrode capacitance.

A plasma display device according to a seventeenth aspect of the present invention is the plasma display panel device according to the fourteenth aspect, wherein a resonance waveform of a partial resonance circuit comprising a partial resonance capacitor connected in parallel to the resonance coil and a series connection of the partial resonance coil is provided. It consists of.

[0053]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIGS. 1 and 2 show a first embodiment according to the present invention. Before describing the description of this figure, first, driving by "discharge mainly composed of an externally applied voltage" and a prior application by the present inventors have been made. Invention, Japanese Patent Application No. 9-2
The difference from the driving using the “discharge mainly composed of wall charges” shown in 71458 will be described. One of the features of the “mainly wall-charged discharge” is that the voltage distribution in the panel is relaxed, and the in-plane luminance variation (display unevenness) is reduced. This is because even if there is a distribution of the discharge voltage in each cell in the panel, an amount of wall charge is formed according to the discharge characteristics of the cell and the discharge ends, so that the discharge mainly consisting of the externally applied voltage follows. When this occurs, the light emission intensity of each cell can be made uniform. In other words, when the sustain discharge is performed only by “discharge mainly by externally applied voltage”, the applied potential is fixed, so that the discharge intensity differs depending on the cell by the generated wall charge.
When cells are used together, cells with a high discharge voltage (hard to discharge) automatically self-adjust such that the discharge mainly due to wall charges is small, and cells with a low discharge voltage (easy to discharge) automatically increase discharge mainly due to wall charges. be able to.

This concept is called “discharge mainly composed of an externally applied voltage”.
Discharges at a predetermined applied voltage twice per cycle, whereas driving using "mainly wall-charged discharge" is one.
It can be considered that four discharges per cycle, two of which are due to an increase in discharge options such that the cell itself can freely select the discharge intensity according to the characteristics of the cell.

Furthermore, the luminous efficiency can be improved by using a discharge mainly consisting of wall charges. AC-PDPs are usually driven by using a glow discharge region, and thus have a characteristic that when the current density increases, the luminous efficiency deteriorates. This is described in detail in, for example, "Latest Technologies for Plasma Displays" (Mikoshiba: ED Research, 1996). When the discharge is sustained only by the discharge mainly composed of the externally applied voltage, the externally applied voltage must be reduced to the margin limit in order to increase the efficiency. On the other hand, when the discharge is sustained by also using the discharge mainly composed of the wall charges, the amount of the wall charges is reduced by the discharge mainly composed of the wall charges, so that the driving uses space charges. By reducing the voltage required for discharging as much as possible and taking a margin by utilizing space charge, the current density can be reduced and high efficiency can be obtained.

The method of obtaining high efficiency by using the above-described “discharge mainly composed of wall charges” has been disclosed in the prior application of the present inventors, Japanese Patent Application No. Hei 9-271458, but the present invention is not limited thereto. A more specific driving method and apparatus are provided.

The first embodiment according to the present invention will be described below with reference to the drawings. FIGS. 1 and 2 are diagrams showing a reactive power recovery circuit and a specific driving method according to the first embodiment of the present invention. First, in FIG. 1, in consideration of the fact that each discharge cell of the PDP is a capacitive load, an arbitrary discharge cell adjacent to each other of the PDP is replaced with a capacitance component C related to the discharge cell.
This is schematically illustrated as P. In the present embodiment, a series resonance type reactive power recovery circuit is used. As shown in FIG. 1, one end of the capacitance component CP, that is, one end of the X electrode of the PDP is indicated by an n-type MOSFET 11 (a switch and a parasitic diode symbol) whose drain terminal is connected to a power supply Vs (Vs: sustain voltage). ), And the source terminal is an n-type MOS FET
12 is connected to the drain terminal of the n-type MOS F
The source terminal of ET12 is grounded. In addition, both MO
Hereinafter, including the parasitic diodes connected in parallel to the SFETs 11 and 12, respectively, the FETs will be referred to as FETs, and the same applies to other MOS FETs described later.

The FETs 11 and 12 constitute a part of the X electrode driver circuit 141 (see FIG. 16) (a main line through which a display discharge current flows at the time of sustain discharge).
It operates as a clamp switch element for holding (clamping) the potential of the X electrode at the power supply potential Vs or the ground potential by a drive signal (gate voltage) applied to the gate terminals of the ETs 11 and 12. Note that the clamp switch element having such a configuration is referred to as “clamp switch elements 11 and 12” using the reference numerals of the FETs included therein. Further, the drive IC 142 is in a conductive state during the sustain discharge period, and is omitted here.

On the other hand, one end of the Y electrode is connected to the FETs 13 and 1 provided in the Y electrode driver circuit 15 (see FIG. 16).
4 are connected to the clamp switch elements 13 and 14 including the reference numeral 4.

The circuit 2 in the portion surrounded by the broken line in FIG.
Is a reactive power recovery circuit. Hereinafter, the reactive power recovery circuit 2 is also referred to as “recovery circuit 2”. The recovery circuit 2 may have substantially the same configuration as the conventional series-type reactive power recovery circuit (see FIG. 19). However, diodes 25 and 26 are connected in parallel with the recovery capacitors 27 and 28, respectively, such that the recovery coils 19 and 20 are cathodes and GND is an anode.

Next, a method of driving the PDP 10 will be described with reference to FIG. 1 and a timing chart of the voltage waveform of each pulse during the sustain discharge period (one subfield) shown in FIG. The potentials V11 to V18 in FIG. 2 indicate drive signal voltages applied to the respective gate terminals of the FETs 11 to 18. VCPX and VC in FIG.
PY is output from the circuit, and the capacitance component C of the PDP is output.
P indicates a voltage waveform applied to the X electrode and the Y electrode, and L indicates a light emission waveform.

In the present invention, the potentials of the X electrode and the Y electrode during the sustain discharge period are particularly important, and the potential of the W electrode is not mentioned. A DC pulse may be applied to a substantially intermediate potential for the purpose of avoiding discharge between the X electrode and the Y electrode. Also, VCP
X and VCPY are repeatedly applied arbitrarily a number of times in one cycle to obtain luminance. (FIG. 2 shows a pulse of one cycle and a half at a certain timing.)

At timing A, the FET 12
Is turned off, and then the FET 15 is turned on. As a result, the energy stored in the recovery capacitor is equivalent to FET1
5. The emission starts toward the panel CP via the resonance coil 19. Accordingly, the potential of VCPX also starts to rise, but during that time, the FET 15 is temporarily turned off at timing B.
To At this time, one end of the diode 25 is connected to the coil 19.
Since the other end is grounded to GND, a loop (circuit) such as GND-diode 25-coil 19-panel CP-FET14-GND is formed even when the FET 15 is in an open state, and the panel CP is stably formed. (The second voltage value) can be secured.

At timing C, the FET 15 is turned on again to supply the remaining energy of the recovery capacitor to the panel CP. After the energy is sufficiently released at the timing D, the voltage of Vs, which is the first voltage value, is supplied from the power supply when the FET 11 is turned on, and the voltage is clamped. Thus, the sustain pulse is formed into a waveform having a plurality of voltage values. In FIG. 2, the FET 11 and the FET 15 are illustrated at a timing at which they do not overlap with each other. Conversely, the waveform is more stable when it is overlapped for about several hundred ns.

At the timing E, the FET 11 is turned off,
When the FET 16 is turned on, the energy stored in the panel capacitance CP is the coil 19, the diode 22, the FET
The flow shifts to the recovery condenser 27 via 16. The VCPX is clamped to the GND potential by turning on the FET 12 at timing F when sufficient current has flowed. FET1
6. The ON timing of the FET 12 may be repeated as described above.

Then, at timing F, VCPX goes to GND.
At the same time, the FET 17 is turned on, and the potential of VCPY rises. Turn off FET17 once at timing G
By turning on again at timing H, VCPY
Has a step at potential Vk. After the energy of the capacitor 28 has sufficiently transferred to the panel CP at the timing I, the FE
T13 is turned on to clamp VCPY to Vs. At timing J, the FET 13 is turned off and the FET 18 is turned on, and the energy stored in the panel CP is transferred to the coil 2.
0, the process proceeds to the recovery capacitor 28 via the diode 24 and the FET 18. At timing K when sufficient resonance current has flowed, the FET 14 is turned on, and the potential of VCPY is changed to GND.
To clamp. Timing K is the timing A
The above operation is repeated a specified number of times.

During one cycle described above, discharge occurs four times: timing B to timing C, timing D to timing E, timing G to timing H, and timing I to timing J. This is because the voltage level of the stepped pulse waveform to be applied, that is, the first voltage value Vs
And the level of the second voltage value Vk.

(Case I: Vk ≧ minimum sustain voltage)
First, consider the case where the second voltage value Vk is sufficiently high, for example, Vk ≧ minimum sustain voltage. Since the panel CP is an aggregate of a plurality of cells, the discharge voltage varies.
Cells with a low discharge voltage (cells that are easy to attach) can be discharged at Vk, and cells with a high discharge voltage (cells that do not easily attach) can be discharged at Vs. If the one-point discharge start voltage is defined as Vf1, the all-point discharge start voltage is defined as Vfn, the one-point extinguishing voltage is defined as Vsm1, and the all-points extinguishing voltage is defined as Vsmn, the margin of a cell with a low discharge voltage is Vsmn to Vf1, and a cell with a high discharge voltage. Can be said to be Vsm1 to Vfn. Of course, the margin of the panel is Vsm1 to Vf1. These voltages vary depending on the panel, but approximately Vf1 = 21
0V, Vfn = 230V, Vsm1 = 155V, Vsm
n = about 135V. If the set voltage Vs, which is the first voltage value, is set to 160 V, a cell with a high discharge voltage emits light with a low luminance of 5 V above the lower margin of the margin.
A cell having a low discharge voltage has a higher luminance of 25 V above the margin. Therefore, if the second voltage value Vk is set to 140 V, a cell having a high discharge voltage cannot be discharged at Vk and is discharged at Vs, and a cell having a low discharge voltage is discharged at Vk. In this case, all operate on 5V from the margin, and the luminance becomes equal.

It is to be noted that a cell having a low discharge voltage is always V
Lighting at k and cells with a high discharge voltage do not always light at Vs. Depending on the conditions of the cell at that time,
Lighting at Vs and lighting at Vk may be alternately repeated. Conventionally, a discharge voltage was given only by Vs, but in the present invention, by applying an intermediate voltage Vk, (Vs-Vs), (Vs-Vk), (V
k-Vk).
That is, the cell itself discharges by freely selecting the discharge voltage according to the discharge characteristic peculiar to the cell. in this way,
There are cells that discharge at Vs and cells that discharge at Vk, and the light emission waveform L shown in FIG. 2 becomes a waveform in which a plurality of cells emit light twice in a half cycle of the sustain pulse as shown in the figure. That is. That is, the first discharge is the first discharge
And the second discharge is performed at the second voltage value Vk.
Done in Therefore, the discharge current is dispersed.

As a result, it is possible to reduce unevenness of luminance, loss of the mother electrode / circuit impedance, and decrease in discharge efficiency, which have conventionally been caused by variations in discharge voltage.

The power supply potential may be set to a value other than Vs, or the recovery current divided into two stages may be divided into three or more stages and supplied. That is, the sustain pulse is formed into a waveform having not only one voltage value but a plurality of voltage values,
It goes without saying that, by causing a discharge at each voltage value, the selection range of the discharge is dramatically increased, and a further effect is obtained.

(Case II: Case of Vk ≦ Vs / 10) Next, the second voltage value Vk is sufficiently low, for example, Vk ≦ Vs
Consider the case of / 10. Setting voltage Vs which is the first voltage
In a region where the discharge voltage is relatively high, or in a region where the space charge is better utilized and the firing voltage is lowered, a self-erasing discharge occurs. Since Vk is applied in a direction that causes the self-erasing discharge to occur more strongly, the intensity of the self-erasing discharge (discharge mainly composed of wall charges) increases. If Vk acting as an auxiliary is too high, the wall charge generated at the previous Vs is excessively reduced (in some cases, inverted), and the discharge cannot be sustained even when the next Vs is applied. FIG. 3 shows the invention of Japanese Patent Application No. 9-2 of the prior application by the present inventors.
FIG. 71D is a diagram showing the self-erase assist pulse voltage value corresponding to Vk and the luminous efficiency shown in 71458, but the maximum value of Vk was 17V, and a margin beyond that was not able to be secured. Although the maximum value of Vk depends on the panel structure, it is approximately 1/1 with respect to the set voltage Vs (the range of the panel margin 155 V to 210 V described in the case I).
It can be said that it is about 0 or less.

The difference between Case I and Case II will be described.
In case I, the discharge in each cell was twice per cycle. That is, a cell once discharged at Vk cannot be turned on at Vs thereafter. This is because once discharged at Vk, wall charges accumulate in the reverse direction, and if lighting is performed again, a voltage must be applied to cancel the charge. For example, it is as high as 2Vs and V
This cannot occur in the present embodiment where the difference between k and Vs is very small, such as Vs / 4 or less. On the other hand, in case II, the cell having a low discharge voltage discharges at Vs and discharges again at Vk in the next cycle with many wall charges formed, so that the same cell discharges four times per cycle. Can be considered. Also in this case, the light emission waveform as a whole becomes the waveform indicated by L in FIG. 2, and the discharge current is also dispersed.

In order to further clarify the above difference in the light emission mode, for example, the Vk potential may be changed without changing Vs. Even if the Vk potential is gradually raised to the Vs potential, the discharge is not interrupted on the way, and the light emission at Vk and the light emission at Vs are merged in an analog manner. Conversely, the case where the light emission at Vs gradually weakens as Vk is increased, the discharge is gradually delayed, and there is a voltage level at which the discharge is interrupted, can be considered as Case II.

Also in case II, cells with a high discharge voltage emit light at Vk weakly (in some cases, do not discharge), and cells with a low discharge voltage emit light at Vk intensely. Selectivity can be given to discharge. Further, since the number of times of discharge is increased in the same cell and the peak current per one time is reduced, the luminous efficiency of discharge is improved more than in case I.

Embodiment 2 FIG. 4 is a diagram illustrating a driving method according to a second embodiment of the present invention. In the first embodiment, in both case I and case II, the supply current flowing from the reactive power recovery circuit to the panel is temporarily stopped.
Voltage value. However, the light emission can be dispersed depending on the voltage setting without actively providing a stage as the second voltage value as in the related art. FIG. 4 shows the voltage waveforms VCPX, VCpy and the light emission waveform in this case. Discharging once while energy is being supplied to the panel capacity from the recovery circuit, that is, while the voltage is rising, and applying energy from the power supply to supply energy after the supply of energy from the recovery circuit has ceased. Is discharged again. The purpose of the present invention is to disperse the discharge current,
Since the purpose of the present invention is to reduce the peak current, a certain effect can be obtained if the discharge current can be dispersed by the conventional reactive power recovery circuit without using a sustain pulse having a step with the second voltage value.

In particular, in case II, the voltage mainly depends on the rate of change of the voltage, and is slower than the discharge delay time, and when the voltage changes slowly, the discharge mainly composed of wall charges is minimized. . Conversely, if the voltage changes earlier than the discharge delay time, there is a possibility that Vk ≧ Vs / 10, which leads to a decrease in margin. Therefore, it is desirable that the potential does not change during the discharge mainly by wall charges.

The difference from the conventional method of controlling discharge only by a certain set voltage is apparent only by observing the light emission waveform, and when the light emission waveform has a plurality of peaks, the operating point of the present invention is determined. Can be determined to have been operated.

Embodiment 3 FIG. 5 is a timing chart showing a driving method according to the third embodiment. In case II in the first embodiment, it is preferable that the falling of the pulse of the X electrode and the rising of the pulse of the Y electrode, or the falling of the pulse of the Y electrode and the rising of the pulse of the X electrode have continuity. This is because when there is a step in the GND potential, a discharge mainly consisting of wall charges occurs in that step, and a sufficient effect may not be obtained. FIG. 5 shows a timing chart as a countermeasure for this and will be described. Note that the circuit configuration and the like are the same as those in FIG.

In FIG. 5, the design concept for creating second voltage value Vk is different from that of the first embodiment. Specifically, timing D
When the FET 11 is turned off and the FET 16 is turned on, the FET 17 is turned on at the same time or with a slight delay. As a result, the energy of the capacitor 28 begins to flow back through a loop (circuit) connecting the FET 17, the coil 20, and the FET 14, and energy corresponding to the reactance is stored in the coil 20. By turning off the FET 17 at the same time as turning on the FET 12 at the timing E, the energy stored in the coil 20 flows to the panel. Once coil 2
Since it is stored at 0, the falling of the X electrode and the rising of the Y electrode are continuous. Thereafter, the FET 17 is turned on again from timing F in anticipation of the end of the discharge mainly by wall charges, and the energy remaining in the capacitor 28 is supplied to the panel.

Similarly, at timing H, the FET 13
F, FET18 simultaneously with or slightly after FET18 is turned on
By turning on 15, the energy is stored in the coil 19, and at the same time as the FET 14 is turned on at the timing I, the FET 15 is turned off and the energy of the coil 19 is supplied to the panel. Further, the remaining energy stored in the capacitor 27 is supplied to the panel at the timing J after the end of the discharge mainly composed of wall charges.

The third embodiment differs from the first embodiment only in that the ON timings of the FETs 17 and 15 are shifted, but the current flowing through the coils 20 and 19 is interrupted in the middle and the reactor The design philosophy is different from transferring energy and supplying it to the panel. In the first embodiment, the FET 17 and the FET 15 are turned on.
The voltage of Vk can be relatively easily generated by controlling the time. In the third embodiment, the coil 20 and the coil 1
9 cannot be controlled by the time of the FET 17 and the FET 15. However, when the third embodiment is used, a sufficient current can be made to flow more than in the first embodiment even when the discharge current is large.

The coils 19 and 20 have the recovery condenser 2
In the period when the energy of 7, 28 is supplied and the current is refluxed, there is no energy loss in an ideal circuit, but it is actually consumed by a resistor. Therefore, the reflux time should be somewhat short.

Embodiment 4 FIG. 6 shows a voltage waveform and a light emission waveform showing a driving waveform of the PDP device 50 according to the fourth embodiment of the present invention. This plasma display device is the same as the plasma display device 50 shown in FIG.
And the driving method has characteristics. Therefore, in the following description, the components in FIG. 16 are denoted by the same reference numerals.

FIG. 6 shows the potentials of the row electrodes Xi (i = 1.2... N), the potentials of the row electrodes Y and the column electrodes W, and the emission waveforms, and shows the drive waveforms in one subfield period. In the driving method according to the third embodiment, as shown in FIG. 6, the PDP device 50 is driven mainly by using a positive pulse. However, the polarity of the pulse shown in FIG. It may be driven in such a manner.

(Reset Period) First, a “reset period”
Then, an entire-surface write pulse is applied between all the column electrodes Wj and the row electrodes Y to erase the display history at the end of the immediately preceding subfield and supply priming particles.

(Address Period) Next, the "address period"
Then, an address discharge is selectively caused only in a cell to be displayed. As in the prior art example shown in FIG. 17, a scan pulse Vxg is sequentially applied to the row electrodes Xi, and in a cell to be lit, an “address discharge” which is a write discharge between the column electrode Wj and the row electrode Xi. Generate. At this time, a sub-scanning pulse Vysc is applied to the row electrode Y. Row electrode X
A potential difference of Vxg + Vysc is applied to i and the row electrode Y. This potential difference is a potential difference in which discharge does not start by itself, but discharge (transition) occurs immediately between the row electrodes Xi and Y triggered by the previous address discharge. As a result, an amount of positive or negative wall charges capable of performing sustain discharge only by application of the subsequent sustain pulse is accumulated.

(Sustain Discharge Period) In the "sustain discharge period", a sustain pulse is applied between the row electrodes Xi and Y to perform a sustain discharge in the sub-field for the written cell. Here, the reactive power recovery circuit is not operated during one initial period of the sustain discharge period. That is, in the example of FIG. 1, the FETs 15 to 18 are not operated. From the next cycle, the reactive power recovery circuit is operated to divide the emission peak into two and reduce the peak value. In addition, the reactive power recovery device is not operated during the last one cycle of the sustain discharge period. In the other periods of the sustain discharge period, the reactive power recovery circuit is operated, and the drive waveform actively used for discharging may be formed into a shape having a plurality of voltage values as described in the first embodiment. Alternatively, a plurality of voltage values of the sustain pulse may be formed by an externally applied voltage.
A feature of the fourth embodiment is that the applied waveforms at the beginning and end of the sustain discharge period are configured only by the first voltage value Vs of the sustain pulse in other periods, that is, rectangular pulses are formed. .

From the end of the address period to the beginning of the sustain discharge period, for example, when the X1 line is considered, the time is separated by the time of (address pulse width × number of address lines). This is as long as 1 msec or more depending on conditions, and the space charge generated during the address period no longer exists. Therefore, at the beginning of the sustain pulse, the sustain pulse becomes unstable with a discharge delay. Therefore, it is necessary to supply space charges to the entire panel as soon as possible to stabilize the discharge. This can be achieved by generating a strong discharge at the beginning of the sustain discharge period. Therefore, in the present embodiment, a pulse is formed only by the maximum voltage Vs of the sustain power supply to enhance discharge. Further, in FIG. 6, in the first two pulses, a pulse formed in a rectangular shape using only the first voltage value Vs is used, but the number of pulses may be arbitrarily determined without any particular reference to the number of pulses.

Thereafter, the discharge is dispersed into a plurality by forming the sustain pulse into a shape having a plurality of voltage values or by operating the reactive power recovery circuit under the condition that the discharge occurs. The cells to be discharged and the timing can be considered several as described in the first embodiment. In each case, a discharge mode is adopted in which the current peaks are dispersed and each peak value is reduced. .

When there is an interval from the end of the sustain discharge period to the reset period of the next subfield, as shown in FIG. 6, similarly to the beginning of the sustain discharge period, the last plural pulses are the first voltage having the maximum voltage value. It is better to form a rectangular shape with the voltage value Vs. Since the discharge with a reduced peak current is a weakened discharge, the amount of wall charges formed on the dielectric is small. If the time until the reset pulse is long,
The space charge generated during the sustain discharge period decreases, and the next reset cannot be performed stably. This can be achieved by forming a plurality of pulses at the end of the sustain discharge period into a rectangular shape at Vs, which is the first voltage value of the sustain pulse, so that wall charges are sufficiently formed and discharge can be stably performed during the reset period. Can be. Also, like the initial pulse of the sustain discharge period, the number of times of forming the rectangular pulse is arbitrary.

Embodiment 5 Next, a driving circuit of the plasma display device according to the fifth embodiment will be described. The fifth embodiment uses a parallel resonance type reactive power recovery circuit, and describes a method of dispersing the discharge by providing a pause period when a discharge mainly including wall charges is also used.

The panel used may be the same as in the first embodiment. The appearance of the plasma display device may be the same as that in FIG. FIG. 7 is a diagram showing a driving circuit of a plasma display panel according to Embodiment 5 of the present invention.
FIG. 8 is a timing chart of the input voltage waveform of each FET switch. In FIG. 7, PDP is a capacitor CP.
Is simulated. Further, FETs 51 to 54 represent a circuit for generating a pulse by the main switch, and recovery switches of the FET 55 and the FET 56, and the resonance coils 61 and 62 and the diodes 71 and 72 represent a reactive power recovery circuit. The reactive power recovery circuit, for the CP and the pulse generation circuit,
They are connected in parallel. The potentials V51 to V56 in FIG. 8 indicate the drive signal voltages applied to the respective gate terminals of the FETs 51 to 56, respectively. VCP in FIG. 8 indicates a voltage waveform output from the circuit and applied to the capacitance component CP of the PDP.

At the timing A, the FET 51 is turned on.
When the power supply is turned off, the voltage supply from the power supply stops. At the same time, since the FET 55 is turned ON, the charge charged in the CP starts flowing through the FET 55 so as to be inverted to the opposite polarity. At the timing B, the FET 53 and the FET 54
Since it is in the N state, the resonance current is
3. Recovery FET 55, diode 71, resonance coil 62
Reflux in the loop. Since the FETs 53 and 54 are ON between the flowing BCs, both ends of the CP are grounded, and a pause period is formed. Then, at timing C
As a result, the FET 54 is turned off, and the recirculated resonance current starts to be supplied to the CP again. After the maximum reverse voltage is applied to the CP at the timing D, the FET 52 turns on and the voltage is supplied from the power supply. Thereafter, at the timing E, the FET 52 is turned off symmetrically with the timing A, and at the same time, the FET 56 is turned off.
Is turned on, the electric charge charged to the CP starts to flow again so as to be inverted to the opposite polarity. The resonance current flows between the timings FG as in the case of the timing BC, and a pulse pause period is created. Thereafter, the same operation is repeated.

When the reflux period is provided and a pause period is formed between pulses, a self-erasing discharge due to wall charges can be generated during the pause period. Although the self-erasing discharge occurs even when no pause period is provided, as described in the first embodiment, the discharge mainly composed of wall charges in a state where the voltage is changing is unstable. According to the present embodiment, since there is a period in which CP is clamped to GND between pulses, a self-erasing discharge can be reliably generated without being affected by a discharge delay, and discharge efficiency can be improved. .
When the present embodiment is used, a falling discharge mainly composed of wall charges occurs, and even if a voltage drop occurs, a current flows from the GND potential and a large potential fluctuation can be prevented.

Embodiment 6 FIG. Hereinafter, Embodiment 6 of the present invention will be described. In the present embodiment, the return in Embodiment 5 is performed by additionally providing return switches (FETs) 57 and 58 without using the main switch. FIG. 9 shows a circuit configuration of the sixth embodiment.
FIG. 10 shows the gate waveform of each FET and the voltage waveform at both ends of the panel. The basic drive waveform is shown in Embodiment 5.
However, the ON timings of the main FET 53 and the main FET 54 do not overlap. FET5
5 turns ON, the diode 71 and the resonance coil 62
What has been charged to the PDP through the circuit is returned at an arbitrary timing (between BC) in a loop of the FET 57, the diode 73, and the resonance coil 62. Alternatively, what is charged to the PDP through the diode 72 and the resonance coil 61 by turning on the FET 56 is returned by the loop of the FET 58, the diode 74, and the resonance coil 61 between the timings FG. By adjusting the timing, the return potential (return timing) between the timing BC and the timing FG can be arbitrarily set. In order to generate the self-erase discharge more strongly, it is desirable to apply a pulse not only to a GND potential but also to a direction in which it is more positively induced. However, the discharge here must be a “mainly wall-charged discharge” which is an extension of the self-erasing discharge. The voltage is about 1/10 of the power supply voltage. For example, when the power supply voltage is 180 V, the voltage may be set to return at −18 V. According to the present embodiment, it is possible to better induce “discharge mainly composed of wall charges”, and to improve discharge efficiency. Further, in the present embodiment, an optimum voltage for inducing a discharge mainly composed of wall charges can be obtained by setting the return timing without providing another power supply.

Further, as described in the first embodiment, the reflux voltage may be further increased, set to a value equal to or higher than the discharge starting voltage, and used. In this case, the type I discharge in the first embodiment can be caused. Therefore, similarly to the first embodiment, the discharge can be dispersed according to the distribution of the discharge voltage of each cell, the loss of the resistance of the mother electrode and the impedance of the circuit can be reduced, and the uneven brightness can be eliminated.

In the present embodiment, the sustain pulse is applied to the first voltage value and the second voltage value using a parallel resonance type reactive power recovery circuit.
In the case of forming the shape having the voltage value of the above, and in case I of dispersing the discharge mainly of the externally applied voltage described above,
As described above, the conventional parallel resonance type driving circuit may be used as it is, and the voltage setting may be set to discharge by the recovery circuit. The voltage waveform and the light emission waveform at this time are the same as those shown in FIG.

Embodiment 7 FIG. FIG. 11 is a diagram showing a drive circuit according to Embodiment 7 of the present invention. In the seventh embodiment, a partial resonance capacitor Cpp and a partial resonance coil Lp are connected in parallel with the resonance coil. FIG. 12 shows Embodiment 7
7 is a voltage waveform of the plasma display panel of FIG. FE
When T56 turns on, the voltage of CP is applied to the resonance coil 63 and the partial resonance circuit A1. At this time, if the resonance frequency of the partial resonance circuit is selected to be higher than the resonance frequency determined by the CP and the resonance coil 63, the current flowing through the CP will be the oscillation current between the CP and the resonance coil 63 and the high-frequency oscillation current of the partial resonance circuit. It becomes a superimposed waveform. Due to the action of the diode 73, the voltage of the partial resonance capacitor Cpp inverted to the maximum value at the time tx in the partial resonance circuit no longer flows through the resonance coil 63.
Will be returned to the CP. With such a circuit configuration, it is possible to create a pause period τk required for “discharge mainly composed of wall charges” between pulses without refluxing current. In the present embodiment, since the pulse waveform that induces the discharge mainly composed of wall charges is generated by the resonance waveform of the partial resonance circuit, complicated ON / OFF timing control as in the fifth and sixth embodiments is required. And there is no advantage. Also,
As in the sixth embodiment, the first-stage pulse that can easily induce the “mainly wall-charged discharge” can be generated without providing a separate power supply. Of course, the voltage of the pulse waveform formed as described in the sixth embodiment may be equal to or higher than the discharge starting voltage to generate the discharge in case I described in the first embodiment.

In FIG. 11, a region A2 indicates a modification of the partial resonance circuit A1, that is, A2 is used instead of A1, and Cpp and Lp are connected via GND. By doing so, there is an advantage that a long wiring for connecting the X and Y terminals becomes unnecessary.

Embodiment 8 FIG. Next, a driving method of the PDP according to the eighth embodiment will be described. The present plasma display device 50 uses a circuit configuration as shown in FIG. That is, the drive waveforms in the first embodiment are set to Vh1, Vh2, and Vs as the power supply voltage of the power supply circuit 41.
The following describes an example in which the three power supply circuits are prepared by switching between these voltages and applying these voltages to the electrodes, and the power recovery circuit is not used for discharging. The recovery circuit used in this embodiment may be a parallel resonance type or a series resonance type.

FIG. 14 shows a voltage waveform VC applied to the X electrode.
A voltage waveform VCPY applied to the PX and Y electrodes and a light emission waveform L are shown. In the first embodiment, the second voltage value Vk is created by the recovery circuit. However, in the present embodiment, similarly to the first voltage value Vs, the voltages Vh1 and Vh2 are supplied from the power supply and the second voltage value Vk is generated. Create values (here multiple). In the present embodiment, a case of Case I in Embodiment 1 will be described as an example.

At timings A and B, energy is supplied from the recovery circuit to the capacity of the panel. At timing B, the recovery circuit is suspended once, and the voltage of Vh1 is supplied from the power supply. For example, Vh1 is set to 150V. Here, cells that are easily discharged are from timing B to timing C.
To discharge once. Next, from the timing C to the timing D, energy is again supplied from the recovery circuit to the capacity of the panel, and the recovery circuit is stopped at the timing D, and Vh2
Is supplied from a power supply. For example, Vh2 is 170V
It is. The cells that did not discharge at Vh1 and that can discharge are at the timing D during the Vh2 application period as before.
To discharge at timing E. Again, timing E
From timing F, energy is supplied from the recovery circuit to the capacity of the panel, and at timing F, the first voltage value Vs is supplied from the power supply. Vs is, for example, 190V
As a result, all cells that could not be discharged at Vh1 and Vh2 are discharged. A voltage pulse is applied to the Y electrode similarly to the X electrode.

As a result, the light emission waveform can be divided into three as shown in FIG. As a result, the peak current can be dispersed, and the loss caused by the circuit impedance and the resistance of the bus electrode can be reduced.

Also, as in the first embodiment, the cell itself can select the discharge voltage from Vh1 to Vs according to the voltage distribution of the discharge cell. The range of selection is equal to or greater than that of the first embodiment, and (Vh1−Vh1) (Vh1−Vh2) (Vh1−
Vs) (Vh2-Vh2) (Vh2-Vs) (Vs-V
s). Cells that are difficult to discharge due to process-related factors are discharged at (Vs−Vs), and cells that are easily formed discharge at (Vh1−Vh1). In addition, discharge is a stochastic phenomenon, and it can be assumed that the discharge suddenly weakens. For example, even if a cell having the center of the driving voltage at Vh2 suddenly weakens the discharge, the center of the discharge is temporarily shifted to Vs, the discharge is strengthened, and then the center of the discharge is shifted to Vh2 again. It is also possible.

The recovery circuit forms a pulse waveform having a plurality of voltage values as in the first and second embodiments, and the voltage from a power supply having a plurality of voltage outputs as in the eighth embodiment described here. Is switched to form a pulse waveform having a plurality of voltage values. Since the recovery circuit has a high impedance configuration including a coil, the voltage drop due to the discharge current is likely to be large. Therefore, if the number of discharge cells in the recovery circuit is excessively increased, there is a possibility that the ability to flow current is lost and the margin is reduced. However, in the eighth embodiment, although there is a disadvantage that the circuit cost increases due to an increase in the number of power supplies, the margin is not likely to decrease because the discharge current can be supplied from the power supply.

In this embodiment, for example, the first embodiment
Has been described in the case I, but a pulse waveform capable of inducing a discharge mainly composed of wall charges as in the case II may be formed only by the power supply.

[0108]

According to the first aspect of the present invention, the sustain voltage having the first voltage value for performing the first discharge and the second voltage value for performing the second discharge during the half cycle. Since the AC plasma display panel is driven by the pulse, the peak current can be dispersed, the resistance loss of the mother electrode is reduced, the loss due to the impedance of the circuit is reduced, and the discharge efficiency is also improved.

According to the second aspect of the present invention, the voltage generated by the reactive power recovery circuit for recovering the reactive power and the voltage from the power supply are switched to form the sustain pulse. With this power supply, one with high discharge efficiency can be obtained.

According to the third aspect of the present invention, since the reactive power recovery circuit used in the second aspect of the present invention is of a parallel resonance type, a high efficiency of discharge can be obtained with a small number of components.

According to the fourth aspect of the present invention, the voltage value of the sustain pulse can be freely set by making the reactive power recovery circuit used in the second aspect of the invention a series resonance type,
Discharge can be reliably dispersed.

According to the fifth aspect of the present invention, since a power supply having a plurality of different voltage outputs is provided, and the plurality of different voltages are switched to form a sustain pulse, the discharge is reliably performed without lowering the discharge margin. Can be dispersed.

According to the invention of claim 6, the first discharge and the second discharge are discharges mainly composed of an externally applied voltage, and the discharges of a plurality of cells are dispersed so as to be dispersed. Since the first voltage value and the second voltage value are set, it is possible to suppress the variation in the discharge characteristics unique to the cell and reduce the luminance unevenness.

According to the seventh aspect of the present invention, the second voltage value is set to be equal to or higher than the minimum sustain voltage, and the first voltage value is set to be equal to or lower than the discharge starting voltage, so that the discharge can be more reliably dispersed.

According to the eighth aspect of the invention, the first discharge and the second discharge are a combination of a discharge mainly composed of an externally applied voltage and a discharge mainly composed of a wall charge. The first voltage value and the second voltage value are set so that the same cell is dispersed in a plurality of discharges during the period, so the number of discharges per cycle is increased, and , The current density of the discharge can be lowered, and the discharge efficiency can be further improved.

According to the ninth aspect of the present invention, discharge can be reliably dispersed by limiting the second voltage value to approximately 1/10 or less of the first voltage value.

According to the tenth aspect of the present invention, the sustain pulse is formed by switching between the voltage generated by the reactive power recovery circuit for recovering the reactive power and the voltage from the power supply, and generated by the reactive power recovery circuit. Discharge is generated during the continuous rise of the voltage to be supplied and when the voltage is supplied from the power supply, and the discharge is dispersed a plurality of times during the half cycle of the sustain pulse, so that the discharge efficiency is improved by simple control. be able to.

According to the eleventh aspect of the present invention, at the beginning of the sustain discharge period, the sustain pulse has only the first voltage value, so that the discharge is stably performed from the address period to the sustain discharge period. Can be migrated.

According to the twelfth aspect, at the end of the sustain discharge period, the sustain pulse has only the first voltage value, so that the discharge is stably transferred from the sustain discharge period to the reset period. can do.

According to the thirteenth aspect, in the first aspect,
According to the driving method of the twelfth aspect, the first electrode and the second electrode
Since a drive circuit for applying a voltage between the electrodes is provided, a plasma display device having the effects of the first to twelfth aspects can be obtained.

According to the driving circuit of the plasma display panel of the present invention, even when a parallel resonance type recovery circuit device is used, a discharge mainly consisting of wall charges is generated between pulses for applying an externally applied voltage. Since the rest period in which the induced potential difference is substantially zero is provided, it is possible to surely induce the discharge mainly composed of wall charges, and to improve the discharge efficiency.

According to the driving circuit for a plasma display panel according to the fifteenth aspect, during the idle period according to the fourteenth aspect, the resonance current generated when the interelectrode capacitance is discharged is returned via the main switch of the pulse generating circuit. After that, I decided to get it by recharging the capacitance between the electrodes,
Discharge mainly by wall charges can be reliably induced, and power use efficiency can be improved.

According to the driving circuit of the plasma display panel of the sixteenth aspect, a return switch is provided in parallel with the resonance coil during the idle period of the fourteenth aspect, and the resonance current generated at the time of discharging the interelectrode capacitance is reduced. Since it is obtained by recharging the inter-electrode capacitance after refluxing through the reflux switch, it is possible to set an optimal pulse voltage that induces a discharge mainly composed of wall charges.

According to the driving circuit for a plasma display panel according to the seventeenth aspect, since the resonance waveform is constituted by the resonance waveform of the partial resonance circuit comprising the partial resonance capacitor connected in parallel to the resonance coil and the partial resonance coil connected in series. It is possible to realize a pause period for inducing a discharge mainly composed of charges without using complicated timing control.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a configuration of a reactive power recovery circuit of a plasma display device according to a first embodiment.

FIG. 2 is a timing chart showing a driving voltage waveform and a light emission waveform for describing a driving method of the plasma display device according to the first embodiment.

FIG. 3 shows a relationship between an auxiliary pulse and luminous efficiency shown in Japanese Patent Application No. 9-271458.

FIG. 4 is a diagram for explaining a driving voltage waveform and a light emission waveform for describing a driving method of the plasma display device according to the second embodiment.

FIG. 5 is a timing chart showing a driving voltage waveform and a light emission waveform for describing a driving method of the plasma display device according to the third embodiment.

FIG. 6 is a timing chart showing a voltage waveform and a light emission waveform in one subfield for describing a driving method of the plasma display device according to the fourth embodiment.

FIG. 7 is a diagram for explaining a configuration of a reactive power recovery circuit of a plasma display device according to a fifth embodiment.

FIG. 8 is a timing chart showing a driving voltage waveform of the plasma display device according to the fifth embodiment.

FIG. 9 is a diagram illustrating a configuration of a reactive power recovery circuit of a plasma display device according to a sixth embodiment.

FIG. 10 is a timing chart showing a driving voltage waveform of the plasma display device according to the sixth embodiment.

FIG. 11 is a diagram illustrating a configuration of a reactive power recovery circuit of a plasma display device according to a seventh embodiment.

FIG. 12 is a diagram showing a driving voltage waveform and a current waveform for describing a driving method of the plasma display device according to the seventh embodiment.

FIG. 13 is a block diagram showing an overall configuration of a plasma display panel device according to an eighth embodiment.

FIG. 14 is a diagram showing a driving voltage waveform and a light emission waveform for describing a driving method of the plasma display device according to the eighth embodiment.

FIG. 15 is a perspective view showing a structure of a conventional AC plasma display panel.

FIG. 16 is a block diagram showing an overall configuration of a conventional AC plasma display panel device.

FIG. 17 is a timing chart showing a driving voltage waveform in one subfield of the conventional AC plasma display panel.

FIG. 18 is a diagram for explaining a configuration of a parallel resonance type reactive power recovery circuit according to a conventional plasma display device.

FIG. 19 is a diagram illustrating a configuration of a series resonance type reactive power recovery circuit according to a conventional plasma display device.

[Explanation of symbols]

 10, 101 Plasma display panel (PDP) 2, 202, 302 Reactive power recovery circuit 41 Power supply circuit CP Interelectrode capacitance of plasma display panel 51, 52, 53, 54 Main switch 55, 56 Recovery switch 57, 58 Return switch 61, 62, 63 Resonance coil Cpp Partial resonance capacitor Lp Partial resonance coil Vk, Vh1, Vh2 Second voltage value Vs First voltage value

Claims (17)

[Claims] 1. A first method for performing a first discharge during a half cycle.
A method of driving an AC-type plasma display panel, wherein the driving is performed by a sustain pulse having a voltage value of (a) and a second voltage value for causing a second discharge. 2. The plasma display panel according to claim 1, wherein the sustain pulse is formed by switching between a voltage generated by a reactive power recovery circuit for recovering reactive power and a voltage from a power supply. Drive method. 3. The driving method for a plasma display panel according to claim 2, wherein said reactive power recovery circuit is a parallel type reactive power recovery circuit connected in parallel to a capacitance between electrodes of the plasma display panel. 4. The method of driving a plasma display panel according to claim 2, wherein the reactive power recovery circuit is a series type reactive power recovery circuit connected in series to a capacitance between electrodes of the plasma display panel. 5. The method according to claim 1, further comprising a power supply having a plurality of different voltage outputs, wherein the plurality of different voltages are switched to form the sustain pulse. 6. The first discharge and the second discharge are mainly composed of an externally applied voltage, and the first voltage value and the second voltage are set so that discharge timings of a plurality of cells are dispersed. 6. The method of driving a plasma display panel according to claim 1, wherein a voltage value of 2 is set. 7. The method according to claim 6, wherein the second voltage value is equal to or higher than the minimum sustain voltage, and the first voltage value is equal to or lower than the discharge starting voltage. 8. The first discharge and the second discharge are a combination of a discharge mainly composed of an externally applied voltage and a discharge mainly composed of wall charges, and a plurality of identical cells are provided during a half cycle of the sustain pulse. So that the first discharge
6. The method according to claim 1, wherein the first voltage value and the second voltage value are set. 9. The method according to claim 8, wherein the second voltage value is approximately 1/10 or less of the first voltage value. 10. A sustain pulse is formed by switching between a voltage generated by a reactive power recovery circuit for recovering reactive power and a voltage from a power supply, and the voltage generated by the reactive power recovery circuit continuously increases. A driving method for driving the plasma display panel, wherein a discharge is generated during the half-period of the sustain pulse and a discharge is generated during the half-cycle of the sustain pulse. 11. The driving method of a plasma display panel according to claim 1, wherein the sustain pulse has only the first voltage value at the beginning of the sustain discharge period. 12. The method of driving a plasma display panel according to claim 1, wherein the sustain pulse has only the first voltage value at the end of the sustain discharge period. 13. A plasma display panel device comprising a driving circuit driven according to the driving method according to claim 1. Description: 14. An AC-type plasma display panel in which a discharge mainly composed of an externally applied voltage and a discharge mainly composed of a wall charge are connected in parallel to a capacitance between electrodes of the AC type plasma display panel. A plasma having a resonance coil for recharging the capacitance to the opposite polarity, a reactive power recovery circuit including a plurality of recovery switches, a power supply, and a pulse generation circuit including a main switch for connecting both ends of the interelectrode capacitance to the power supply. In a display panel drive circuit,
A driving circuit for a plasma display panel, wherein a pause period in which a potential difference between the electrodes for inducing a discharge mainly comprising wall charges is provided between pulses for applying an externally applied voltage is substantially zero. 15. The idle period is obtained by recirculating a resonance current generated at the time of discharging the inter-electrode capacitance through a main switch of the pulse generation circuit and then recharging the inter-electrode capacitance. The driving circuit for a plasma display panel according to claim 14, wherein 16. A return switch is provided in parallel with the resonance coil during the idle period, and a resonance current generated when the interelectrode capacitance is discharged is returned via the return switch, and then recharged to the interelectrode capacitance. 15. The driving circuit for a plasma display panel according to claim 14, wherein: 17. The plasma according to claim 14, wherein said idle period is constituted by a resonance waveform of a partial resonance circuit comprising a partial resonance capacitor connected in parallel to said resonance coil and a series connection of the partial resonance coil. Display panel drive circuit.