JPH11284155A - Non-volatile semiconductor memory - Google Patents

Abstract

(57) [Problem] To narrow the space between select gate electrodes regardless of the size of a contact portion. SOLUTION: The select gate transistor has a first layer select gate electrode SGD (lower) and a second layer select gate electrode SGD (upper). The select gate electrode SGD (bottom) has a plurality of contact regions, and the select gate electrode SGD (top) is removed on the plurality of contact regions. Regarding two select gate electrodes adjacent in the column direction, the contact region of one select gate electrode and the contact region of the other select gate electrode do not face each other. The other select gate electrodes SDG (lower) and SGD (upper) facing the contact region of one select gate electrode are removed so that they are not short-circuited.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory.

[0002]

2. Description of the Related Art Conventionally, as one of the nonvolatile semiconductor memories, for example, a NAND flash EEPROM having a memory cell array section as shown in FIG. 46 is known.

The memory cell array of a NAND flash EEPROM is composed of a plurality of NAND cell units. Each NAND cell unit is composed of N (for example, 16) memory cells connected in series.
An AND column, a source-side select gate transistor connected between one end of the NAND column and the source line SL,
It has a drain-side select gate transistor connected between the other end of the ND column and the bit line BLi.

The memory cell array section includes a plurality of blocks B
LKj. Control gate electrodes (word lines) CG0 to CG15, source side select gate electrode SGS, and drain side select gate electrode SGD
Extend in the row direction, and the bit line BLi extends in the column direction. The plurality of memory cells M0 to Mi connected to one word line constitute a unit called a page PAGE.

Usually, one page of data is read by one read operation. The data for one page is latched by the latch circuit and then output serially outside the memory chip.

FIG. 47 shows a NAND flash EEPROM.
2 shows an outline of a planar pattern of an OM memory cell array section. FIG. 48 shows the region XD of FIG. 47 in an enlarged manner,
FIG. 49 shows the region XS of FIG. 47 in an enlarged manner. FIG. 50 is a sectional view of a memory cell array portion of the NAND flash EEPROM.

A field oxide film 11 is formed on a silicon substrate 10. In the element region surrounded by the field oxide film 11, for example, a NAND comprising 16 memory cells and 2 select gate transistors
Cell units are arranged.

Each memory cell has a floating gate electrode FG and a control gate electrode (word line) CG0-CG0.
It is composed of a CG 15 and an N-type diffusion layer 12. The source side select gate transistor includes select gate electrodes SGS (upper), SGS (lower) and N-type diffusion layer 12a,
12 are provided. The drain-side select gate transistor has a select gate electrode SGD
(Upper), SGD (lower) and N-type diffusion layers 12b and 12.

Control gate electrodes CG0-CG1
5. Source-side select gate electrode SGS (top), SGS
(Bottom) and drain side select gate electrode SGD
(Upper), SGD (lower) extend in the row direction, and bit line B
Li extends in the column direction. The bit line BLi is
It is connected to the diffusion layer 12b via the wiring B. Source line SL is connected to diffusion layer 12a.

The source-side and drain-side select gate transistors are provided for selecting a memory cell to be written and erased when writing and erasing data, respectively. Therefore, the source-side and drain-side select gate transistors are configured to perform a switching operation at a fixed threshold value, unlike the memory cells.

Therefore, in the source-side and drain-side select gate transistors, the control signal is directly applied to the first-layer select gate electrodes SGS (lower) and SGD (lower). More specifically, a part of the second-layer select gate electrodes SGS (upper) and SGD (upper) is removed, and the removed parts are replaced with first-layer select gate electrodes SGS (lower) and SGD (lower). A contact region for SGD (bottom) is formed. Contact holes SS and SD are formed on this contact region.

The hatched portions in FIGS. 48 and 49 indicate the select gate electrodes SGS (lower) and SG of the first layer.
D (bottom) indicates the portion where it exists.

The contact area (contact holes SS,
SD) is provided every time the select gate electrode straddles several hundred bit lines in consideration of the resistance of the select gate electrode. Also, for example, the first-layer select gate electrode SGS of the source-side select gate transistor
The contact region for (lower) is provided in common to the two first-layer select gate electrodes SGS (lower) adjacent in the column direction, and the first-layer select gate electrode SGD (lower) of the drain-side select gate transistor. ) Are separately provided in the two first-layer select gate electrodes SGD (lower) adjacent in the column direction.

In the drain side select gate transistor, contact regions for two first layer select gate electrodes SGD (lower) adjacent in the column direction are alternately arranged so as not to face each other as shown in FIG. Or they may be arranged so as to face each other as shown in FIG.

Next, a conventional NAND flash EEP
A method for manufacturing the memory cell array section of the ROM will be described.

First, as shown in FIGS. 52 to 57, L
A field oxide film (hatched portion) 11 is formed on a silicon substrate 10 by using the OCOS method. Further, a gate oxide film 13 is formed in the element region between the field oxide films 11 by a thermal oxidation method. A polysilicon film 14 containing, for example, an n-type impurity (for example, phosphorus) of about 2 × 10 ²⁰ cm ⁻³ is formed on the field oxide film 11 and the gate oxide film 13 by using the CVD method.

Further, a slit-shaped opening OP extending in the column direction is formed in the polysilicon film 14. This opening O
The width of P (the width in the row direction) is smaller than the width of the field oxide film 11 (the width in the row direction).

An insulating film 15 is formed on the polysilicon film 14. The insulating film 15 is, for example, a silicon oxide film having a thickness of about 5 nm, a silicon nitride film having a thickness of about 8 nm, and a thickness of about 5 nm.
nm silicon oxide film (called "ONO film").

Further, for example, the insulating film 1 is formed by CVD.
A polysilicon film 16 containing an n-type impurity (for example, phosphorus) of about 3.6 × 10 ²⁰ cm ⁻³ is formed on 5. Subsequently, a silicon nitride film (mask material) 17 is formed on the polysilicon film 16 by the CVD method.

A resist pattern 18A is formed on the silicon nitride film 17 by PEP (photo etching process). Then, using this resist pattern 18A as a mask, R
IE, the silicon nitride film 17 and the polysilicon film 1
6 is etched. As a result, the linear polysilicon film 16 extending in the row direction remains, and the control gate electrodes (word lines) CG0 to CG15 and the second-layer select gate electrodes SGS (upper) and SGD (upper) are formed. .

At this time, select gate electrode SGS
Regarding (upper) and SGD (upper), portions corresponding to contact regions for the first-layer select gate electrode are removed. Thereafter, the resist pattern 18A is
Removed.

Next, as shown in FIGS.
A resist pattern 18B is formed in a portion corresponding to a contact region for a first-layer select gate electrode by EP (photo etching process). Using the resist pattern 18B as a mask, the insulating film 15 and the polysilicon film 14 are etched by RIE.

At this time, the silicon nitride film 17 existing on the control gate electrodes (word lines) CG0 to CG15 and the second-layer select gate electrodes SGS (upper) and SGD (upper) also functions as an RIE mask. . Therefore, the control gate electrodes (word lines) CG0 to CG
15, a floating gate electrode FG made of a polysilicon film 14 is formed. Immediately below the select gate electrodes SGS (upper) and SGD (upper), a first-layer select gate made of the polysilicon film 14 is formed. Electrode SGS
(Lower), SGD (lower) are formed, and the resist pattern 1
Immediately below 8B, contact regions for the first-layer select gate electrodes SGS (lower) and SGD (lower) made of the polysilicon film 14 are formed.

Thereafter, the resist pattern 18B is removed. Although the silicon nitride film 17 is not deleted in this example, it may be deleted or not.

Next, as shown in FIGS. 66 to 77, the control gate electrodes CG0 to CG15 and the select gate electrodes SGD (top) and SGS (top) are used as masks.
An n-type impurity (phosphorous or arsenic) is ion-implanted into the silicon substrate 10 by self-alignment,
12a and 12b are formed. Note that the diffusion layer 12a is made of N
The source of the AND cell unit, the diffusion layer 12b
It becomes the drain of the NAND cell unit.

On the entire surface of the silicon substrate 10, for example, a BPSG film having a thickness of about 1.45 μm, which completely covers the control gate electrodes CG0 to CG15 and the select gate electrodes SGD (upper) and SGS (upper). 19 is formed. After that, the BPSG film 19 is polished by about 0.4 μm using a CMP method to flatten the surface of the BPSG film 19.

Further, a silicon nitride film 20 as an etching stopper is formed on the BPSG film 19 by the CVD method. Subsequently, the silicon nitride film 20 is formed by CVD.
A TEOS film 21 is formed thereon.

The TEOS film 21 is formed by using PEP and RIE.
Then, wiring grooves 22A to 22E are formed. At the time of RIE, the silicon nitride film 20 functions as an etching stopper. Further, a diffusion layer (drain) 12 is formed on the silicon nitride film 20 and the BPSG film 19 by using PEP and RIE.
b and the contact holes 23A and 23C reaching the diffusion layer (source) 12a, and the contact holes 23B and 23D reaching the contact regions for the first-layer select gate electrodes SGD (lower) and SGS (lower). .

Thereafter, the wiring groove 22A is formed on the TEOS film 21.
To 22E and the inner surfaces of the contact holes 23A to 23D respectively.
32 are formed. Barrier metal 24, 26, 28, 3
Reference numerals 0 and 32 are made of, for example, titanium nitride and titanium. Also, barrier metals 24, 26, 28, 30, 32
The wiring grooves 22A to 22E and the contact holes 23
A to 23D completely filling tungsten films 25, 27,
29, 31, and 33 are formed. This tungsten film 2
5, 27, 29, 31, and 33 are polished by the CMP method, and are formed in the wiring grooves 22A to 22E and the contact holes 23.
It remains only in A to 23D.

Next, as shown in FIGS.
The TEOS film 34 is formed on the TEOS film 21 by the VD method. Subsequently, a silicon nitride film 35 as an etching stopper is formed on the TEOS film 34 by the CVD method. Further, a TEOS film 36 is formed on the silicon nitride film 35 by the CVD method.

Using PEP and RIE, the TEOS film 36
Then, wiring grooves 37A and 70A are formed. At the time of RIE, the silicon nitride film 35 functions as an etching stopper. Further, by using PEP and RIE, contact holes 37B and 37B are formed in the silicon nitride film 35 and the TEOS film 34.
Form 70B.

Thereafter, the wiring groove 37 is formed on the TEOS film 36.
A, 70A inner surface and contact holes 37B, 70B
The barrier metals 38 and 71 are formed respectively on the inner surfaces of the layers.
The barrier metals 38 and 71 are made of, for example, titanium nitride and titanium. Also, the wiring grooves 37A, 70A and the contact holes 37 are formed on the barrier metals 38, 71.
Metal film that completely fills B, 70B (such as aluminum)
39 and 72 are formed.

The metal films 39 and 72 are polished by the CMP method and remain only in the wiring grooves 37A and 70A and in the contact holes 37B and 70B. As a result, bit lines BL and other wirings are formed. A passivation film made of a silicon nitride film is formed on the bit lines and other wires.

Through the above manufacturing steps, a NAND flash EEPROM is completed.

[0035]

As described above, the source-side and drain-side select gate transistors in the NAND cell unit have the first-layer select gate electrodes SGS (lower) and SGD (lower), respectively, as described above. It has a second-layer select gate electrode SGS (upper) and SGD (upper). Also, the second-layer select gate electrode SGS
(Top), a part of SGD (top) is removed, and the part is replaced with the first-layer select gate electrodes SGS (bottom), SG
It is a contact region for D (bottom).

That is, the first-layer select gate electrodes SGS (lower) and SGD (lower) actually function as the select gate electrodes of the select gate transistors, and the contact region is the first-layer select gate electrode. Considering the resistance of the select gate electrodes SGS (lower) and SGD (lower), they are set at a plurality of places (one place for every several hundred bit lines).

The size of the contact region is determined in consideration of misalignment of a contact hole formed on the contact region by a photolithography process. Normally, when the contact hole size includes the misalignment margin of the contact hole, the length of the contact region in the column direction is larger than the gate length g of the select gate electrodes SGS (lower) and SGD (lower).

FIGS. 88 and 89 show two examples of the arrangement of the contact region for the first-layer select gate electrode on the drain side. Here, n is the minimum width that can be processed in the photolithography process (for example, the interval between control gate electrodes is set to n).

In the example shown in FIG. 88, the length of a portion where the contact region protrudes from the gate region (a linear region other than the contact region) of the select gate electrode SGD (lower) is h, and the contact region is adjacent in the column direction. Assuming that the interval between the contact regions of the first-layer select gate electrode SGD (lower) is k, k = n, and the gate region of the first-layer select gate electrode SGD (lower) adjacent in the column direction. The interval between them is k + 2h.

In the example of FIG. 89, the length of the portion where the contact region protrudes from the gate region of the select gate electrode SGD (below) is defined as h, and the select gate electrode SGD of the first layer adjacent in the column direction is defined as h. M)
Then, n <m, and the distance between the gate regions of the first-layer select gate electrode SGD (lower) adjacent in the column direction is m + h.

The reason why m is larger than n is that misalignment of the second-layer select gate electrode SGD (upper) causes
The contact region of the first-layer select gate electrode SGD (lower) and the select gate electrode SGD adjacent thereto
This is because the misalignment in (above) must be considered.

In any of the examples, select gate electrodes adjacent to each other in the column direction (portions other than the contact region)
Is larger than the minimum width n that can be processed in the photolithography process. This hinders an increase in the storage capacity of the memory cell array section (when the area is fixed) and a reduction in the area of the memory cell array section (when the storage capacity is fixed).

As shown in FIGS. 90 and 91, when a resist misalignment occurs in a photolithography step during the patterning of the contact region of the first layer select gate electrode SGD (lower), the first layer The connection point (shown by a thick line) between the contact region and the gate region of the first select gate electrode SGD (lower) becomes narrower, and the resistance of the first-layer select gate electrode SGD (lower) increases.

The present invention has been made in order to solve the above-mentioned drawbacks, and an object of the present invention is to make the distance between the gate regions (line-shaped portions) of the select gate electrodes of the select gate transistors independent of the size of the contact region. The idea is to come up with a pattern that can be reduced.

It is another object of the present invention to provide a method of forming a contact region for a first-layer select gate electrode even if a resist misalignment occurs in a photolithography step during patterning of a contact region with the first-layer select gate electrode. Is to come up with a pattern that does not increase.

[0046]

In order to achieve the above object, a nonvolatile semiconductor memory according to the present invention has first and second select gate electrodes which are adjacent to each other across a diffusion layer in a column direction and extend in a row direction. The first and second select gate electrodes are each formed of a first conductive layer and a second conductive layer thereon, and the first conductive layer of the first and second select gate electrodes is formed of the first conductive layer. A plurality of contact regions for the first and second select gate electrodes, wherein the second conductive layers of the first and second select gate electrodes are removed on the plurality of contact regions, and the first select gate electrode contacts the first conductive layer. A region and a contact region of the second select gate electrode with respect to the first conductive layer are arranged so as not to face each other, and the first select gate electrode has a first contact region.
The first and second conductive layers of the second select gate electrode at a portion facing a contact region with respect to the conductive layer are removed, and the first and second conductive layers at a portion of the second select gate electrode facing a contact region with the first conductive layer are removed. The first and second conductive layers of the select gate electrode have been removed.

The contact region of the first select gate electrode to the first conductive layer is commonly connected to a first wiring on the first select gate electrode, and the contact region of the second select gate electrode to the first conductive layer. Are commonly connected to a second wiring on the second select gate electrode.

Further, a contact region of the first and second select gate electrodes with respect to the first conductive layer may be commonly connected to a wiring on the first and second select gate electrodes.

The first and second select gate electrodes are:
A select gate transistor connected to one end on the drain side of a NAND string including a plurality of memory cells connected in series can be configured.

The first and second select gate electrodes are:
A select gate transistor connected to one end on the source side of a NAND string including a plurality of memory cells connected in series may be configured.

The interval between the first and second select gate electrodes can be substantially equal to the interval between the plurality of control gate electrodes of the plurality of memory cells.

The contact region of the first select gate electrode with respect to the first conductive layer and the contact region of the second select gate electrode with respect to the first conductive layer are arranged at regular intervals.

The length of the plurality of contact regions in the column direction is longer than the gate lengths of the first and second select gate electrodes.

The nonvolatile semiconductor memory of the present invention has first and second select gate electrodes adjacent to each other in the column direction with a diffusion layer interposed therebetween and extending in the row direction. A first conductive layer and a second
The first conductive layer of the first and second select gate electrodes has a plurality of contact regions with the first conductive layer, and at least one of the first and second select gate electrodes is The second conductive layer is removed on the plurality of contact regions, and the length of the plurality of contact regions in the column direction is the first and second lengths.
It is configured to be longer than the gate length of the select gate electrode.

It is preferable that the second conductive layer has a pattern bent in the column direction on the contact region.

The contact region of the first select gate electrode to the first conductive layer and the contact region of the second select gate electrode to the first conductive layer are arranged so as not to face each other.

The first and second conductive layers of the second select gate electrode are removed at a portion facing the contact region of the first select gate electrode with the first conductive layer, and the first conductive layer of the second select gate electrode is removed. The portions of the first and second conductive layers of the first select gate electrode opposite to the contact region for the layer have been removed.

[0058]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a nonvolatile semiconductor memory according to the present invention will be described in detail with reference to the drawings.

FIG. 1 schematically shows a plane pattern of a memory cell array section of a NAND flash EEPROM according to a first embodiment of the present invention. FIG. 2 shows FIG.
3 is shown in an enlarged manner, and FIG. 3 is an enlarged view of the area XS in FIG. FIG. 4 is a sectional view of a memory cell array section of the NAND flash EEPROM of FIG.

FIG. 5 shows a plane pattern of a first wiring layer formed on the NAND cell unit.
Shows a planar pattern of a second wiring layer formed on the first wiring layer in FIG.

In the silicon substrate 10, STI (Shallo)
An element isolation film 49 having a (w Trench Isolation) structure is formed. In the element region surrounded by the element isolation film 49,
For example, a NAND cell unit including 16 memory cells and two select gate transistors is arranged.

Each memory cell has a floating gate electrode FG and a control gate electrode (word line) CG0 to CG0.
It has a CG 15 and an N-type diffusion layer 61. The floating gate electrode FG is composed of polysilicon films 45 and 50, and has a control gate electrode (word line) CG0.
CG15 are composed of polysilicon films 55 and 56 and a tungsten silicide film 57.

The source side select gate transistor is
Select gate electrodes SGS (top), SGS (bottom) and N
It has the mold diffusion layers 61 and 61a. The select gate electrode SGS (lower) is composed of polysilicon films 45 and 50, and the select gate electrode SGS (upper) is composed of polysilicon films 55 and 56 and a tungsten silicide film 57.

The drain-side select gate transistor also has select gate electrodes SGD (upper), SGD (lower) and N-type diffusion layers 61 and 61b. The select gate electrode SGS (bottom) is composed of polysilicon films 45 and 50, and the select gate electrode SGS (top) is composed of polysilicon films 55 and 56 and a tungsten silicide film 57.
It is composed of

Control gate electrode (word line) CG
0 to CG15, source side select gate electrode SGS
The (upper), SGS (lower) and drain-side select gate electrodes SGD (upper), SGD (lower) extend in the row direction, and the bit lines BL0 to BLk extend in the column direction.

Each of the bit lines BL0 to BLk is formed of a laminated film of, for example, a barrier metal 68 made of titanium and titanium nitride and a metal film (for example, an aluminum film) 69.
The bit lines BL0 to BLk are connected to the NAN via a wiring made of a tungsten film 66 (66B) formed immediately below.
It is connected to the diffusion layer (drain) 61b of the D cell unit. Between the tungsten film 66 and the diffusion layer 61b,
For example, a barrier metal 65 made of titanium and titanium nitride
(65B) is formed.

The dummy bit line DUMMY is connected to the bit line B
This is provided to equalize the capacitance between L0 and BLk, and is not actually used.

The source line SL is connected to the diffusion layer (source) 61a of the NAND cell unit. Source line S
L is composed of, for example, a laminated film of a barrier metal 65 (65B) made of titanium and titanium nitride and a tungsten film 66 (66A).

The source-side and drain-side select gate transistors are provided for selecting a memory cell to be written and erased at the time of data writing and erasing, respectively. Therefore, the source-side and drain-side select gate transistors are configured to perform a switching operation at a fixed threshold value, unlike the memory cells.

Therefore, in the source-side and drain-side select gate transistors, the control signal is directly applied to the first-layer select gate electrodes SGS (lower) and SGD (lower). More specifically, a part of the second-layer select gate electrodes SGS (upper) and SGD (upper) is removed, and the removed parts are replaced with first-layer select gate electrodes SGS (lower) and SGD (lower). A contact region for SGD (bottom) is formed. Contact holes SS and SD are formed on this contact region.

The hatched portions in FIGS. 2 and 3
First layer select gate electrode SGS (lower), SGD
(Bottom) indicates the portion where it exists.

Contact regions (contact holes SS,
SD) is provided every time the select gate electrode straddles several hundred bit lines in consideration of the resistance of the select gate electrode. Also, for example, the first-layer select gate electrode SGS of the source-side select gate transistor
The contact region for (lower) is provided in common to the two first-layer select gate electrodes SGS (lower) adjacent in the column direction, and the first-layer select gate electrode SGD (lower) of the drain-side select gate transistor. ) Are separately provided in the two first-layer select gate electrodes SGD (lower) adjacent in the column direction.

In the drain-side select gate transistor, the contact regions for the two first-layer select gate electrodes SGD (lower) adjacent in the column direction do not face each other (ie, both select gate electrodes SGD
GD (bottom) contact areas are arranged alternately (so that they do not come into contact with each other).

Here, the important point is that the drain side select gate transistor is opposed to the contact region for one select gate electrode SGD (lower) of two select gate electrodes SGD (lower) adjacent in the column direction. Other select gate electrode SGD
(Upper) and SGD (lower) are removed. Thereby, even if the interval between both select gate electrodes SGD (lower) is narrowed, the contact region for one select gate electrode SGD (lower) is changed to the other select gate electrode SGD.
There is no contact with D (upper) and SGD (lower).

That is, according to this example, one of the select gate electrodes SGD (upper) and SGD (lower) is cut at a portion facing the contact region with the other select gate electrode SGD (lower). Become.

Therefore, the cut select gate electrode SGD (lower) is connected to the upper layer wiring SDL1 or wiring SDL.
It is electrically connected by L2. Wiring SDL1, SD
L2 is formed in the same layer as the layer in which the source line SL is formed, and is composed of, for example, a barrier metal 65 (65C) made of titanium and titanium nitride and a tungsten film 66 (66C).

On the other hand, two select gate electrodes S adjacent to each other in the column direction of the source side select gate transistor
The contact region for GS (bottom) is formed by the wiring 66D, 9
5 (contact holes SS1 and SS2) and are commonly connected to the wiring SSL.

The wirings 66D and SSL are formed in the same layer as the layer where the source line SL is formed. For example, the wirings 66D and SSL are formed of a barrier metal 65 (65D, 65E) made of titanium and titanium nitride and a tungsten film 66 (66D, 66E). Be composed. The wiring 95 is formed in the same layer as the layer in which the bit lines BL0 to BLk are formed, and includes, for example, a barrier metal 68 made of titanium and titanium nitride and a metal film (for example, an aluminum film) 69.

FIG. 7 schematically shows a plane pattern of a memory cell array section of a NAND flash EEPROM according to a second embodiment of the present invention. FIG.
FIG. 9 shows the region XS of FIG. 7 in an enlarged manner.

FIG. 10 shows a plane pattern of a first wiring layer formed on the NAND cell unit. FIG. 11 shows a second wiring layer formed on the first wiring layer of FIG. Is shown.

The NAND flash EEP of FIG.
The cross section of the memory cell array portion of the ROM is the same as that of FIG.

In the silicon substrate 10, STI (Shallo)
An element isolation film 49 having a (w Trench Isolation) structure is formed. In the element region surrounded by the element isolation film 49,
For example, a NAND cell unit including 16 memory cells and two select gate transistors is arranged.

Each memory cell has a floating gate electrode FG and a control gate electrode (word line) CG0 to CG0.
It has a CG 15 and an N-type diffusion layer 61. The floating gate electrode FG is composed of polysilicon films 45 and 50, and has a control gate electrode (word line) CG0.
CG15 are composed of polysilicon films 55 and 56 and a tungsten silicide film 57.

The source side select gate transistor is
Select gate electrodes SGS (top), SGS (bottom) and N
It has the mold diffusion layers 61 and 61a. The select gate electrode SGS (lower) is composed of polysilicon films 45 and 50, and the select gate electrode SGS (upper) is composed of polysilicon films 55 and 56 and a tungsten silicide film 57.

The drain-side select gate transistor also has select gate electrodes SGD (upper), SGD (lower), and N-type diffusion layers 61 and 61b. The select gate electrode SGS (bottom) is composed of polysilicon films 45 and 50, and the select gate electrode SGS (top) is composed of polysilicon films 55 and 56 and a tungsten silicide film 57.
It is composed of

Control gate electrode (word line) CG
0 to CG15, source side select gate electrode SGS
The (upper), SGS (lower) and drain-side select gate electrodes SGD (upper), SGD (lower) extend in the row direction, and the bit lines BL0 to BLk extend in the column direction.

Each of the bit lines BL0 to BLk is formed of a laminated film of, for example, a barrier metal 68 made of titanium and titanium nitride and a metal film (eg, an aluminum film) 69.
The bit lines BL0 to BLk are connected to the NAN via a wiring made of a tungsten film 66 (66B) formed immediately below.
It is connected to the diffusion layer (drain) 61b of the D cell unit. Between the tungsten film 66 and the diffusion layer 61b,
For example, a barrier metal 65 made of titanium and titanium nitride
(65B) is formed.

The dummy bit line DUMMY is connected to the bit line B
This is provided to equalize the capacitance between L0 and BLk, and is not actually used.

The source line SL is connected to the diffusion layer (source) 61a of the NAND cell unit. Source line S
L is composed of, for example, a laminated film of a barrier metal 65 (65A) made of titanium and titanium nitride and a tungsten film 66 (66A).

The source-side and drain-side select gate transistors are provided for selecting a memory cell to be written and erased when writing and erasing data, respectively. Therefore, the source-side and drain-side select gate transistors are configured to perform a switching operation at a fixed threshold value, unlike the memory cells.

Thus, in the source side and drain side select gate transistors, the control signal is directly applied to the first layer select gate electrodes SGS (lower) and SGD (lower). More specifically, a part of the second-layer select gate electrodes SGS (upper) and SGD (upper) is removed, and the removed parts are replaced with first-layer select gate electrodes SGS (lower) and SGD (lower). A contact region for SGD (bottom) is formed. Contact holes SS and SD are formed on this contact region.

The hatched portions in FIGS. 8 and 9
First layer select gate electrode SGS (lower), SGD
(Bottom) indicates the portion where it exists.

The contact region (contact hole SS,
SD) is provided every time the select gate electrode straddles several hundred bit lines in consideration of the resistance of the select gate electrode. Unlike the first embodiment, the contact region of the source-side select gate transistor with respect to the first-layer select gate electrode SGS (lower) is different from the two first-layer select gate electrodes adjacent in the column direction. The contact region for the first-layer select gate electrode SGD (lower) of the drain-side select gate transistor provided separately on the gate electrode SGS (lower) also has two select gate electrodes SGD (lower) adjacent in the column direction.
Are provided separately.

In the drain side select gate transistor, the contact regions for the two first layer select gate electrodes SGD (lower) adjacent in the column direction do not face each other (ie, both select gate electrodes SGD
GD (lower) contact regions are arranged alternately (so that they do not overlap).

Similarly, with respect to the source side select gate transistor, the contact regions for the two first layer select gate electrodes SGS (lower) adjacent in the column direction do not face each other (ie, both select gate electrodes SGS). (Lower contact regions are not overlapped).

Further, regarding the drain-side select gate transistor, of the two select gate electrodes SGD (lower) adjacent in the column direction, the other select gate of the portion facing the contact region with one select gate electrode SGD (lower) Electrode SGD (top), SGD (bottom)
Has been removed. Thereby, even if the interval between both select gate electrodes SGD (lower) becomes narrow, the contact region for one select gate electrode SGD (lower) contacts the other select gate electrodes SGD (upper) and SGD (lower). There is no.

Further, regarding the source side select gate transistor, one of the two select gate electrodes SGS (lower) adjacent in the column direction is selected.
The other select gate electrodes SGS (upper) and SGS (lower) of the portion facing the contact region for GS (lower) are removed. Thereby, even if the interval between the two select gate electrodes SGS (lower) becomes narrow, the contact region for one select gate electrode SGS (lower) contacts the other select gate electrodes SGS (upper) and SGS (lower). There is no.

As described above, in this example, the select gate electrodes on the source side and the drain side are cut off at predetermined positions.

The drain-side select gate electrode thus cut is connected to the upper wiring SDL1 or SDL2.
Electrically connected by Wiring SDL1, SDL2
Are formed on the same layer as the layer on which the source line SL is formed,
For example, a barrier metal 65 made of titanium and titanium nitride
(65C) and a tungsten film 66 (66C).

On the other hand, two select gate electrodes S adjacent to each other in the column direction of the source side select gate transistor
The contact region for GS (bottom) is formed by the wiring 66D, 9
5 (contact holes SS1 and SS2) and are commonly connected to the wiring SSL.

The wirings 66D and SSL are formed in the same layer as the layer in which the source line SL is formed. For example, the wirings 66D and SSL are formed of a barrier metal 65 (65D, 65E) made of titanium and titanium nitride and a tungsten film 66 (66D, 66E). Be composed. The wiring 95 is formed in the same layer as the layer in which the bit lines BL0 to BLk are formed, and includes, for example, a barrier metal 68 made of titanium and titanium nitride and a metal film (for example, an aluminum film) 69.

FIGS. 12 and 13 show a memory cell array section of a NAND flash EEPROM according to the third embodiment of the present invention. This example is a modification of the above-described second embodiment, FIG. 12 is a modification of the plane pattern of the first wiring layer in FIG. 10, and FIG.
13 is a modification of the planar pattern of the first second wiring layer.

The NAND flash EEP of this example
The cross section of the memory cell array portion of the ROM is the same as that of FIG.

With respect to the source side select gate transistor, two select gate electrodes S adjacent in the column direction
Of the GS (upper) and SGS (lower), one of the select gate electrodes SGS (upper) and SGS (lower) is cut at a portion facing the contact region of the other select gate electrode SGS (lower).

The cut select gate electrode SG
S (lower) is an upper layer wiring SSL via a contact region.
1 or SSL2. That is, in the present example, unlike the above-described second embodiment, two select gate electrodes SGS adjacent in the column direction are used.
Wirings SSL1, (upper) and SGS (lower) different from each other
It is connected to SSL2.

Thus, in this example, it is possible to control on / off of the select gate transistors on the source and drain sides of the NAND cell unit for each block.

The wirings SSL1 and SSL2 are formed in the same layer as the layer where the source line SL is formed. For example, the barrier metal 65 (65E) made of titanium and titanium nitride is formed.
And a tungsten film 66 (66E).

According to the pattern of the memory cell array portion of the NAND type flash EEPROM according to the above-described first to third embodiments, first, regarding the two select gate electrodes adjacent in the column direction, both select gate electrodes Are arranged so as not to face each other. Further, one select gate electrode is cut at a portion facing the contact region of the other select gate electrode.

Therefore, the interval between the gate regions (line regions other than the contact region) of the two select gate electrodes adjacent in the column direction can be reduced irrespective of the size of the contact region.

Specifically, as shown in FIG. 14, the minimum width that can be processed in the photolithography process is n (for example, the interval between control gate electrodes is set to n), and the contact region is a select gate. Electrode SGD
Assuming that the length of the portion protruding in the column direction from the (lower) gate region is h, and the distance between the contact region of the select gate electrode SGD (lower) and the control gate electrode CG0 adjacent thereto is m, The distance p between the gate regions of two adjacent select gate electrodes can be reduced to a minimum value n irrespective of the size of the contact region in principle (however, it is necessary to satisfy n <m).

As a result, it is possible to reduce the size of the memory cell array section in the column direction by 9 to 10% as compared with the conventional case, to increase the storage capacity of the memory cell array section (when the area is fixed) and to reduce the memory cell array section. Can be reduced (when the storage capacity is fixed).

The select gate electrodes (first layer) cut at a plurality of locations are connected to each other by a wiring in an upper layer via a contact region. If this wiring is made of a low-resistance material, for example, a barrier metal made of titanium and titanium nitride and a tungsten film, it can contribute to lowering the resistance of the select gate electrode.

Second, in the portion where the contact region for the first-layer select gate electrode is formed, the second-layer select gate electrode is removed. In the pattern near the contact region, the length r in the column direction is larger than the gate length g of the select gate electrode (for example, the pattern is bent at 90 ° in the column direction). Also, naturally, the first-layer select gate electrode exists immediately below the second-layer select gate electrode.

Therefore, for example, as shown in FIG. 15, even if a resist misalignment occurs in the photolithography process during patterning of the contact region of the first-layer select gate electrode, the first-layer select gate Connection between electrode contact area and gate area (shown by bold line)
Is not narrowed, and the resistance value of the first-layer select gate electrode does not increase.

Next, the above-mentioned NAND flash EE
A method for manufacturing the memory cell array portion of the PROM will be described.

First, as shown in FIG. 16, a silicon oxide film 41a having a thickness of about 10 nm is formed on a p-type silicon substrate 40 by, for example, thermal oxidation.

Next, as shown in FIG. 17, an n-type impurity (for example, phosphorus (P)) is ion-implanted into the silicon substrate 40 using a mask for forming an n-well, and an n-well region 42 is formed. To form Here, the formation of the n-well region 42 is realized by, for example, three-stage ion implantation. That is, in the first stage, for example, phosphorus is ion-implanted into the silicon substrate at an acceleration energy of 1.5 [MeV] and a dose of 4.0 × 10 ¹² cm ⁻² , and in the second stage, for example, Acceleration energy of 750 [KeV], 8.0 × 10
^At a dose of ¹² cm ^-2 , phosphorus is ion-implanted into the silicon substrate. In the third step, phosphorus is implanted at an acceleration energy of, for example, 150 [KeV] and a dose of 1.0 × 10 ¹² cm ^-2. Ions are implanted into a silicon substrate.

Further, a p-type impurity (for example, boron (B)) is ion-implanted into the silicon substrate 40 using a mask for forming a p-well to form a p-well region 43. Here, the p-well region 43 is formed, for example, by 2
It is realized by ion implantation in stages. That is, in the first stage, for example, an acceleration energy of 400 [KeV];
At a dose of 0 × 10 ¹³ cm ⁻² , boron is ion-implanted into the silicon substrate.
Boron is ion-implanted into the silicon substrate at an acceleration energy of eV] and a dose of 1.0 × 10 ¹² cm ⁻² .

In p-well region 43, p-field region 44 having a higher impurity concentration than p-well region 43 is formed. After this, the silicon oxide film 41a
Is removed.

Next, as shown in FIG.
Thermal oxidation is performed in an oxygen atmosphere at a temperature of about 0 ° C. to form a silicon oxide film 41 having a thickness of about 8 nm on the silicon substrate 40. Further, for example, an n-type impurity (for example, phosphorus) is deposited on the silicon oxide film 41 by about 2 × 10 ²⁰ using the CVD method.
An n-type polysilicon film 45 having a thickness of about 60 nm including cm ^-3 is formed.

Thereafter, a silicon nitride film 46 having a thickness of about 150 nm is formed on the polysilicon film 45 by using, for example, the CVD method. Subsequently, a silicon oxide film 47 having a thickness of about 100 nm is formed on the silicon nitride film 46 by using, for example, a CVD method.

Next, as shown in FIG. 19, a resist pattern is formed on the silicon oxide film 47 by PEP (photo etching process). Using this resist pattern as a mask, the silicon oxide film 47 is etched by RIE (reactive ion etching). After the silicon nitride film 46 is etched by RIE using the silicon oxide film 47 as a mask, the silicon oxide film 47 is removed.

Thereafter, the polysilicon film 45 and the silicon oxide film 41 are sequentially etched by RIE using the silicon nitride film 46 as a mask. The silicon substrate 40 is etched using the silicon nitride film 46 as a mask.
4 are formed.

Next, as shown in FIG. 20, for example, CV
The trench 48 is formed on the silicon nitride film 46 by using the D method.
TEOS film 4 with a thickness of about 820 nm that completely satisfies
9 is formed. Thereafter, the TEOS film 49 is polished using a CMP (Chemical Mechanical Polishing) method, and the TEOS film 49 is left only in the trench 48, and the STI (Shallow Tren) is formed.
ch Isolation) Complete the structure.

Since the silicon nitride film 46 functions as an etching stopper during CMP, the TEOS film 4
9 substantially coincides with the surface of the silicon nitride film 46 (generally, the surface of the TEOS film 49 is slightly lower than the surface of the silicon nitride film 46). Thereafter, the silicon nitride film 46 is removed.

Next, as shown in FIG.
Using method D, a thickness of about 10 × 10 ²⁰ cm ⁻³ containing an n-type impurity (for example, phosphorus) is formed on the polysilicon film 45.
An 0-nm n-type polysilicon film 50 is formed.

Next, as shown in FIG.
D method, a thickness of about 200 nm is formed on the polysilicon film 50.
Is formed. The silicon nitride film 51 is patterned to form slits extending in the column direction in the silicon nitride film 51 except for the regions where the source-side and drain-side select gate transistors are formed. The width of the slit (width in the row direction)
Is 200 to 300 nm.

Further, a silicon nitride film 52 having a thickness of about 80 nm is formed on the silicon nitride film 51 by the CVD method. When the silicon nitride film 52 is etched by RIE, the silicon nitride film 52 remains only on the side wall of the slit of the silicon nitride film 51.

Thereafter, when the polysilicon film 50 is etched by RIE using the silicon nitride films 51 and 52 as a mask, a slit-shaped opening 53 is formed in the polysilicon film 50 as shown in FIG. . Here, the width of the opening 53 (the width in the row direction) is equal to T which realizes the STI structure.
Since the width (width in the row direction) of the EOS film 49 is narrower, the polysilicon film 4 serving as a floating gate
5, 50 are wing-shaped.

After this, the silicon nitride films 51 and 52
Is removed.

Next, as shown in FIG. 24, an insulating film 54 is formed on the polysilicon film 50. This insulating film 54
For example, a silicon oxide film having a thickness of about 5 nm and a thickness of about 8 nm
And a silicon oxide film having a thickness of about 5 nm (a so-called ONO film). Also, for example, CV
By the method D, about 3.6 × 10 ²⁰ cm ^{−3 is} formed on the insulating film 54.
About 200 nm in thickness containing n-type impurities (for example, phosphorus)
Is formed.

Next, as shown in FIG. 25, for example, CV
A polysilicon film 56 containing an n-type impurity and having a thickness of about 100 nm is formed on the polysilicon film 55 by using the D method. In addition, for example, a tungsten silicide (WSi) film 57 having a thickness of about 100 nm is formed on the polysilicon film 56 by using the CVD method. Then, a thickness of about 280 n is formed on the tungsten silicide film 57 by the CVD method.
An m-th silicon nitride film 58 is formed. Further, a silicon oxide film (TEOS film) 59 having a thickness of about 50 nm is formed on the silicon nitride film 58 by the CVD method.

Thereafter, by PEP (photo etching step),
A resist pattern is formed on the silicon oxide film 59, and the silicon oxide film 59 is etched by RIE using the resist pattern as a mask. Using the silicon oxide film 59 as a mask, the silicon nitride film 58 is formed by RIE.
Is etched, silicon oxide film 59 is removed.

Next, as shown in FIGS. 26 to 28, using the patterned silicon nitride film 58 as a mask,
The tungsten silicide film 57 and the polysilicon films 56 and 55 are sequentially etched by RIE. As a result, the control gate electrodes CG0 to CG0 extending in the row direction
CG15 and select gate electrode SGS (top), SGD
(Top) is completed.

Here, select gate electrode SGS
Regarding (upper) and SGD (upper), the portion where the contact region is arranged is removed, and the portion is formed in a pattern bent at 90 ° in the column direction at that portion. In the portion where the contact region is arranged, the adjacent select gate electrodes SGS (upper) and SGD (upper) are also removed.

Next, as shown in FIG. 29 to FIG.
A resist pattern 90 is formed in a portion where a contact region is to be arranged by EP. Using the resist pattern 90 and the silicon nitride film 58 as a mask,
The insulating film 54 and the polysilicon films 50 and 45 are sequentially etched. Thereby, the floating gate electrode FG extending in the row direction and the select gate electrode SGS (lower),
The SGD (bottom) (gate region and contact region) is completed. Thereafter, the resist pattern 90 is removed.

Next, as shown in FIG. 34, a silicon nitride film 58 (control gate electrode and select gate)
Is used as a mask to ion-implant an n-type impurity (phosphorus or arsenic) into the p-well region 43 by self-alignment.
The n-type diffusion layers 61, 61a, 61b are formed. The diffusion layer 61a serves as a source of the NAND cell unit,
The diffusion layer 61b becomes a drain of the NAND cell unit.

Further, for example, a silicon nitride film 60 having a thickness of about 60 nm is formed as a spacer on the side walls of the control gate electrodes CG0 to CG15, the select gate electrodes SGS, SGD, and the floating gate electrode FG by using the CVD method. .

Next, as shown in FIG. 35, a BPSG film 62 having a thickness of about 1.45 μm is formed on the silicon nitride film 60. The BPSG film 62 is polished by about 0.4 μm using a CMP method to flatten the surface of the BPSG film 62.

Next, as shown in FIG. 36 to FIG.
A silicon nitride film 91 is formed on the PSG film 62 as an etching stopper. Subsequently, a TEOS film 64 is formed on the silicon nitride film 91.

Further, a resist pattern is formed by PEP. Using this resist pattern as a mask, RIE
The TEOS film 64 is etched by
A wiring groove is formed on the substrate. At this time, the silicon nitride film 91 becomes
Functions as an etching stopper in RIE. Thereafter, the resist pattern is removed.

[0142] Again, a resist pattern is formed by PEP. Using this resist pattern as a mask, RIE
Thereby, contact holes S and D are formed in the BPSG film 62, the silicon nitride film 60, and the silicon oxide film 41 to reach the diffusion layer (source) 61a and the diffusion layer (drain) 61b. At the same time, contact holes SS and SD reaching the contact regions of the first-layer select gate electrodes SGS (lower) and SGD (lower) are formed by this RIE. Thereafter, the resist pattern is removed.

Thereafter, barrier metals 65A to 65E made of, for example, a laminate of titanium and titanium nitride are formed on the inner surface of the wiring groove and the inner surface of the contact hole. Also, TE
On the OS film 64, tungsten films 66A to 66E completely filling the wiring groove and the contact hole are formed. When the tungsten films 66A to 66E are polished by the CMP method and left only in the wiring grooves and the contact holes, the NA
Source wiring S connected to the source of the ND cell unit
L, wirings 65B and 66B connected to the drain of the NAND cell unit, and a drain-side select gate electrode SGD
Wiring SDL connected to (bottom) and other wiring 65
D, 66D, and SSL are formed.

Next, as shown in FIG. 43 to FIG.
A TEOS film 92 is formed on the EOS film 64. TEOS
On the film 92, a silicon nitride film 93 as an etching stopper is formed. Subsequently, TE on the silicon nitride film 93 is formed.
An OS film 94 is formed.

Further, a resist pattern is formed by PEP. Using this resist pattern as a mask, RIE
The TEOS film 94 is etched by
Then, wiring grooves for bit lines, dummy bit lines, and the like are formed. At this time, the silicon nitride film 93 functions as an etching stopper in RIE. Thereafter, the resist pattern is removed.

[0146] Again, a resist pattern is formed by PEP. Using this resist pattern as a mask, RIE
Thereby, a contact hole B reaching the wirings 65B and 66B and other contact holes SS1 and SS2 are formed in the silicon nitride film 93 and the TEOS film 92. Thereafter, the resist pattern is removed.

Thereafter, a barrier metal 68 made of, for example, a laminate of titanium and titanium nitride is formed on the inner surface of the wiring groove and the inner surface of the contact hole. Also, the TEOS film 94
A metal film (for example, an aluminum film) 69 that completely fills the wiring groove and the contact hole is formed thereon. When the metal film 69 is polished by the CMP method and left only in the wiring groove and the contact hole, the plurality of bit lines BL and the source-side select gate electrode SGS (lower) are connected to the wiring SSL.
A wiring 95 for connection to is formed.

Note that a passivation film made of a silicon nitride film is formed on these wirings.

Through the above manufacturing steps, a NAND flash EEPROM is completed.

[0150]

As described above, according to the nonvolatile semiconductor memory of the present invention, the following effects can be obtained.

First, with respect to two select gate electrodes (source side, drain side) adjacent in the column direction, the contact regions of both select gate electrodes are arranged so as not to face each other. Further, one select gate electrode is cut at a portion facing the contact region of the other select gate electrode.

Therefore, the interval between the gate regions (line regions other than the contact region) of the two select gate electrodes adjacent in the column direction can be reduced irrespective of the size of the contact region, and the storage capacity of the memory cell array portion And the area of the memory cell array can be reduced.

The select gate electrodes (first layer) cut at a plurality of locations are connected to each other by a wiring in an upper layer via a contact region. If this wiring is made of a low-resistance material, for example, a barrier metal made of titanium and titanium nitride and a tungsten film, it can contribute to lowering the resistance of the select gate electrode.

Second, in the portion where the contact region for the first-layer select gate electrode is formed, the second-layer select gate electrode is removed. In the pattern near the contact region, the length r in the column direction is larger than the gate length g of the select gate electrode (for example, it is bent at 90 ° in the column direction). Also, of course,
The first-layer select gate electrode is located immediately below the second-layer select gate electrode.

Therefore, even when resist misalignment occurs in the photolithography step during patterning of the contact region of the first-layer select gate electrode, the connection between the contact region and the gate region of the first-layer select gate electrode can be achieved. The portion does not become narrow, and the resistance value of the first-layer select gate electrode does not increase.

[Brief description of the drawings]

FIG. 1 shows a NAND type E according to a first embodiment of the present invention.
The figure which shows the outline of the planar pattern of EPROM.

FIG. 2 is an enlarged view showing a region XD of FIG. 1;

FIG. 3 is an enlarged view showing a region XS in FIG. 1;

FIG. 4 is a view showing a cross section of the NAND EEPROM of FIG. 1;

FIG. 5 is a view showing a plane pattern of a first wiring layer of the EEPROM of FIG. 1;

FIG. 6 is a view showing a plane pattern of a second wiring layer of the EEPROM of FIG. 1;

FIG. 7 shows a NAND type E according to a second embodiment of the present invention.
The figure which shows the outline of the planar pattern of EPROM.

FIG. 8 is an enlarged view showing a region XD in FIG. 7;

FIG. 9 is an enlarged view showing an area XS in FIG. 7;

FIG. 10 is a view showing a plane pattern of a first wiring layer of the EEPROM of FIG. 7;

FIG. 11 is a diagram showing a plane pattern of a second wiring layer of the EEPROM of FIG. 7;

FIG. 12 is an EEPRO according to a third embodiment of the present invention.
The figure which shows the plane pattern of M 1st wiring layer.

FIG. 13 shows an EEPRO according to a third embodiment of the present invention.
The figure which shows the plane pattern of M 2nd wiring layer.

FIG. 14 is a diagram showing a first effect of the present invention, that is, reduction between select gates.

FIG. 15 is a diagram showing a second effect of the present invention, that is, a decrease in resistance of a contact region.

FIG. 16 is a sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 17 is a sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 18 is a sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 19 is a sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 20 is a sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 21 is a sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 22 is a sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 23 is a sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 24 is a sectional view showing one step of a method of manufacturing an EEPROM according to the present invention.

FIG. 25 is a sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 26 is a plan view showing one step of an EEPROM manufacturing method according to the present invention.

FIG. 27 is a plan view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 28 is a sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 29 is a plan view showing one step of an EEPROM manufacturing method according to the present invention.

FIG. 30 is a plan view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 31 is a sectional view showing one step of a method of manufacturing an EEPROM according to the present invention.

FIG. 32 is a sectional view taken along the line XXXII-XXXII of FIG. 29;

FIG. 33 is a sectional view taken along the line XXXIII-XXXIII in FIG. 30;

FIG. 34 is a sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 35 is a sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 36 is a plan view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 37 is a plan view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 38 is a cross-sectional view showing one step of a method for manufacturing an EEPROM according to the present invention.

39 is a sectional view taken along the line XXXIX-XXXIX of FIG. 36.

FIG. 40 is a sectional view taken along the line XL-XL in FIG. 36;

FIG. 41 is a sectional view taken along the line XLI-XLI in FIG. 37;

FIG. 42 is a sectional view taken along the line XLII-XLII of FIG. 37;

FIG. 43 is a plan view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 44 is a plan view showing one step of a method for manufacturing an EEPROM according to the present invention.

FIG. 45 is a sectional view showing one step of a method of manufacturing an EEPROM according to the present invention;

FIG. 46 is a circuit diagram showing a configuration of a memory cell array portion of a NAND type EEPROM.

FIG. 47 is a view schematically showing a plane pattern of a NAND type EEPROM.

FIG. 48 is an enlarged view showing a region XD in FIG. 47;

FIG. 49 is an enlarged view showing a region XS in FIG. 47;

50 is a view showing a cross section of the NAND EEPROM of FIG. 47;

FIG. 51 is a view schematically showing a plane pattern of a NAND type EEPROM;

FIG. 52 is a plan view showing one step of the method for manufacturing the EEPROM.

FIG. 53 is a plan view showing one step of a method for manufacturing an EEPROM.

FIG. 54 is a sectional view taken along the line LIV-LIV in FIG. 52;

FIG. 55 is a sectional view taken along the line LV-LV in FIG. 52;

FIG. 56 is a sectional view taken along the line LVI-LVI of FIG. 52;

FIG. 57 is a sectional view taken along the line LVII-LVII of FIG. 52;

FIG. 58 is a plan view showing one step of a method for manufacturing an EEPROM.

FIG. 59 is a plan view showing one step of a method for manufacturing an EEPROM.

FIG. 60 is a sectional view taken along the line LX-LX in FIG. 58;

FIG. 61 is a sectional view taken along the line LXI-LXI in FIG. 58;

FIG. 62 is a sectional view taken along the line LXII-LXII in FIG. 58;

FIG. 63 is a sectional view taken along lines LXIII-LXIII in FIG. 58;

FIG. 64 is a sectional view taken along the line LXIV-LXIV in FIG. 58;

FIG. 65 is a sectional view taken along the line LXV-LXV in FIG. 59;

FIG. 66 is a plan view showing one step of a method for manufacturing an EEPROM.

FIG. 67 is a plan view showing one step of a manufacturing method of the EEPROM.

FIG. 68 is a sectional view taken along the line LXVIII-LXVIII in FIG. 66;

FIG. 69 is a sectional view taken along the line LXIX-LXIX of FIG. 66;

70 is a sectional view taken along the line LXX-LXX in FIG. 66.

71 is a sectional view taken along the line LXXI-LXXI of FIG. 66.

FIG. 72 is a sectional view taken along the line LXXII-LXXII of FIG. 66;

73 is a sectional view taken along the line LXXIII-LXXIII in FIG. 67.

74 is a sectional view taken along the line LXXIV-LXXIV in FIG. 67.

FIG. 75 is a sectional view taken along the line LXXV-LXXV of FIG. 67;

FIG. 76 is a sectional view taken along the line LXXVI-LXXVI of FIG. 67;

FIG. 77 is a sectional view taken along the line LXXVII-LXXVII of FIG. 67;

FIG. 78 is a plan view showing one step of a method for manufacturing an EEPROM.

FIG. 79 is a plan view showing one step of the method for manufacturing the EEPROM.

FIG. 80 is a sectional view taken along the line LXXX-LXXX of FIG. 78;

FIG. 81 is a sectional view taken along the line LXXXI-LXXXI of FIG. 78;

FIG. 82 is a sectional view taken along the line LXXXII-LXXXII of FIG. 78;

83 is a sectional view taken along the line LXXXIII-LXXXIII of FIG. 78.

84 is a sectional view taken along the line LXXXIV-LXXXIV of FIG. 79.

85 is a sectional view taken along the line LXXXV-LXXXV of FIG. 79.

86 is a sectional view taken along the line LXXXVI-LXXXVI in FIG. 79.

FIG. 87 is a sectional view taken along the line LXXXVII-LXXXVII of FIG. 79;

FIG. 88 is a view showing a distance between select gates, which is a first conventional problem.

FIG. 89 is a view showing a distance between select gates, which is a first conventional problem.

FIG. 90 is a view showing a misalignment of a contact region, which is a second conventional problem.

FIG. 91 is a view showing a misalignment of a contact region, which is a second conventional problem.

[Description of Signs] 10, 40: silicon substrate, 11: element isolation film, 12: n-type diffusion layer, 12a: source diffusion layer, 12b: drain diffusion layer, 13: gate insulating film, 14: floating gate electrode, 15 : Insulating film (ONO
16: polysilicon film; 17: silicon nitride film (mask material); 18A, 18B: resist pattern; 19: BPSG film; 20, 35, 91, 93: silicon nitride film (etching stopper), 21, 34 , 36: TEOS film, 22A to 22F, 37A, 70A: wiring groove, 23A to 23F, 37B, 70B: contact hole, 24, 26, 28, 30, 32, 38, 65, 68, 7
1: barrier metal (Ti / TiN), 25, 27, 29, 31, 33: tungsten film, 39, 69, 72: metal film, 42: n-well region, 43: p-well region, 44: p- Field regions, 45, 50, 55, 56, 63: polysilicon film, 46, 51, 52, 58, 60: silicon nitride film, 47, 59: silicon oxide film, 48: trench, 49: element isolation film (ST)
I), 64, 92, 94: TEOS film, 53: slit, 54: insulating film (ONO)
57): Tungsten silicide film, 61: N-type diffusion layer, 61a: Source diffusion layer, 61b: Drain diffusion layer, 62: BPSG film, 66, 67: Tungsten film, 95: Wiring, CG0-CG15: Control gate SGS (bottom): source-side select gate electrode of the first layer, SGD (bottom): drain-side select gate electrode of the first layer, SGS (top): source-side select gate electrode of the second layer, SGD (upper): second layer drain side select gate electrode, S, D, SS, SD, B, SS1, SS2: contact hole, BL0 to BLk, BLi: bit line, SL: source line. SSL, SSL1, SSL2: wiring connected to the source-side select gate electrode, SDL1, SDL2: wiring connected to the drain-side select gate electrode.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Kazuhiro Shimizu 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside Toshiba Yokohama Office (72) Inventor Yuji Takeuchi 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Company Toshiba Yokohama Office

Claims (12)

[Claims] 1. A semiconductor device comprising: first and second select gate electrodes adjacent to each other across a diffusion layer in a column direction and extending in a row direction, wherein the first and second select gate electrodes are respectively formed on a first conductive layer and over the first conductive layer; In the nonvolatile semiconductor memory including the second conductive layer, the first conductive layer of the first and second select gate electrodes has a plurality of contact regions for the first conductive layer, The second conductive layer of the second select gate electrode is removed on the plurality of contact regions, and the contact region of the first select gate electrode for the first conductive layer and the second select gate electrode for the first conductive layer are removed. The contact region is arranged so as not to face each other, and the second select portion of the portion of the first select gate electrode facing the contact region with respect to the first conductive layer is provided. The first and second conductive layers of the second select gate electrode are removed, and the first and second conductive layers of the first select gate electrode in a portion facing a contact region of the second select gate electrode with the first conductive layer are removed. A nonvolatile semiconductor memory characterized by the following. 2. A contact region of the first select gate electrode with respect to a first conductive layer is commonly connected to a first wiring on the first select gate electrode, and a contact region of the second select gate electrode with respect to the first conductive layer. 2. The nonvolatile semiconductor memory according to claim 1, wherein the contact region is commonly connected to a second wiring on the second select gate electrode. 3. A contact region of the first and second select gate electrodes with respect to a first conductive layer is commonly connected to a wiring on the first and second select gate electrodes. 2. The nonvolatile semiconductor memory according to 1. 4. A NAND circuit comprising a plurality of memory cells connected in series, wherein the first and second select gate electrodes are NAND.
2. The nonvolatile semiconductor memory according to claim 1, wherein a select gate transistor connected to one end of the column on the drain side is formed. 5. A NAND circuit comprising a plurality of memory cells connected in series, wherein the first and second select gate electrodes are NAND.
2. The nonvolatile semiconductor memory according to claim 1, wherein a select gate transistor connected to one end on the source side of the column is formed. 6. The nonvolatile semiconductor memory according to claim 4, wherein an interval between said first and second select gate electrodes is substantially equal to an interval between a plurality of control gate electrodes of said plurality of memory cells. . 7. The contact region of the first select gate electrode with respect to a first conductive layer and the contact region of the second select gate electrode with respect to a first conductive layer are arranged at regular intervals. Item 7. The nonvolatile semiconductor memory according to Item 1. 8. The nonvolatile semiconductor memory according to claim 1, wherein a length of said plurality of contact regions in a column direction is longer than a gate length of said first and second select gate electrodes. 9. A semiconductor device comprising first and second select gate electrodes adjacent to each other in the column direction with the diffusion layer interposed therebetween and extending in the row direction, wherein the first and second select gate electrodes are respectively formed on the first conductive layer and on the first conductive layer. In the nonvolatile semiconductor memory including the second conductive layer, the first conductive layer of the first and second select gate electrodes has a plurality of contact regions for the first conductive layer, In at least one of the second select gate electrodes, the second conductive layer is removed on the plurality of contact regions, and the length of the plurality of contact regions in the column direction is equal to that of the first and second select gate electrodes. A non-volatile semiconductor memory configured to be longer than a gate length. 10. The semiconductor memory according to claim 9, wherein said second conductive layer has a pattern bent in a column direction on said contact region. 11. The contact region of the first select gate electrode for the first conductive layer and the contact region of the second select gate electrode for the first conductive layer are arranged so as not to face each other. The semiconductor memory according to claim 9. 12. A portion of the second select gate electrode which faces a contact region with respect to a first conductive layer of the second select gate electrode.
The first and second conductive layers of the select gate electrode are removed, and the first and second conductive layers of the first select gate electrode in a portion facing a contact region of the second select gate electrode with the first conductive layer are removed. The nonvolatile semiconductor memory according to claim 11, wherein: