JPH11297088A - Nonvolatile semiconductor memory and method of rewriting data in nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the erase characteristics from varying between memory cells with preventing the gate insulation film deterioration. SOLUTION: The nonvolatile semiconductor memory has composite gate electrodes having a gate insulation film 4, floating gate electrodes 5, gate insulation film 6 and control gate electrodes 7 laminated on a substrate 1 and sources and drains 2, 3 formed at both sides of the composite gate electrodes and comprises voltage applying means for applying voltages between the control gate electrodes 7, sources and drains 2, 3 so as to tunnel-discharge electrons from the floating gate electrodes 5 through the gate insulation film 4 on overlapped regions of the sources 2 or drains 3 and floating gate electrodes 5 after applying voltages between the control gate electrodes 7 and substrate 1 so as to tunnel-discharge electrons from the floating gate electrode 5 through the gate insulation film 4 on channel regions in the case of discharging electrons stored on the floating gate electrodes 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a data rewriting method thereof, and more particularly, to a first gate insulating film, a floating gate electrode, and a second gate insulating film on one main surface of a semiconductor substrate. A film, a composite gate electrode in which control gate electrodes are sequentially stacked, and a source and a drain formed on the surface of the semiconductor substrate on both sides of the composite gate electrode,
And a data rewriting method for the same.

[0002]

2. Description of the Related Art The structure of a nonvolatile semiconductor memory device having a floating gate electrode will be described with reference to FIG. As shown in FIG. 1, on a P-type semiconductor substrate 1, a first gate oxide film 4 having a thickness of about 100 angstroms, a floating gate electrode 5 made of a first polycrystalline silicon, and an ONO (Oxide-Ni
tride-Oxide) with a three-layer structure, equivalent to an oxide film of about 200
A composite gate electrode in which a second gate insulating film 6 of angstrom and a control gate electrode 7 made of a second polycrystalline silicon are sequentially laminated, and the P-type semiconductor substrate 1 on both sides of the composite gate electrode has N ^A memory cell is configured to have a source 2 and a drain 3 made of a ⁺ type diffusion layer.

[0003]

In a nonvolatile memory device having a floating gate electrode having the above-described structure, conventional data erasing is performed by an erasing load such as a PMOS transistor connected to the source 2 as shown in FIG. For example, 5 V is applied to the device, the drain 3 is floated, and the control gate electrode 7
For example, a voltage of −10 V is applied to the floating gate electrode 5, and a relatively high erase voltage is applied between the floating gate electrode 5 and the source 2. The erase voltage is accumulated in the floating gate electrode by the Fowler-Nordheim tunnel (hereinafter, referred to as FN tunnel) effect. Electrons were emitted to the source (hereinafter referred to as source-gate erasure).

In addition, a PMOS transistor is generally used as an erase load element connected to a source.

FIG. 4 is a characteristic diagram showing a load PMOS characteristic and a source voltage-source current characteristic of a cell.

The actual voltage applied to the source of the cell array at the time of erasing is determined by the intersection Q of the current-voltage characteristics of the load PMOS transistor and the cell source current. When a positive voltage is applied to the source when the potential of the electrode is negative, the source region is deeply depleted in the overlap region with the floating gate electrode, and a large amount of interband tunnel current flows.

When the erase current is large, the voltage applied to the cell source becomes low due to the current-voltage characteristics of the load PMOS transistor and the cell source current. As the erase proceeds and the potential of the floating gate electrode rises, the erase current due to band-to-band tunneling increases The erasing voltage is controlled so as to be lower and the erasing voltage is higher.

It is important to control the source voltage to be low at the initial stage of erasing. Therefore, the generation of holes due to band-to-band tunneling near the source is suppressed, and the deterioration of the first gate insulating film due to hole injection is suppressed. However, there is an effect of preventing deterioration of reliability such as data retention characteristics.

However, the voltage between the source and the control gate at the time of erasing cannot be made sufficiently low in consideration of the erasing time. In fact, hole injection by the interband tunnel cannot be completely suppressed. At present, deterioration of the insulating film is inevitable.

As another erasing method, in order to completely suppress the band-to-band tunnel near the source at the time of erasing, no voltage is applied to the source at the time of erasing, and a voltage is applied between the control gate and the substrate at the time of erasing. (Hereinafter referred to as channel erasure) has been proposed in which electrons in the floating gate electrode are emitted to the substrate by FN tunneling in the channel region.

In this channel erasing, the substrate does not become deeply depleted at the time of erasing, the generation of holes by the interband tunnel is completely suppressed, and the deterioration of the first gate insulating film due to the erasing can be suppressed.

However, in this channel erasing, since the FN tunnel is performed over the entire channel region, the tunnel area becomes wider than that of the source erasing or the source-gate erasing.
There is a problem in that defects such as weak spots in the tunnel region are easily picked up, and the variation in erase characteristics between memory cells tends to increase.

[0013]

In a nonvolatile semiconductor memory device according to the present invention, a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode are formed on one main surface of a semiconductor substrate. An operation of emitting electrons accumulated in the floating gate electrode in a nonvolatile semiconductor memory device having a sequentially stacked composite gate electrode and sources and drains formed on the surface of the semiconductor substrate on both sides of the composite gate electrode When performing a, after applying a voltage between the control gate electrode and the semiconductor substrate, so as to cause the tunneling emission of electrons from the floating gate electrode through the first gate insulating film on the channel region, Tunnel emission of electrons from the floating gate electrode via the first gate insulating film on an overlap region between the source or drain and the floating gate electrode Thereby manner, the control gate electrode and the source or characterized by having a voltage applying means for applying a voltage between the drain.

According to a data rewriting method for a nonvolatile semiconductor memory device of the present invention, a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode are sequentially laminated on one main surface of a semiconductor substrate. In a data rewriting method for a nonvolatile semiconductor memory device having a composite gate electrode formed, and a source and a drain formed on the surface of the semiconductor substrate on both sides of the composite gate electrode, wherein the electrons accumulated in the floating gate electrode are released. When performing an operation, electrons are tunnel-emitted from the floating gate electrode through the first gate insulating film on the channel region, and then the source or drain and the floating gate electrode are overlapped on the floating region. Electrons are tunnel-emitted from the floating gate electrode via the first gate insulating film.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

The structure of a nonvolatile memory cell having a floating gate electrode according to the present invention will be described with reference to FIG. As shown in FIG. 1, on a P-type semiconductor substrate 1, a first gate oxide film 4 having a thickness of about 100 Å, a floating gate electrode 5 made of first polycrystalline silicon, and an ONO (Oxide-
Nitride-Oxide) has a three-layer structure, equivalent to an oxide film of about 20
A composite gate electrode in which a second gate insulating film 6 of 0 Å and a control gate electrode 7 made of a second polycrystalline silicon are sequentially laminated, and the P-type semiconductor substrate on both sides of the composite gate electrode 1 has a source 2 and a drain 3 made of an N ⁺ type diffusion layer to form a memory cell.

In the initial state where electrons are not injected into the floating gate electrode 5, the threshold value of the memory cell is P
Although it depends on the type impurity concentration, it is usually set to about 3V.

Next, the operation of the nonvolatile memory cell will be described. The data erasing operation is described with reference to FIGS.
This will be described with reference to FIG.

For data reading, 1 V is applied to the drain, 0 V is applied to the source, and 5 V is applied to the control gate electrode. As a result, data “0” or “1” is obtained depending on the presence or absence of electrons in the floating gate electrode.

For data writing, for example, about 6 V is applied to the drain, 0 V is applied to the source, and 1 is applied to the control gate electrode.
When 2 V is applied, impact ionization occurs near the drain, electrons are injected into the floating gate electrode, and data is written. The electrons are sufficiently accumulated in the floating gate electrode, and the threshold value of the memory cell is set to a high level of, for example, 7V.

On the other hand, in the data erasing method, electrons are emitted from the floating gate electrode and the threshold is set to a low level of, for example, 3V. As shown in (a), the source 2 and the drain 3 are in a floating state, the substrate is grounded to 0 V, a negative voltage of, for example, -20 V is applied to the control gate electrode 7, and the floating gate electrode 5 is Next, channel erasure for emitting electrons through the first gate oxide film 4 by FN tunneling is performed.

Then, when the erasing progresses to some extent and the threshold value drops to, for example, 5 V, as shown in FIG. 2B, a voltage of, for example, -10 V is applied to the control gate electrode 7 and a voltage of, for example, 5 V is applied to the source 2. In the overlap region between the floating gate electrode 5 and the source 2, electrons are emitted through the first gate oxide film 4 through the FN tunnel to perform source-gate erasure, and a desired low threshold level, for example, 3 V Erase up to

As described above, in the initial stage of erasing when the erasing electric field applied to the first gate oxide film 4 becomes the highest, the floating gate is formed by channel erasing in which injection of holes into the first gate oxide film 4 is suppressed. Electrons are emitted from the electrodes by FN (Fig. 2
(A)) By performing source-gate erasure in the middle of erasure (FIG. 2 (b)), the FN tunnel region of erasure is limited to a small floating gate-source overlap region, and the first gate oxide film is formed. Defects are less likely to be included in the tunnel region, and variations in erasure can be suppressed.

In another embodiment of the present invention, for example, -1 is applied to the control gate electrode at the stage of channel erasing at the initial stage of erasing.
2 V may be applied and 8 V may be applied to the substrate to distribute the potential difference between the control gate electrode and the substrate.

In the present embodiment described above, the operation of releasing electrons stored in the floating gate electrode has been described as the data erasing operation. However, the operation of releasing the electrons stored in the floating gate electrode is referred to as the data writing operation. You can also catch it.

[0026]

As described above, according to the present invention,
Since deterioration of the first gate oxide film due to hole injection at the time of erasing can be suppressed, the data retention characteristics of the non-volatile memory device are improved, and variation in the threshold value of the memory cell after erasing is suppressed, and the data is stably stored. A non-volatile memory device that can be manufactured can be obtained.

The reason is that in the initial stage of erasing when the erasing electric field applied to the first gate oxide film is the highest, the injection of holes into the first gate oxide film is suppressed by the channel erasing, whereby electrons from the floating gate electrode are removed. Is released to FN and the source-gate erasure is performed in the middle of the erasure, so that the FN tunnel region of the erasure is limited to a small overlap region between the floating gate and the source, and the defect of the first gate oxide film is included in the tunnel region. This is because it becomes difficult to suppress erasure variation.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a nonvolatile semiconductor device having a floating gate electrode.

FIGS. 2A and 2B are diagrams illustrating the operation of the nonvolatile semiconductor device of the present invention.

FIG. 3 is a diagram illustrating an operation of a conventional nonvolatile semiconductor device.

FIG. 4 is a characteristic diagram showing a load PMOS characteristic and a source voltage-source current characteristic of a cell.

[Explanation of symbols]

 Reference Signs List 1 P-type semiconductor substrate 2 Source 3 Drain 4 First gate oxide film 5 Floating gate electrode 6 Second gate insulating film 7 Control gate electrode

Claims (6)

[Claims] 1. A composite gate electrode in which a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode are sequentially laminated on one main surface of a semiconductor substrate, and both sides of the composite gate electrode. A non-volatile semiconductor memory device having a source and a drain formed on the surface of the semiconductor substrate, wherein when performing an operation of discharging electrons accumulated in the floating gate electrode, the first gate on a channel region After applying a voltage between the control gate electrode and the semiconductor substrate so as to cause electrons to tunnel from the floating gate electrode via an insulating film, an overlap region between the source or drain and the floating gate electrode The first on
A voltage applying means for applying a voltage between the control gate electrode and the source or the drain so that electrons are emitted from the floating gate electrode through the gate insulating film. Storage device. 2. The non-volatile semiconductor memory device according to claim 1, wherein the operation of discharging the electrons stored in the floating gate electrode is a data erasing operation. 3. The non-volatile semiconductor memory device according to claim 1, wherein the operation of discharging the electrons stored in the floating gate electrode is a data write operation. 4. A composite gate electrode in which a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode are sequentially laminated on one main surface of a semiconductor substrate, and both sides of the composite gate electrode. A data rewriting method for a nonvolatile semiconductor memory device having a source and a drain formed on the surface of the semiconductor substrate, wherein when performing an operation of discharging electrons accumulated in the floating gate electrode, After electrons are tunnel-emitted from the floating gate electrode through the first gate insulating film, the floating through the first gate insulating film on the overlap region between the source or drain and the floating gate electrode is performed. A data rewriting method for a nonvolatile semiconductor memory device, wherein electrons are emitted from a gate electrode by tunnel emission. 5. The data rewriting method for a nonvolatile semiconductor memory device according to claim 4, wherein the operation of discharging electrons accumulated in the floating gate electrode is a data erasing operation. A method for rewriting data in a semiconductor memory device. 6. The method according to claim 4, wherein the operation of discharging the electrons stored in the floating gate electrode is a data write operation. A method for rewriting data in a semiconductor memory device.