JPH11297746A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH11297746A
JPH11297746A JP10094915A JP9491598A JPH11297746A JP H11297746 A JPH11297746 A JP H11297746A JP 10094915 A JP10094915 A JP 10094915A JP 9491598 A JP9491598 A JP 9491598A JP H11297746 A JPH11297746 A JP H11297746A
Authority
JP
Japan
Prior art keywords
bonding
pad
wire
chip
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10094915A
Other languages
Japanese (ja)
Inventor
Manabu Kondo
学 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP10094915A priority Critical patent/JPH11297746A/en
Publication of JPH11297746A publication Critical patent/JPH11297746A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07553—Controlling the environment, e.g. atmosphere composition or temperature changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5366—Shapes of wire connectors the bond wires having kinks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】 【課題】ＩＣチップのパッケージングに関して、従来の
ワイヤーボンディング方法にて微細パッドピッチあるい
は、面積の小さいパッド電極とのワイヤーボンディング
接合信頼性を向上させることを目的とする。 【解決手段】ＩＣ電極形状を従来のフラットなものから
凹型部分を形成させることにより、ワイヤーボンディン
グとの接合面積を向上させることにより、ボンディング
強度が向上する。また凹型パッドにボンディングワイヤ
ーを埋め込む形で結線することにより、隣間のボンディ
ングどうしが接触する危険を回避させることが可能とな
り、従来技術のままでボンディング接合信頼性を低下さ
せることなく微細パッドピッチのＩＣにも対応すること
ができる。 【効果】その課題は微細パッドピッチ及び、パッド面積
の小さいＩＣチップとのボンディング接合信頼性を向上
させることにある。 (57) Abstract: An object of the present invention is to improve the reliability of wire bonding bonding with a fine pad pitch or a pad electrode having a small area by a conventional wire bonding method with respect to packaging of an IC chip. A bonding strength is improved by forming a concave portion from a conventional flat shape of an IC electrode to improve a bonding area with wire bonding. Also, by embedding the bonding wire in the recessed pad, it is possible to avoid the risk of contact between adjacent bondings, and it is possible to reduce the fine pad pitch without deteriorating the bonding reliability with the conventional technology. It can also handle ICs. The object is to improve the reliability of bonding bonding with an IC chip having a small pad pitch and a small pad area.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置(以下Ｉ
Ｃと呼ぶ)をパッケージングする際に外部リードとの結
線に使用されるワイヤーボンディングとの接合信頼性を
向上しうる構造に関するものである。The present invention relates to a semiconductor device (hereinafter referred to as I).
(Referred to as "C") when packaging is used, which can improve the bonding reliability with wire bonding used for connection with external leads.

【０００２】[0002]

【従来の技術】従来のＩＣパッドは、図１のような構造
をしていて、フラットなパッド表面１０２にボンディン
グワイヤー１０３が結線されている。2. Description of the Related Art A conventional IC pad has a structure as shown in FIG. 1, and a bonding wire 103 is connected to a flat pad surface 102.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、従来の
構造では、配線の微細化に伴う多ピン化が進む一方でＩ
Ｃチップの小型化に伴いパッドピッチ及びパッド面積は
縮小される傾向にあり、これに伴うボンディング接合面
積の縮小化により、ボンディングの接合信頼性が低下す
るという問題を有していた。However, in the conventional structure, the number of pins has been increased with the miniaturization of the wiring, but the number of pins has been increased.
The pad pitch and the pad area tend to be reduced with the miniaturization of the C chip, and there has been a problem that the bonding reliability of bonding is reduced due to the reduction in the bonding area.

【０００４】そこで本発明は上記問題点を解決するもの
であり、その課題は微細パッドピッチ及び、パッド面積
の小さいＩＣチップとのボンディング接合信頼性を向上
させることにある。Accordingly, the present invention has been made to solve the above problems, and has as its object to improve the reliability of bonding bonding with an IC chip having a small pad pitch and a small pad area.

【０００５】[0005]

【課題を解決するための手段】本電子部品は、上記問題
を解決するためにパッド構造を凹型に形成し、この凹部
側面にもパッド表面材質を形成させることによって、全
体のパッド表面積が大きくなるよう構成したものであ
る。In order to solve the above problem, the present electronic component has a pad structure formed in a concave shape, and a pad surface material is formed on the side surface of the concave portion, so that the entire pad surface area is increased. The configuration is as follows.

【０００６】[0006]

【作用】本発明の電子部品は、パッド表面積を縮小する
ことなく、パッドピッチ及びパッド開口面積を減らすこ
とが可能となり、ワイヤーボンディングの接合信頼性の
向上が図られ、ＩＣ部品自体の寿命に有利となる。According to the electronic component of the present invention, the pad pitch and the pad opening area can be reduced without reducing the pad surface area, the bonding reliability of wire bonding is improved, and the life of the IC component itself is improved. Becomes

【０００７】[0007]

【発明の実施の形態】次に、本発明に関わる実施例を図
面を用いて説明する。Next, embodiments of the present invention will be described with reference to the drawings.

【０００８】（第１実施例）まず、本発明の第一実施例
を図２から図３を参照して説明する。図２を参照すると
ＩＣパッドに相当する部分が一部凹型となるようなＩＣ
チップを作製する。ここで図３を参照してパッケージン
グの際にはボール形成したボンディングワイヤーを一部
凹型に形成されたパッドに埋め込むように圧着し外部端
子との接続をおこなう。このとき金属ワイヤーのファー
ストボンディング部分では、パッドの表面かつ底面のみ
ならず凹部側面とも合金化が促進することによって、ボ
ンディングの接合総面積が増加し接合強度が向上する。(First Embodiment) First, a first embodiment of the present invention will be described with reference to FIGS. Referring to FIG. 2, an IC in which a portion corresponding to an IC pad is partially concave.
Make a chip. Here, referring to FIG. 3, during packaging, a bonding wire formed into a ball is pressure-bonded so as to be embedded in a pad formed in a partially concave shape, and connection with an external terminal is performed. At this time, in the first bonding portion of the metal wire, alloying is promoted not only on the surface and the bottom surface of the pad but also on the side surface of the concave portion, so that the total bonding area is increased and the bonding strength is improved.

【０００９】（第２実施例）次に、図４から図５を参照
して本発明に関わる第２実施例を説明する。まず図４を
参照して説明するとＩＣパッドに相当する部分において
複数凹型（ディンプル状態）となるようなＩＣチップを
作製する。ここで図５を参照してパッケージングの際に
はボール形成したボンディングワイヤーを複数凹型に形
成されたパッドに埋め込むように圧着し外部端子との接
続をおこなう。このときボンディングワイヤーのファー
ストボンディング部分では、パッドの表面かつ底面のみ
ならず複数の凹部側面とも合金化が促進することによっ
て、ボンディングの接合総面積が増加し接合強度が向上
する。(Second Embodiment) Next, a second embodiment according to the present invention will be described with reference to FIGS. First, referring to FIGS. 4A and 4B, an IC chip having a plurality of concaves (dimple state) in a portion corresponding to an IC pad is manufactured. Here, referring to FIG. 5, at the time of packaging, a bonding wire formed in a ball is pressure-bonded so as to be embedded in a pad formed in a plurality of concave shapes, and connection with an external terminal is performed. At this time, in the first bonding portion of the bonding wire, the alloying is promoted not only on the surface and the bottom surface of the pad but also on the side surfaces of the plurality of concave portions, so that the total bonding area of bonding is increased and the bonding strength is improved.

【００１０】（第３実施例）次に、図６から図７を参照
して本発明に関わる第３実施例を説明する。まず、図６
を参照して説明するとＩＣパッドに相当する部分が全体
に凹型となるようなＩＣチップを作製する。ここで図７
を参照してパッケージングの際にはボール形成したボン
ディングワイヤーを凹型に形成されたパッドに全て埋め
込むように圧着し外部端子との接続をおこなう。このと
き金属ワイヤーのファーストボンディング部分では、パ
ッド底面及び凹部側面とも合金化が促進することによっ
て、ボンディングの接合総面積が増加し接合強度が向上
する。またファーストボールは全体が凹部パッドに埋め
込まれる形状になることから、隣間パッドのボンディン
グワイヤー（もしくはファーストボール）と接触する危
険を回避することも可能であることから、従来までのワ
イヤーボンディング技術で容易にパッドピッチの微細化
に対応することが可能である。(Third Embodiment) Next, a third embodiment according to the present invention will be described with reference to FIGS. First, FIG.
The IC chip is manufactured such that the portion corresponding to the IC pad is entirely concave. Here, FIG.
At the time of packaging, a bonding wire formed in a ball is crimped so as to be buried in a pad formed in a concave shape, and connection with an external terminal is performed. At this time, in the first bonding portion of the metal wire, alloying is promoted on both the pad bottom surface and the concave side surface, so that the total bonding area increases and the bonding strength is improved. Also, since the first ball is entirely embedded in the concave pad, it is possible to avoid the danger of contact with the bonding wire (or first ball) of the adjacent pad. It is possible to easily cope with miniaturization of the pad pitch.

【００１１】[0011]

【発明の効果】こうして凹型パッドに結線されたワイヤ
ーボンディングは、従来のワイヤーボンディング技術の
ままでさらなる微細パッドピッチＩＣに対応することが
可能でありかつボンディング接合信頼性を向上させるこ
とができるため、部品全体の寿命を延ばすことが可能と
なる。As described above, the wire bonding connected to the concave pad can cope with a finer pad pitch IC with the conventional wire bonding technology and can improve the bonding bonding reliability. It is possible to extend the life of the entire part.

【図面の簡単な説明】[Brief description of the drawings]

【図１】従来から使用されているＩＣチップと外部端子
への結線方法を示す概念図である。FIG. 1 is a conceptual diagram showing a conventionally used IC chip and a method of connecting to an external terminal.

【図２】第１実施例に基づいた本発明の電子部品を製造
するために使用するＩＣチップ電極（パッド部分）の断
面図を示したものである。FIG. 2 is a sectional view of an IC chip electrode (pad portion) used to manufacture the electronic component of the present invention based on the first embodiment.

【図３】第１実施例に基づいた本発明の電子部品を製造
するために使用するＩＣチップ電極（パッド部分）及び
ボンディングワイヤー結線状態の断面図を示したもので
ある。FIG. 3 is a cross-sectional view of an IC chip electrode (pad portion) used to manufacture the electronic component of the present invention based on the first embodiment and a bonding wire connection state.

【図４】第２実施例に基づいた本発明の電子部品を製造
するために使用するＩＣチップ電極（パッド部分）の断
面図を示したものである。FIG. 4 is a cross-sectional view of an IC chip electrode (pad portion) used to manufacture an electronic component of the present invention based on a second embodiment.

【図５】第２実施例に基づいた本発明の電子部品を製造
するために使用するＩＣチップ電極（パッド部分）及び
ボンディングワイヤー結線状態の断面図を示したもので
ある。FIG. 5 is a sectional view showing an IC chip electrode (pad portion) used for manufacturing an electronic component of the present invention based on a second embodiment and a bonding wire connection state.

【図６】第３実施例に基づいた本発明の電子部品を製造
するために使用するＩＣチップ電極（パッド部分）の断
面図を示したものである。FIG. 6 is a cross-sectional view of an IC chip electrode (pad portion) used to manufacture an electronic component of the present invention based on a third embodiment.

【図７】第３実施例に基づいた本発明の電子部品を製造
するために使用するＩＣチップ電極（パッド部分）及び
ボンディングワイヤー結線状態の断面図を示したもので
ある。FIG. 7 is a sectional view showing an IC chip electrode (pad portion) used for manufacturing an electronic component of the present invention based on a third embodiment and a bonding wire connection state.

【符号の説明】[Explanation of symbols]

１０１・・・・・ＩＣチップ １０２・・・・・ＩＣチップ電極（パッド） １０３・・・・・ボンディングワイヤー １０４・・・・・外部端子 ２０１・・・・・一部凹型電極 ３０１・・・・・一部凹型電極に結線したボンディング
ワイヤー ４０１・・・・・複数凹型（ディンプル）電極 ５０１・・・・・複数凹型（ディンプル）電極に結線し
たボンディングワイヤー ６０１・・・・・完全凹型電極 ７０１・・・・・完全凹型電極に結線したボンディング
ワイヤー101: IC chip 102: IC chip electrode (pad) 103: Bonding wire 104: External terminal 201: Partially concave electrode 301: .. Bonding wire 401 connected to partially concave electrode 401 Bonding wire connected to multiple concave (dimple) electrode 601 Completely concave electrode 701 ..... Bonding wires connected to completely concave electrodes

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】ＩＣチップにおいて凹型の電極(パッド)を
形成させることによりパッド表面積の増大がなされてい
ることを特徴とする半導体装置。1. A semiconductor device wherein the surface area of a pad is increased by forming a concave electrode (pad) on an IC chip. 【請求項２】ＩＣチップにおいて凹型の電極(パッド)を
形成させることにより埋め込み方式のワイヤーボンディ
ングを可能とすることを特徴とする半導体装置。2. A semiconductor device wherein a recessed electrode (pad) is formed on an IC chip to enable wire bonding of an embedded method.
JP10094915A 1998-04-07 1998-04-07 Semiconductor device Withdrawn JPH11297746A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10094915A JPH11297746A (en) 1998-04-07 1998-04-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10094915A JPH11297746A (en) 1998-04-07 1998-04-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH11297746A true JPH11297746A (en) 1999-10-29

Family

ID=14123308

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10094915A Withdrawn JPH11297746A (en) 1998-04-07 1998-04-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH11297746A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1494280A1 (en) * 2003-07-01 2005-01-05 STMicroelectronics, Inc. System and method for increasing the strength of a bond made by a small diameter wire in a ball bonding
EP2339622A1 (en) * 2009-12-23 2011-06-29 Nxp B.V. Wirebonding Process

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1494280A1 (en) * 2003-07-01 2005-01-05 STMicroelectronics, Inc. System and method for increasing the strength of a bond made by a small diameter wire in a ball bonding
JP2005026691A (en) * 2003-07-01 2005-01-27 Stmicroelectronics Inc System and method for increasing the strength of bonds composed of small diameter wires in ball bonding
US6908787B2 (en) 2003-07-01 2005-06-21 Stmicroelectronics, Inc. System and method for increasing the strength of a bond made by a small diameter wire in ball bonding
US7265452B2 (en) 2003-07-01 2007-09-04 Stmicroelectronics, Inc. System and method for increasing the strength of a bond made by a small diameter wire in ball bonding
US7482260B2 (en) 2003-07-01 2009-01-27 Stmicroelectronics, Inc. System and method for increasing the strength of a bond made by a small diameter wire in ball bonding
EP2339622A1 (en) * 2009-12-23 2011-06-29 Nxp B.V. Wirebonding Process

Similar Documents

Publication Publication Date Title
US8035221B2 (en) Clip mount for integrated circuit leadframes
US8089141B1 (en) Semiconductor package having leadframe with exposed anchor pads
JP3913134B2 (en) Bump forming method and bump
US7579674B2 (en) Semiconductor package configuration with improved lead portion arrangement
US7948068B2 (en) Semiconductor device having a chip mounting portion and a plurality of suspending leads supporting the chip mounting portion and each suspension lead having a bent portion
US5708304A (en) Semiconductor device
US20030104655A1 (en) Semiconductor integrated circuit package, semiconductor apparatus provided with a plurality of semiconductor integrated circuit packages, method of inspecting semiconductor integrated circuit package and method of fabricating semiconductor integrated circuit package
JPH1187556A (en) Semiconductor device
JPH11297746A (en) Semiconductor device
JP3614738B2 (en) Resin-sealed semiconductor device
JP2005311099A (en) Semiconductor device and manufacturing method thereof
JP2000196005A (en) Semiconductor device
JP2001267484A (en) Semiconductor device and method of manufacturing the same
JP2000021920A (en) Semiconductor device
US6744140B1 (en) Semiconductor chip and method of producing the same
JPH08111432A (en) Semiconductor device and manufacturing method thereof
JP2005135938A (en) Semiconductor device and manufacturing method thereof
JP2577879B2 (en) Semiconductor device
JP3153185B2 (en) Semiconductor device
JP2018137315A (en) Lead frame and semiconductor device
KR20020024654A (en) Stacking -type semiconductor package unit and stacking-type semiconductor package
JP2023108665A (en) Lead frame and semiconductor device using it
JPH08250624A (en) Semiconductor device and manufacturing method thereof
JPH0684993A (en) Semiconductor device
JPH01206652A (en) Semiconductor device

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20050607