JPH11312736A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] [Problem] To obtain analysis information of a semiconductor chip easily and in a short time without disassembling a package. SOLUTION: In a probe inspection step or the like, fuses FN1 to FNn and FM1 to FMm are cut by a laser or the like, and a semiconductor wafer coordinate in the X direction consisting of N-bit data and a semiconductor wafer in the Y direction consisting of M-bit data. Set the coordinates. At the time of failure analysis or the like, by inputting a test signal from a predetermined external pin, the shift register SR outputs these N + M bits of data as analysis information via a predetermined external pin in synchronization with the clock signal CK. .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique which is effective when applied to detection of arrangement information of individual semiconductor chips.

[0002]

2. Description of the Related Art According to studies made by the present inventor, each semiconductor chip has a coordinate position on a semiconductor wafer, for example, formed on an insulating film on the surface of the semiconductor chip. When analyzing a semiconductor device such as an electrical characteristic or a yield in a circuit device manufacturing process, a characteristic correlation between a semiconductor wafer position and a product semiconductor integrated circuit device by examining its position coordinates, that is, The distribution of the processing status of the semiconductor wafer is obtained.

As an example which describes in detail the failure analysis of this type of semiconductor integrated circuit device, see “Latest LSI Process Technology” published by the Industrial Research Institute, Inc. on May 25, 1985, Kazuo Maeda (author). P527-P53
This document describes a method for analyzing reliability failure in a semiconductor integrated circuit device.

[0004]

However, it has been found by the present inventor that the above-described semiconductor chip position display has the following problems.

That is, since the position information of the semiconductor chip is formed on the surface of the semiconductor chip, in the case of a semiconductor integrated circuit device as a product, the resin-sealed package must be disassembled, and the analysis becomes difficult. It ’s been a long time,
There is a problem that efficiency is deteriorated.

In analyzing the electrical characteristics and the yield in the manufacturing process of a semiconductor integrated circuit device, the package of the semiconductor integrated circuit device must be disassembled.
Since it is not possible to analyze a large number of products, it may be difficult to obtain data such as the distribution of the processing state of the semiconductor wafer in the manufacturing process.

An object of the present invention is to provide a semiconductor integrated circuit device capable of easily and quickly obtaining analysis information such as arrangement information on individual semiconductor chips without disassembling a package. is there.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor integrated circuit device of the present invention electrically stores the analysis information and outputs the analysis information to the second external lead line based on the analysis signal input from the first external lead line. An analysis information storage means is provided.

Further, in the semiconductor integrated circuit device according to the present invention, the analysis information storage means includes an information storage unit for storing the analysis information, and an analysis unit for outputting the analysis information stored in the information storage unit based on a control signal. An information output unit for detecting an analysis signal input from the first external lead line, controlling the analysis information output unit, and outputting the analysis information output from the analysis information output unit to the second external lead line And a signal detection unit that performs the operation.

Further, according to the semiconductor integrated circuit device of the present invention,
The analysis information storage means includes a plurality of fuses, and sets analysis information of a predetermined bit according to a connection state of the plurality of fuses.

Further, in the semiconductor integrated circuit device according to the present invention, the analysis information output section includes a shift register, and converts the analysis information output from the information storage section into a serial signal and outputs the serial signal.

Further, according to the semiconductor integrated circuit device of the present invention,
The analysis information stored in the information storage means is information on an arrangement in each semiconductor chip.

As described above, since the analysis information such as the arrangement of individual semiconductor chips can be obtained without disassembling the package, the analysis information such as the distribution of the processing state of the semiconductor wafer can be obtained efficiently and in large quantities. .

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a circuit diagram of an analysis information storage circuit provided in a semiconductor integrated circuit device according to Embodiment 1 of the present invention. FIG. 2 is an analysis diagram of Embodiment 1 of the present invention. FIG. 3 is a circuit diagram of the information output circuit provided in the information storage circuit, and FIG. 3 is a timing chart of the analysis information storage circuit according to the first embodiment of the present invention.

In the first embodiment, an analysis information storage circuit (analysis information storage means) 1 is provided in a semiconductor integrated circuit device, and the analysis information storage circuit 1 is required for the semiconductor integrated circuit device. Analysis information used for failure analysis and the like is stored electrically.

As shown in FIG. 1, the analysis information storage circuit 1 includes N N-channel MOSs (Metal Oxides).
(Transistors TS1 to TSN). Transistor TS1
A test pin (first external lead line) T, which is an external pin to which a test signal (analysis signal) is input,
The transistor TSN is connected to P, and the other connection of the transistor TSN is connected to a ground potential, which is a reference potential.

The transistors TS1 to TSN are connected in series, the gates of the transistors TS1 to TSN are respectively connected to one connection part, and the gate of the transistor TSN is connected to the gate of the transistor T1. .

A voltage having a voltage value higher than the power supply voltage, which is the operating voltage of the semiconductor integrated circuit device, is input to the test pin TP as a test signal, and a predetermined voltage stepped down from the gate of the transistor TSN is applied to the gate of the transistor T1. Is output to Therefore, even if a power supply voltage or the like is erroneously input, the analysis information storage circuit 1 does not operate.

One connecting portion of the transistor T1 has P
The other connection of the transistor T2, which is a channel MOS, is connected to the other connection, and the other connection of the transistor T1 is connected to the ground potential.

A power supply voltage is supplied to one connection portion and a gate of the transistor T2, and an input portion of the inverter Iv1 is connected to the other connection portion of the transistor T2.

The output of the inverter Iv1 is connected to the input of the inverter Iv2, and the output of the inverter Iv2 is connected to the input of the inverter Iv3. The output of the inverter Iv2 has a switch S
The control signal input units 1C of W1 to SW3 are connected,
Switches SW1 to SW are connected to the output section of the inverter Iv3.
3 control signal input units 1C are connected.

Each of the switches SW1 to SW3 has a structure in which N-channel MOS and P-channel MOS transistors are connected in parallel. The gate of the N-channel MOS transistor becomes the control signal input section 1C, and the P-channel M
The gate of the OS transistor serves as the control signal input unit 1C, and the conduction control of the switches SW1 to SW3 is performed based on the control signals input to the control signal input units C and / C.

Further, an external pin P1, an external pin P2, and an external pin (second external lead-out line) P3 are connected to one connection portion of the switches SW1 to SW3, respectively. The clock signal CK is input to the external pin P1, and the shift pulse SP is input to the external pin P2.

The external pin P3 is connected to the analysis information output from the information output circuit 2 to output serial signal output data Dt.
Output as Since the analysis information is output by a serial signal, only one external pin P3 is required, and the number of external pins for outputting the analysis information can be reduced.

The transistors TS1 to TS1
N, T1, T2, inverters Iv1 to Iv3, and switches SW1 to SW3 constitute a signal detection unit.

The information output circuit 2 is connected to the switches SW1 to SW3. The information output circuit 2 stores, as analysis information, arrangement information on individual semiconductor chips, that is, coordinate position data of a semiconductor wafer.
Output analysis information based on the test signal.

As shown in FIG. 2, the information output circuit 2 includes a shift register (analysis information output unit) SR, a plurality of fuses (information storage units) FN1 to FNn, FM1 to FMm, and a plurality of fuses FN1 to FNn. N-channel MOS transistors TN1 to TN as many as FM1 to FMm
n, TM1 to TMm.

The shift register SR has a switch SW1
To SW3 are connected to each other, and the signal synchronous clock signal C is output through these switches SW1 and SW2.
K and a shift pulse SP for controlling the shift register SR are input. Further, output data Dt of a serial signal output from the shift register SR via the switch SW3 is output.

The shift register SR receives parallel data. The other input portions of the fuses FN1 to FNn and FM1 to FMm are connected to the data input portions DN1 to DNn and DM1 to DMm to which the parallel data is input, respectively.
One of the connecting portions of FM1 to FMm is connected so that a power supply voltage is supplied.

Fuse FN1 to FNn, FM1 to FMm
Are connected to transistors TN1-TNn, T
One of the connection portions of M1 to TMm is connected, and the other connection portion of these transistors TN1 to TNn and TM1 to TMm is connected to a ground potential as a reference potential.
Transistor TN1～TNn, to the gates of TM1～TMm, a constant voltage source V _IE is supplied.

The semiconductor wafer coordinates in the X direction are represented by N bits of the fuses FN1 to FNn, and the semiconductor wafer coordinates in the Y direction are represented by M bits of the fuses FM1 to FMm.

Next, the operation of the present embodiment will be described with reference to the timing charts of FIGS. 1, 2 and 3.

In FIG. 3, from top to bottom,
Clock signal CK input from external pin P1, shift pulse SP input from external pin P2, external pin P3
3 shows a signal of a data output Dt output from the data output device.

When a test signal having a predetermined voltage value higher than the power supply voltage is input from a test pin TP provided in the semiconductor integrated circuit device, a signal stepped down to the voltage set by the transistors TS1 to TSN is applied to the transistor T
1 is output to the gate.

The N + M-bit data input to the data input sections DN1 to DNn and DM1 to DMm of the shift register SR are stored in advance in the probe inspection step or the like by using the fuses FN1 to FNn and the fuses FM1 to FMm.
Are arbitrarily cut by a laser or the like, and the setting of the X-direction semiconductor wafer coordinates composed of the N-bit data and the Y-direction semiconductor wafer coordinates composed of the M-bit data is performed.

Since the Hi signal is input to the gate of the transistor T1, the transistor T1 is turned ON, and the Lo signal is input to the input section of the inverter Iv1, so that the output section of the inverter Iv2 has the Lo signal, and the output section of the inverter Iv3 has the Lo section. Hi signal output.

Therefore, a Hi signal is applied to the control signal input section C of the switches SW1 to SW3, and a Lo signal is applied to the control signal input section / C.
Since the signals are respectively input, the switches SW1 to SW
3 becomes conductive.

The shift register SR has a shift pulse SP
Is a Lo signal, the shift pulse SP input from the external pin P2 is inverted from the Hi signal to the Lo signal.

When the shift pulse SP becomes the Lo signal, the shift register SR synchronizes with the clock signal CK inputted via the switch SW1 to the data input section DN1.
To DNn and DM1 to DMm are output as data output Dt as serial signals.

Therefore, by reading out the data output Dt output from the external pin P3 via the switch SW3 by a tester or the like, analysis information can be detected, and the semiconductor wafer in the semiconductor chip used in each semiconductor integrated circuit device can be detected. Information on the coordinate position can be obtained.

Thus, in the first embodiment,
By providing the analysis information storage circuit 1 in the semiconductor integrated circuit device, the coordinate position of the semiconductor wafer can be electrically read, so that characteristic correlation data such as the distribution of the processing state of the semiconductor wafer can be easily obtained.

Further, since it is possible to obtain analysis information without disassembling the package, a semiconductor integrated circuit device which has been analyzed for electrical characteristics and yield in a manufacturing process can be shipped as a product, and the manufacturing efficiency is greatly reduced. It can improve and analyze a large number of products.

Further, in the first embodiment, the data input sections DN1 to DNn, DM1 to DM
m + N-bit data input to the fuse FN1
To FNn and fuses FM1 to FMm. For example, as shown in FIG. 4, N + M-bit data is stored in an EPROM (Erasable and Prog).
ramble Read Only Memor
y) or the like, and the data stored in the memory 3 may be read by the shift register SR.

(Embodiment 2) FIG. 5 is a circuit diagram of an analysis information storage circuit provided in a semiconductor integrated circuit device according to Embodiment 2 of the present invention.

In the second embodiment, an analysis information storage circuit (analysis information storage means) 1a is provided for each of the (N + M) external pins provided in the semiconductor integrated circuit device. These external pins are, for example, N + M address pins (first and second external lead lines) A0 to An in the case of a memory such as a DRAM.

The analysis information storage circuit 1a includes N N
The transistor TSS1 comprises a channel MOS transistor TSS1 to TSSN and a fuse (information storage unit) FA. The transistor TSS1 to TSSN and the fuse FA constitute an analysis information output unit and a signal detection unit.

For example, the case of the analysis information storage circuit 1a connected to the address pin A0 will be described.

An address buffer B is connected to the address pin A0.
, An address signal is output to peripheral circuits and the like. Further, one connection portion and the gate of the transistor TSS1 are connected to the address pin A0.

The transistors TSS1 to TSSN-1 are connected in series. One connection of the fuse FA is connected to the other connection of the transistor TSSN-1, and the other connection of the fuse FA is connected. Is connected to one connection of the transistor TSSN.

A ground potential is connected to the other connection of the transistor TSSN, and a constant voltage power supply V _IE is supplied to the gate and one connection of the transistor TSSN. Further, the transistor TSS
Each of the gates of 1 to TSSN-1 is connected to one connection of the transistors TSS1 to TSSN-1, respectively.

Since the analysis information storage circuit 1a is connected to each of the N + M address pins A0 to An, the number of the fuses FA is also N + M. The N fuses FA set the semiconductor wafer coordinates in the X direction. The semiconductor wafer coordinates in the Y direction are set by the fuses FA.

Therefore, in the probe inspection process or the like, the N + M fuses FA are arbitrarily cut by a laser or the like, so that the N + M bits of data are set.

To output the analysis information, a voltage having a voltage value higher than the power supply voltage is input to the address pin test pins A0 to An.
n is measured by a tester to determine whether current flows
Acquires information on a semiconductor wafer coordinate position.

Thus, also in the second embodiment,
By providing the semiconductor integrated circuit device with the analysis information storage circuit 1a, the coordinate position of the semiconductor wafer can be electrically read out, so that characteristic correlation data such as the distribution of the processing state of the semiconductor wafer can be easily obtained.

Further, since the semiconductor wafer coordinate position can be read out without disassembling the package, the semiconductor integrated circuit device analyzed in the electric characteristics and the yield in the manufacturing process can be shipped as a product, so that the manufacturing efficiency is improved. In addition, it is possible to analyze a large number of products.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the first and second embodiments, the analysis information stored in the analysis information storage circuit is only the information on the coordinate position of the semiconductor wafer. Various information necessary for analysis and the like may be stored. Thereby, failure analysis and the like can be performed more efficiently.

[0061]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, by providing the analysis information storage means for outputting the analysis information from the second external lead line, the analysis information such as the arrangement in each semiconductor chip can be disassembled into a package. Therefore, it is possible to efficiently analyze a semiconductor integrated circuit device such as failure analysis and distribution of a processing state of a semiconductor wafer.

(2) Further, according to the present invention, since the package does not need to be disassembled, the analysis information of the semiconductor integrated circuit device as a product can be obtained before shipment, so that a large amount of analysis information can be obtained without waste. Can be obtained in time.

(3) Further, in the present invention, according to the above (1) and (2), the manufacturing efficiency of the semiconductor integrated circuit device can be improved and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an analysis information storage circuit provided in a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an information output circuit provided in the analysis information storage circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart of the analysis information storage circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram of an information output circuit provided in an analysis information storage circuit according to another embodiment of the present invention.

FIG. 5 is a circuit diagram of an analysis information storage circuit provided in a semiconductor integrated circuit device according to a second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Analysis information storage circuit (analysis information storage means) 1a Analysis information storage circuit (analysis information storage means) 2 Information output circuit 3 Memory (information storage part) TS1-TSN transistor T1, T2 transistor TN1-TNn, TM1-TMm transistor TSS1 To TSSN transistor TP test pin (first external lead line) Iv1 to Iv3 inverter SW1 to SW3 switch SR shift register (analysis information output unit) FN1 to FNn, FM1 to FMm fuse (information storage unit) FA fuse (information storage unit) ) C, / C control signal input section P1 external pin P2 external pin P3 external pin (second external lead line) DN1 to DNn data input section DM1 to DMm data input section A0 to An address pin (first and second) External lead wire) SP shift pulse Dt output data CK clock signal V _IE constant voltage power supply

Continued on the front page (72) Inventor Isao Tagaya 5-22-1, Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hitachi Cho LSI Systems, Ltd.

Claims (5)

[Claims] 1. An analysis information storage means for electrically storing analysis information and outputting the analysis information to a second external lead line based on an analysis signal input from the first external lead line. A semiconductor integrated circuit device characterized by the above-mentioned. 2. The semiconductor integrated circuit device according to claim 1, wherein said analysis information storage means outputs an information storage section for storing analysis information based on a control signal. An analysis information output unit that detects an analysis signal input from the first external leader line, controls the analysis information output unit, and outputs the analysis information output from the analysis information output unit to the second A semiconductor integrated circuit device comprising: a signal detection unit that outputs to an external lead line. 3. The semiconductor integrated circuit device according to claim 2, wherein said information storage section comprises a plurality of fuses, and analysis information of a predetermined bit is set according to a connection state of said plurality of fuses. Circuit device. 4. The semiconductor integrated circuit device according to claim 2, wherein the analysis information output unit includes a shift register, and converts the analysis information output from the information storage unit into a serial signal and outputs the serial signal. A semiconductor integrated circuit device, characterized by: 5. The semiconductor integrated circuit device according to claim 1, wherein the analysis information stored in the information storage means is information on an arrangement in each semiconductor chip. Semiconductor integrated circuit device.