JPH1132231A - Vertical dynamic focusing circuit for monitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the image quality by amplifying a 2nd lamp signal which results from varying a level of a 1st ramp signal depending on a 1st DC power supply and a frequency of the 1st ramp signal based on a 2nd DC power supply and converting the amplified signal into a vertical dynamic convergence signal of a parabolic form, so as to vary a level of the vertical dynamic convergence signal according to the frequency of a vertical synchronizing signal. SOLUTION: A ramp signal control circuit 100 amplifies a 1st ramp signal CS1 of a sawtooth waveform according to a 1st DC power supply Vcc1 and a frequency of the 1st ramp signal CS1 and provides an output of a 2nd ramp signal CS2. A vertical dynamic convergence signal generating circuit 200 amplifies the 2nd ramp signal CS2 depending on a voltage of a 2nd DC power supply Vcc2, converts the amplified signal into a vertical dynamic convergence signal of a parabolic form, inverts the signal and generates a superimposing signal M by superimposing the inverted signal onto a DC voltage DC. Thus, the convergence of electron beams at the edges ridges of a screen is increased to improve the image quality, when the frequency of the vertical synchronization signal is high.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monitor, and more particularly to a monitor.
The present invention relates to a vertical dynamic focusing circuit of a monitor for maintaining a constant peak).

[0002]

2. Description of the Related Art Generally, electrons emitted from a cathode of a cathode ray tube (hereinafter abbreviated as "CRT") are accelerated by a voltage supplied from a grid terminal, and thus electrons are emitted by a magnetic field generated by vertical and horizontal deflection coils. It collides with the surface and thus a screen is formed.

Such a CRT has a heater voltage of about 6.3 V, a focused grid voltage and a screen grid voltage supplied to a grid terminal for focusing emitted electrons, and an anode for accelerating emitted electrons. A high voltage of about 25 KV is supplied to the terminals.

At this time, the focus of the emitted electrons is inferior as it approaches the edge of the screen, so that the image quality deteriorates. In order to improve the image quality at the edge of the screen, a parabolic focused signal is supplied to the cathode ray tube.

[0005] The focus signal is a static focusing signal in which the magnitude of the focus signal is fixed according to the frequency of the fixed synchronization signal, and the dynamic focus signal in which the magnitude of the signal is varied according to the frequency of the synchronization signal. focusing signal), and the magnitude of the dynamic focusing signal increases in proportion to the size of the screen.

FIG. 1 is a diagram showing a configuration of a vertical dynamic focusing circuit of a general monitor, and FIGS.
(H) is a diagram showing output signals of each unit in FIG. 1. Here, reference numeral 1 denotes an amplifying unit corresponding to the frequency of the horizontal synchronizing signal and amplifies a ramp signal CS having a sawtooth waveform supplied from the outside. Reference numeral 3 denotes a signal converter for generating a vertical dynamic focusing signal, and a symbol 3 for amplifying the vertical dynamic focusing signal, superimposing the DC voltage DC supplied from the high voltage flyback transformer FBT, and supplying the superimposed signal to the mixing unit. Is a superimposed portion.

Next, the configuration of the vertical dynamic focusing circuit will be described more specifically.

The input side of the ramp signal CS is the ramp signal CS.
Is connected to one side of a capacitor (capacitor) C for blocking a DC component of the capacitor C, and the other side of the capacitor C is connected to one side of a resistor R for passing an output signal of the capacitor C.

The other side of the resistor R is connected to the positive terminal (+) of the amplifier 11 of the amplifier 1 for amplifying the output signal of the resistor R. On the other hand, an externally supplied DC power supply Vcc
Is connected to one side of a resistor 12 for distributing a DC power supply Vcc, the other side of the resistor 12 is connected to one side of a resistor 13, and the other side of the resistor 12 is connected to a negative terminal of the amplifier 11 ( -) Is connected. The other side of the resistor 13 is grounded.

A resistor 14 for determining the amplification of the amplifier 11 is connected between one side of the resistor 12 and the output side of the amplifier 11. The output side of the amplifier 11 is connected to one side of a resistor 15 for passing an amplified signal.

The other side of the resistor 15 is connected to the negative terminal (-) of the amplifier 21 of the signal converter 2. One side of a resistor 22 for distributing the DC power supply Vcc is connected to the input side of the DC power supply Vcc supplied from the outside, and the other side of the resistor 22 is connected to one side of the resistor 23 and the other side of the resistor 22. Is connected to the positive terminal (+) of the amplifier 21. Resistance 23
Is grounded.

The output side of the amplifier 21 is connected to one side of a resistor 24 for passing the output signal of the amplifier 21, and the other side of the resistor 24 outputs the output signal of the resistor 24 to a parabolic vertical dynamic One side of a resistor 25 for converting into a focused signal and one side of a capacitor 26 are connected. The other side of the capacitor 26 is grounded, and the other side of the resistor 25 is connected to the negative terminal (-) of the amplifier 21.

On the other hand, a capacitor 27 for determining the degree of amplification of the amplifier 21 is connected between the negative terminal (-) of the amplifier 21 and its output side.

The output side of the amplifier 21 is connected to a capacitor 28 for blocking the DC component of the shaped signal, and the other side of the capacitor 28 is connected to the capacitor 2.
8 is connected to the resistor 29 for passing the output signal.

On the other hand, an externally supplied DC power supply Vcc
Is connected to one side of a resistor 31 of the superimposing section 3 for superimposing the vertical dynamic convergence signal of the signal converting section 2, and the other side of the resistor 31 is the other side of the resistor 29 of the signal converting section 2. Connected to

The other side of the resistor 31 is connected to the base of a transistor 32 for amplifying a vertical dynamic focusing signal. The resistor 33 and the resistor 34 for determining the amplification of the transistor 32 are connected to the transistor 3.
2 are connected to the base side and the emitter side, respectively, and the other sides of the resistors 33 and 34 are grounded.

The input side of the DC voltage DC supplied from the high-voltage flyback transformer is connected to the anode side of a diode 35 for rectifying the DC voltage DC, and the cathode side of the diode 35 smoothes the output voltage of the diode 35. One side of the capacitor 36 and the resistor 37 is connected. The other side of capacitor 36 is grounded.

The output side of the resistor 37 and the collector side of the transistor 32 are connected to one side of a capacitor 38 which superimposes the output voltage of the resistor 37 and the output signal of the transistor 32 and forms a superimposed signal. Is connected to the mixing section M to which the dynamic focusing signal is supplied. The other side of the capacitor 38 is grounded.

Next, the operation of the general dynamic focusing circuit thus configured will be described with reference to FIGS.
This will be described with reference to FIG.

When the frequency of the vertical synchronizing signal is low (about 50 Hz), the magnitude of the sawtooth ramp signal CS supplied from the outside is about 2.5 V as shown in FIG. When the frequency of the vertical synchronizing signal is a high frequency (about 120 Hz), the magnitude of the ramp signal is about 2.5 V as shown in FIG.

Such a ramp signal CS is supplied to the amplifier 11 of the amplifier 1 via the resistor R and the capacitor C.
The amplifier 11 amplifies the output signal of the resistor R in accordance with the externally supplied DC power supply Vcc and the resistance values of the resistors 12 and 13. The amplification of the amplifier 11 is represented by resistors 13 and 14
Is determined by the resistance value.

The magnitude of the amplified signal of the amplifier 11 is such that when the frequency of the vertical synchronizing signal is low, for example, about 50 Hz,
As shown in FIG. 2C, 2.5 × (1 + R12 / R1
3) When the frequency is V and the frequency of the vertical synchronization signal is a high frequency, for example, about 120 Hz, the magnitude of the amplified signal is
As shown in (D), 2.5 × (1 + R12 / R13)
V.

Here, R12 is the resistance value of the resistor 12, and R13 is the resistance value of the resistor 13.

The amplified signal of the amplifier 11 is supplied to the amplifier 21 via the resistor 15, and the amplifier 21 shapes the amplified signal according to a limit voltage set by the resistance values of the resistors 22 and 23. The output signal of the amplifier 21 is a resistor 2
4 and supplied to a resistor 25 and a capacitor 26. The resistor 25 and the capacitor 26 integrate the output signal of the amplifier 21 to generate a parabolic vertical dynamic focusing signal. The amplification of the vertical dynamic focusing signal is
7 is determined by the capacitance.

The magnitude of the vertical dynamic focusing signal is 14.5 V as shown in FIG. 2E when the frequency of the vertical synchronizing signal is low, for example, about 50 Hz, and the frequency of the vertical synchronizing signal is high. For example, when the frequency is about 120 Hz, the peak value of the amplified signal is 5 as shown in FIG.
V.

The vertical dynamic focusing signal of the amplifier 21 is supplied to a capacitor 28, which blocks a DC component of the dynamic focusing signal, and an output signal of the capacitor 28 outputs a DC power supplied from the outside via a resistor 31. Vcc. Then, the superimposed signal is supplied to the transistor 32 of the amplifier 3.

The transistor 32 inverts the superimposed signal and then amplifies the signal. The degree of amplification is determined by the resistance values of the resistors 33 and 34.

On the other hand, the DC voltage DC supplied from the high-voltage flyback transformer FBT is supplied to a diode 35, which rectifies the DC voltage DC. The output voltage of the diode 35 is supplied to a capacitor 36, which smoothes the output voltage. The output voltage of the capacitor 36 is superimposed on the output signal of the transistor 32 via the resistor 37, and the superimposed signal is smoothed by the capacitor 38.

The smoothed signal of the capacitor 38 is supplied to a mixing section M, which mixes the horizontal dynamic convergence signal and the superimposed signal, and the mixed signal is supplied to a grid terminal of a CRT.

When the frequency of the vertical synchronizing signal is low, the magnitude of the smoothed signal is 16 as shown in FIG.
When the frequency is 0 V and the frequency of the vertical synchronization signal is a high frequency, it is 60 V as shown in FIG.

FIG. 3A shows a horizontal dynamic convergence signal for improving the image quality of the left and right edges of the screen. The vertical dynamic focus signal for improving the image quality of the upper and lower edges of the screen is shown in FIG.
This is as shown in FIG. The magnitude of the vertical dynamic focus signal is 150V and the magnitude of the horizontal dynamic focus signal is about 300V.

However, in such a general dynamic focusing circuit of a monitor, the frequency of the vertical synchronizing signal is 5
When the frequency is 0 Hz, the magnitude of the vertical dynamic focusing signal is about 160 V, and the frequency of the vertical synchronization signal is 120 H
When z, the magnitude of the vertical dynamic focus signal is about 60V. Therefore, there is a problem that the higher the frequency of the vertical synchronization signal, the lower the image quality.

[0033]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to change the magnitude of a vertical dynamic focusing signal according to the frequency of a vertical synchronization signal, An object of the present invention is to provide a vertical dynamic focusing circuit of a monitor capable of improving image quality.

[0034]

In order to achieve the above object, a vertical dynamic focusing circuit of a monitor according to the present invention is provided which converts the magnitude of an externally supplied first ramp signal into an externally supplied first DC signal. A lamp signal control circuit for outputting a second ramp signal variably in accordance with the power supply and the frequency of the first ramp signal; and an amplified signal which amplifies the second ramp signal in accordance with a second DC power supplied from outside An amplifying unit for outputting a signal, a signal converting unit for converting the amplified signal into a vertical dynamic focusing signal in a parabolic form, and inverting the vertical dynamic focusing signal of the signal converting unit, and superimposing the inverted vertical dynamic focusing signal on a DC voltage. A vertical dynamic focus for generating the parabolic vertical dynamic focus signal from the second ramp signal including a superimposition unit for generating a superimposed signal. Characterized by comprising the No. generating circuit.

According to a preferred embodiment of the present invention, a first ramp signal is supplied to a ramp signal control circuit, and the ramp signal control circuit determines the magnitude of the first ramp signal when the frequency of the vertical synchronizing signal is high. When the frequency of the vertical synchronizing signal is low, the first ramp signal is increased from the magnitude of the externally supplied first ramp signal, and the second ramp signal is output. The second ramp signal is supplied to a vertical dynamic focusing signal generation circuit. The vertical dynamic focusing signal generation circuit converts the second ramp signal into a parabolic vertical dynamic focusing signal, and converts the converted vertical dynamic focusing signal and DC voltage. And outputs a superimposed signal. Therefore, the magnitude of the first ramp signal supplied from the outside changes according to the frequency of the vertical synchronization signal, and the changed first ramp signal is supplied to the vertical dynamic focusing signal generation circuit. When is a high frequency, image quality can be improved.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 4 is a diagram showing a configuration of a vertical dynamic focusing circuit according to an embodiment of the present invention. In the figure, reference numeral 100 denotes a first ramp signal CS1 supplied from the outside.
Is amplified in accordance with the frequency of the first DC power supply Vcc1 and the first ramp signal CS1 supplied from the outside, and a second ramp signal CS2 is output.

Reference numeral 200 denotes an amplifying section 210 for amplifying the second ramp signal CS2 according to a second DC power supply Vcc2 supplied from the outside and outputting an amplified signal, and a parabolic vertical dynamic focusing of the amplified signal having a sawtooth waveform. A vertical signal including a signal converting unit 220 for converting the signal into a signal and a superimposing unit 230 for inverting the vertical dynamic focusing signal of the signal converting unit 220 and generating a superimposed signal in which the inverted vertical dynamic focusing signal is superimposed on the DC voltage DC. This is a dynamic focusing signal generation circuit.

Here, the ramp signal control circuit 100 controls the first ramp signal CS1 having a sawtooth waveform supplied from the outside.
A pulse signal conversion unit 110 that converts the pulse signal into a pulse signal, an oscillation unit 120 that oscillates according to the frequency of the pulse signal, a switching signal generation unit 130 that integrates an output signal of the oscillation unit 120 and outputs a switching signal, And a second ramp signal generator 140 that switches according to the switching signal, adjusts the magnitude of the output signal of the pulse signal converter 110 according to the frequency of the first ramp signal, and outputs the second ramp signal CS2.

Next, the configuration of the ramp signal control circuit 100 will be described more specifically.

First ramp signal CS1 supplied from outside
Is connected to the positive terminal (+) of the buffer 111 for delaying the output of the first ramp signal CS1, and the negative terminal (−) of the buffer 111 is connected to the output terminal of the buffer 111.

The output terminal of the buffer 111 is connected to one side of a resistor 112 for passing the output signal of the buffer 111, and the other side of the resistor 112 is connected to the buffer 111
Is connected to the positive terminal (+) of the amplifier 113 for converting the output signal of the amplifier 113 into a pulse signal. On the other hand, the first
The first DC power supply Vcc1 is connected to the input terminal of the DC power supply Vcc1.
Is connected to one side of the resistor 114 for distributing the current, and the other side of the resistor 114 is connected to the negative terminal (−) of the amplifier 113 and the resistor 1.
15 are connected. The other side of the resistor 115 is grounded.

The output terminal of the amplifier 113 operates according to a first DC power supply Vcc1 supplied from the outside, and is provided with an oscillating unit 120 for converting the frequency of the pulse signal of the amplifier 113 according to the frequency of the first ramp signal. Input side is connected. The output side of the oscillating unit 120 is
One side of a resistor 131 of the switching signal generating unit 130 for passing the oscillation signal is connected, and the other side of the resistor 131 is connected to one side of a capacitor 132 for integrating the oscillation signal and outputting the switching signal. The other side of the capacitor 132 is grounded.

One side of the capacitor 132 is connected to one side of a resistor 133 for allowing a switching signal to pass therethrough, and the other side of the resistor 133 is connected to the base of the transistor 141 of the second ramp signal generating section 140 which switches by the switching signal. Connected to the side.

On the other hand, the output terminal of the buffer 111
Ramp signal control unit 1 for amplifying ramp signal CS1
The positive terminals (+) of the forty amplifiers 142 are connected. One side of resistors 143, 144 and 145 for determining the amplification of the amplifier 142 is provided between the emitter side and the collector side of the transistor 141 and between the negative terminal (−) of the amplifier 142 and the output terminal of the amplifier 142. Are connected to each other, and the other sides of the resistors 143 and 144 are grounded.

The amplifying section 210 of the vertical dynamic focus signal generation circuit 200 and the dynamic focus signal conversion section 2
20, and the superimposing unit 230 include amplifiers 211 and 221,
Resistors 212 to 215, 222 to 225, 229, 23
1, 233, 234 and 237, capacitors 226, 2
28, 236 and 238, a transistor 232, and a diode 235, and the configuration is the same as that of FIG.

Next, FIGS. 4 and 5 (A) to 5
The operation and effect of the vertical dynamic focusing circuit of the monitor according to the embodiment of the present invention will be described with reference to FIG.

First ramp signal CS1 supplied from outside
When the frequency of the vertical synchronizing signal is a low frequency, for example, about 50 Hz, as shown in FIG.
V and the frequency of the vertical synchronization signal is a high frequency, for example, about 1
When the frequency is 20 Hz, as shown in FIG.
5V. The first ramp signal CS1 supplied from the outside is supplied to the buffer 111 of the pulse signal converter 110.
And the buffer 111 supplies the first ramp signal CS1
Delay the output of The output signal of the buffer 111 is supplied to an amplifier 113 via a resistor 112.

The first DC power supply Vcc1 supplied from the outside is supplied to resistors 114 and 115,
14 and 115 are first DC power supplies Vc supplied from outside.
c1 is distributed, and the distribution voltage is supplied to the amplifier 113.

The amplifier 113 has a resistor 11 according to the distribution voltage.
2A, the pulse signal of the amplifier 113 becomes as shown in FIG. 5C when the frequency of the vertical synchronization signal is low, and when the frequency of the vertical synchronization signal is high, the pulse signal of FIG. D).

The pulse signal and the first DC power supply Vcc1 supplied from the outside are supplied to the oscillating unit 120,
Reference numeral 20 changes the period of the pulse signal according to the frequency of the vertical synchronization signal, and outputs an oscillation signal. When the frequency of the vertical synchronization signal is low, the oscillation signal
As shown in (E), when the frequency of the vertical synchronization signal is a high frequency, the oscillation signal is as shown in FIG. 5 (F).

The oscillation signal is supplied to the switching signal generator 130.
Is supplied to the capacitor 132 through the resistor 131, and the capacitor 132 integrates the oscillation signal and outputs a switching signal. When the frequency of the vertical synchronization signal is low, the magnitude of the switching signal is about 0.6 V as shown in FIG. 5 (G), and when the frequency of the vertical synchronization signal is high, the magnitude of the switching signal is small. Is about 1.2 V as shown in FIG.

The switching signal is supplied to the base side of the transistor 141 via the resistor 133. When the vertical synchronizing signal has a low frequency, the magnitude of the switching signal is about 0.5.
Since it is 6V, transistor 141 is switched to the off state.

On the other hand, the output signal of the buffer 111 is amplified via the amplifier 142, and the transistor 141 is turned off.
44 and 145. That is,
The amplifier 142 amplifies the first ramp signal CS1 according to the resistance values of the resistors 144 and 145, and outputs a second ramp signal.

That is, the magnitude of the second ramp signal CS2 is proportional to (1 + R144 / R145), and when the frequency of the vertical synchronizing signal is low, the magnitude of the second ramp signal CS2 is as shown in FIG. As shown in FIG. Here, R144 is the resistance value of the resistor 144, and R145
Is the resistance value of the resistor 145.

However, when the vertical synchronizing signal has a high frequency, the magnitude of the switching signal is about 1.2 V, so that the transistor 141 is turned on.

Therefore, the amplification degree of the amplifier 142 for amplifying the output signal of the buffer 111 is determined by the resistors 143, 144 and 1
45 is determined by the resistance value. That is, the amplifier 14
2 outputs the first ramp signal CS1 to the resistors 143, 144 and 1
It amplifies according to the resistance value of 45 and outputs a second ramp signal CS2.

That is, the magnitude of the second ramp signal CS2 is ｛1+ [R145 / (R143 × R144) / (R14
3 + R144)], and the peak value of the second ramp signal CS2 is about 3 V as shown in FIG. 5 (J). Here, R143 is the resistance value of the resistor 143, and R144 is the resistor 1
A resistance value of R44 and R145 are resistance values of the resistor 145.

Therefore, the magnitude of the second ramp signal CS2 is larger when the frequency of the vertical synchronizing signal is high than when the frequency of the vertical synchronizing signal is low.

The second ramp signal CS2 is supplied to the amplifier 21
The power is supplied to an amplifier 211 via a resistor R and a capacitor C, which are 0, and the amplifier 211 amplifies the DC power supply Vcc2 supplied from outside and the resistance values of the resistors 212 and 213. The amplification of the amplifier 211 is determined by the resistance values of the resistors 214 and 215.

The amplified signal of the amplifier 211 is supplied to an amplifier 221 via a resistor 215, and the amplifier 221 converts the amplified signal into a parabolic vertical dynamic focusing signal. Then, the output signal of the amplifier 221 is shaped according to the limit voltage set by the resistance values of the resistors 222 and 223, and when the frequency of the vertical synchronization signal is low, the magnitude of the vertical dynamic focusing signal is as shown in FIG. As shown in FIG. 5K, when the frequency of the vertical synchronization signal is high, the magnitude of the vertical dynamic focusing signal is about 11 V as shown in FIG.

The vertical dynamic focusing signal of the amplifier 221 is supplied to a capacitor 228. The capacitor 228 blocks the DC component of the vertical dynamic focusing signal, and the output signal of the capacitor 228 is supplied to the outside through a resistor 231. The superimposed signal is supplied to the transistor 232 of the superimposing unit 230 via the resistor 229.

The transistor 232 inverts and amplifies the rectified vertical dynamic convergence signal, and the degree of amplification is determined by the resistance values of the resistors 233 and 234.

On the other hand, the DC voltage DC supplied from the high-voltage flyback transformer is supplied to a diode 235, and the diode 235 rectifies the DC voltage DC. The output voltage of the diode 235 is supplied to a capacitor 236, which smoothes the output voltage. The output voltage of the capacitor 236 is superimposed on the output signal of the transistor 232 via the resistor 237, and the superimposed signal is smoothed by the capacitor 238.

The smoothed superimposed signal of the capacitor 238 is supplied to a mixing section M. The mixing section M mixes the superimposed signal with the superimposed signal generated by the horizontal dynamic convergence signal generating circuit, and then supplies the mixed signal to the grid terminal of the CRT. Supply. When the frequency of the vertical synchronizing signal is low, the magnitude of the smoothed superimposed signal is about 150 V as shown in FIG. 5M, and when the frequency of the vertical synchronizing signal is high, smoothing is performed. The magnitude of the superimposed signal is about 1 as shown in FIG.
30V.

That is, the vertical dynamic focusing signal is constant irrespective of the frequency of the vertical synchronizing signal.

FIG. 6 is a diagram showing a vertical dynamic focusing circuit of a monitor according to another embodiment of the present invention. In the figure, reference numeral 300 denotes an amplifier for amplifying a first ramp signal CS1 supplied from the outside according to the frequency of the first DC power supply Vcc1 supplied from the outside and the frequency of the first ramp signal CS1, and outputting a second ramp signal CS2. This is a lamp signal control circuit for performing the operation. Reference numeral 200 denotes an amplifier 210 that amplifies the second ramp signal CS2 according to a second DC power supply Vcc2 supplied from the outside and outputs an amplified signal, and a signal converter that converts the amplified signal into a parabolic dynamic focusing signal. And a superposition unit 23 for inverting the vertical dynamic focus signal of the signal conversion unit 220 and superimposing the inverted vertical dynamic focus signal with the DC voltage DC to generate a superposition signal.
It is a vertical dynamic focusing signal generation circuit including 0,
The configuration of the vertical dynamic convergence signal generation circuit 200 is the same as that of FIG. 5, and a description thereof will be omitted.

On the other hand, the ramp signal control circuit 300 includes a microprocessor 310 for generating a pulse signal by pulse width modulating the externally supplied vertical synchronizing signal Vs, and a switching for integrating the pulse signal to generate a switching signal. The signal generator 320 includes an amplifying unit 330 for switching a switching signal generated by the switching signal generator 320 to amplify a first ramp signal CS1 supplied from the outside and output a second ramp signal CS2.

Next, the configuration of the ramp signal control circuit 300 will be specifically described.

The externally supplied vertical synchronizing signal Vs is supplied to a microprocessor 310 that generates a pulse signal by performing pulse width modulation, and the output side of the microprocessor 310 has a resistor 321 of a switching signal generator 320.
Are connected.

On the other hand, a third DC power supply V
One side of a resistor 322 for distributing an externally supplied third DC power supply Vcc3 is connected to the input side of cc3, and the other side of the resistor 322 is connected to the other side of the resistor 321 and the resistor 3
23 is connected to one side.

The other side of the resistor 322 is connected to one side of a resistor 324 for superimposing the distribution voltage and the pulse signal and passing the superimposed signal, and the other side of the resistor 324 integrates the superimposed signal to perform switching. One side of a capacitor 325 for generating a signal is connected, and the other side of the capacitor 325 is grounded. The above capacitor 3
A positive terminal (+) of an amplifier 326 for amplifying a switching signal is connected to one side of 25.

A resistor 32 for determining the degree of amplification of the amplifier 326 is provided between the output side of the amplifier 326 and the negative terminal (-).
7 is connected to a negative terminal (-) of the amplifier 326, and a resistor 328 for determining the amplification of the amplifier 326 is also connected.
Are connected on one side. The other side of the resistor 328 is grounded. The amplifier 326 outputs the amplified switching signal.

The output terminal of the amplifier 326 is connected to one side of a resistor 331 for passing the amplified switching signal, and the other side of the resistor 331 is connected to the base side of a transistor 332 that switches by the switching signal.

On the other hand, a positive terminal (+) of an amplifier 333 for amplifying the first ramp signal CS1 is connected to an input side of the first ramp signal CS1. And the transistor 33
2 is connected between the emitter side and the collector side, and between the negative terminal (−) of the amplifier 333 and the output terminal of the amplifier 333.
One side of each of the resistors 334, 335 and 336 for determining the amplification degree of 33 is connected to each other.
The other side of 35 is grounded.

Next, the operation and effect of the vertical dynamic focusing circuit of the monitor according to another embodiment of the present invention having the above configuration will be described with reference to FIGS. 7 (A) to 7 (J).

The externally supplied vertical synchronizing signal Vs is supplied to the microprocessor 310, and the microprocessor 310 pulse-modulates the vertical synchronizing signal Vs and outputs a pulse signal. When the frequency of the vertical synchronization signal is low, the pulse signal is as shown in FIG. 7A, and when the frequency of the vertical synchronization signal is high, the pulse signal is as shown in FIG. 7B. .

On the other hand, a third DC power supply V
cc3 is supplied to resistors 322 and 323,
2 and 323 distribute a DC power supply Vcc3 supplied from the outside. Such a distribution voltage and the pulse signal supplied via the resistor 321 are superimposed, and when the frequency of the vertical synchronization signal is low, the magnitude of the superimposed signal is as shown in FIG.
As shown in FIG. 7C, when the vertical synchronizing signal has a high frequency of about 4 V, the magnitude of the superimposed signal is as shown in FIG.
As shown in FIG.

The superimposed signal is supplied to a capacitor 325 via a resistor 324. The capacitor 325 integrates the superimposed signal and outputs a switching signal. The switching signal is provided to amplifier 326. The amplifier 326 amplifies the switching signal. Here, the amplification degree is the resistance 327
And 328. The output signal of the amplifier 326 is supplied to the base of the transistor 332 via the resistor 331 of the amplifier 330. When the vertical synchronizing signal has a low frequency, the magnitude of the switching signal is about 4 V, so that the transistor 332 is turned off. Switched to state.

On the other hand, the first ramp signal CS 1 is
3, the amplifier 333 amplifies the first ramp signal CS1 and outputs a second ramp signal CS2. then,
Since the transistor 332 is turned off, the amplification of the amplifier 333 is determined by the resistance values of the resistors 334 and 336.

That is, the magnitude of the second ramp signal CS2 is proportional to (1 + R336 / R334), and when the frequency of the vertical synchronizing signal is low, the magnitude of the second ramp signal CS2 is as shown in FIG. It is about 2.5V as shown. Here, R334 is the resistance value of the resistor 334, and R336
Is the resistance value of the resistor 336.

However, when the frequency of the vertical synchronizing signal is high, the magnitude of the switching signal is about 3 V, so that the transistor 332 switches to the turn-on state.

Therefore, the amplification degree of the amplifier 333 for amplifying the first ramp signal CS1 is determined by the resistances 334, 335 and 336.
Is determined by the resistance value.

That is, the magnitude of the second ramp signal CS2 is ｛1+ [R336 / (R335 × R334) / (R3
34 + R335)] is proportional to｝, and the second ramp signal CS2
Is about 3 V as shown in FIG. 7 (F). Here, R334 is the resistance value of the resistor 334, and R335 is the resistor 3
A resistance value of 35 and R336 are resistance values of the resistor 336.

Therefore, the magnitude of the second ramp signal CS2 is larger when the frequency of the vertical synchronization signal is high than when the frequency of the vertical synchronization signal is low.

The second ramp signal CS2 is supplied to the amplifier 21
The power is supplied to an amplifier 211 via a resistor R and a capacitor C, which are 0, and the amplifier 211 amplifies the DC power supply Vcc2 supplied from outside and the resistance values of the resistors 212 and 213. The amplification of the amplifier 211 is determined by the resistances 213 and 21.
4 is determined by the resistance value.

The amplified signal of the amplifier 211 is supplied to the amplifier 221, the resistors 224 and 225 and the capacitor 226 via the resistor 215, and the amplifier 221, the resistors 224 and 22
5 and the capacitor 226 convert the amplified signal into a parabolic vertical dynamic focusing signal. Further, the vertical dynamic focusing signal is shaped according to the limit voltage set by the resistance values of the resistors 222 and 223, and when the frequency of the vertical synchronization signal is low, the magnitude of the vertical dynamic focusing signal is as shown in FIG. About 11.8V as shown in G)
When the frequency of the vertical synchronizing signal is a high frequency, the magnitude of the vertical dynamic focusing signal is about 11 V as shown in FIG.

The vertical dynamic focusing signal of the amplifier 221 is supplied to a capacitor 228. The capacitor 228 blocks a DC component of the vertical dynamic focusing signal. The output signal of the capacitor 228 is supplied via a resistor 231 of the superimposing unit 230. The superimposed signal is supplied to the transistor 232 via the resistor 229.

The transistor 232 inverts the superimposed signal and then amplifies the signal. The degree of amplification is determined by the resistance values of the resistors 233 and 234.

On the other hand, the DC voltage DC supplied from the high-voltage flyback transformer is supplied to a diode 235, which rectifies the DC voltage DC. The output voltage of the diode 235 is supplied to a capacitor 236, which smoothes the output voltage. The output voltage of the capacitor 236 is superimposed on the vertical dynamic focusing signal of the transistor 232 via the resistor 237, and the superimposed signal is smoothed by the capacitor 238.

The smoothed superimposed signal of the capacitor 238 is supplied to a mixing section M, which mixes the superimposed signal with a horizontal dynamic focusing signal generated by a horizontal dynamic focusing signal generating circuit (not shown). After that, it is supplied to the grid terminal of the CRT. At this time, when the frequency of the vertical synchronizing signal is low, the magnitude of the smoothed superimposed signal is about 150 V as shown in FIG. 7I, and when the frequency of the vertical synchronizing signal is high, The magnitude of the smoothed superimposed signal is about 130 V as shown in FIG.

That is, the vertical dynamic focusing signal is constant irrespective of the frequency of the vertical synchronizing signal.

[0093]

As described above, according to the present invention,
If the frequency of the vertical synchronization signal is high, the first ramp signal is amplified and a parabolic vertical dynamic focusing signal is generated from the amplified first ramp signal. It is constant regardless of the frequency. Therefore, when the frequency of the vertical synchronizing signal is high, the image quality can be improved by increasing the convergence of the electron beam at the edge of the screen.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to these embodiments, and can be modified and improved without departing from the scope of the present invention. Of course.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a vertical dynamic focusing circuit of a conventional monitor.

FIG. 2 is a diagram showing output signals of respective units in FIG. 1;

FIG. 3A is a diagram illustrating a horizontal dynamic focusing signal of a general monitor, and FIG. 3B is a diagram illustrating a vertical dynamic focusing signal of a general monitor.

FIG. 4 is a diagram illustrating a configuration of a vertical dynamic focusing circuit of a monitor according to an embodiment of the present invention.

FIG. 5 is a diagram showing output signals of respective units in FIG. 4;

FIG. 6 is a diagram illustrating a configuration of a vertical dynamic focusing circuit of a monitor according to another embodiment of the present invention.

FIG. 7 is a diagram showing output signals of respective units in FIG. 6;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 ramp signal control circuit 110 pulse signal converter 120 oscillator 130 switching signal generator 140 second ramp signal generator 200 vertical dynamic focusing signal generator 210 amplifier 220 signal converter 230 superimposing unit

Claims (9)

[Claims] 1. A lamp signal control for outputting a second ramp signal by varying the magnitude of a first ramp signal supplied from outside according to a first DC power supplied from outside and a frequency of the first ramp signal. Means for amplifying the second ramp signal according to a second DC power supplied from the outside and outputting an amplified signal; and a signal converter for converting the amplified signal into a parabolic vertical dynamic focusing signal And a superimposing section for inverting the vertical dynamic converging signal of the signal converting section and superimposing the inverted vertical dynamic converging signal with a DC voltage to generate a superimposed signal. A vertical dynamic focusing signal generating means for generating a focusing signal; and a vertical dynamic focusing circuit of the monitor. 2. A pulse signal conversion unit for converting a first ramp signal having a sawtooth waveform supplied from the outside into a pulse signal; a duty cycle of the pulse signal according to a frequency of the pulse signal. An oscillating unit that variably generates an oscillating signal; a switching signal generating unit that integrates the oscillating signal of the oscillating unit to generate a switching signal; and a switching unit that is switched by the switching signal and is switched according to a switching state. The vertical dynamic focusing circuit according to claim 1, further comprising a second ramp signal generator for amplifying a magnitude of an output signal and outputting the second ramp signal. 3. The microprocessor according to claim 1, wherein the ramp signal control means generates a pulse signal by pulse width modulating the externally supplied vertical synchronizing signal; and a switching signal generating means for integrating the pulse signal and converting the pulse signal into a switching signal. The vertical dynamic focusing circuit of a monitor according to claim 1, further comprising: an amplifying unit that amplifies the first ramp signal supplied from the outside by being switched by the switching signal. 4. The buffer for receiving the first ramp signal supplied from the outside and delaying the output of the first ramp signal; the pulse signal conversion unit being connected to an output terminal of the buffer, A first resistor for passing an output signal of the buffer; a second resistor and a third resistor connected in series to the first DC power supply so as to distribute the first DC power supplied from the outside; A first amplifier that inputs an output signal of the buffer via a resistor, inputs a voltage applied to the second resistor, and converts an output signal of the buffer into a pulse signal in accordance with the voltage of the second resistor; 3. The vertical dynamic focusing circuit of a monitor according to claim 2, wherein: 5. The oscillator according to claim 1, wherein the oscillating unit is a multivibrator that receives the pulse signal of the pulse signal converting unit and changes a duty cycle of the pulse signal according to a frequency of a first ramp signal. Item 3. A monitor vertical dynamic focusing circuit according to Item 2. 6. The switching signal generating unit receives the output signal of the oscillating unit, and receives the output signal via a fourth resistor for passing the pulse signal having a variable duty cycle; and the fourth resistor. 3. The vertical dynamic focusing circuit of a monitor according to claim 2, further comprising a first capacitor for integrating said pulse signal having a variable duty cycle to output a switching signal. 7. The fifth ramp signal generation section is connected to an output side of the switching signal generation section, and is connected to the other side of the fifth resistance for passing the switching signal; An NPN-type first transistor which is switched by an output signal of a fifth resistor; a second amplifier connected to the output side of the buffer for amplifying the first ramp signal; a second amplifier in accordance with a switching state of the first transistor. 6. Sixth to eighth resistors for determining the amplification of the amplifier, wherein the sixth resistor is connected between the emitter side of the first transistor and ground,
The seventh resistor is connected between the collector of the first transistor and ground, the eighth resistor is connected between the negative terminal (−) of the second amplifier and the output terminal of the second amplifier, The vertical dynamic focusing circuit of a monitor according to claim 2, wherein a collector side of the first transistor and a negative terminal (-) of the second amplifier are connected. 8. The ninth resistor for inputting a pulse signal of the microprocessor and allowing the pulse signal of the microprocessor to pass therethrough, the switching signal generating unit being connected in series with a third DC power supply externally supplied. A tenth resistor and an eleventh resistor for distributing a third DC power supplied from the outside; an output voltage of the tenth resistor and an output signal of the ninth resistor for superimposing the superimposed signal; A twelfth resistor; a second capacitor for inputting the superimposed signal of the twelfth resistor and integrating the superimposed signal to generate a DC component switching signal; inputting the switching signal and amplifying and amplifying the switching signal A third amplifier for outputting a signal; and a thirteenth resistor and a fourteenth resistor for determining an amplification degree of the third amplifier, wherein the thirteenth resistor is an upper resistor. The fourteenth resistor is connected between the output side of the third amplifier and the negative terminal (−), and one side of the fourteenth resistor is connected to the negative terminal (−) of the third amplifier, and the other side is grounded. The vertical dynamic focusing circuit of a monitor according to claim 3. 9. The fifteenth resistor for receiving the output signal of the switching signal generator and passing the amplified signal of the third amplifier; the first ramp signal generator;
A second transistor of a PNP type that receives an output signal of the fifth resistor and performs switching according to the output signal of the fifteenth resistor; receives an output signal of the second transistor and the first ramp signal, and converts the first ramp signal to the first A fourth amplifier for amplifying and outputting a second ramp signal according to a switching state of the second transistor; and a sixteenth resistor to a eighteenth resistor for determining an amplification degree of the fourth amplifier, The sixteenth resistor is connected between the emitter side of the second transistor and ground, the seventeenth resistor is connected between the collector side of the second transistor and ground,
The eighteenth resistor is connected to the negative terminal (−) of the fourth amplifier and the fourth terminal.
4. The vertical dynamic focusing circuit of a monitor according to claim 3, wherein the vertical dynamic focusing circuit of the monitor is connected between an output terminal of the amplifier and a collector side of the second transistor and a negative terminal (-) of the fourth amplifier are connected. .