JPH113295A - Data transceiver - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To realize highly reliable data transmission and reception by checking whether two independent devices can normally transmit and receive data. A data transmitting / receiving circuit includes a command register, a transmission control unit, and a memory.
, The selector 106, the line driver 112, the line receiver 113, the register 109, and the reception control unit 1
07, a memory 108, a comparator 110, and a status register 115.
2 outputs a check data transmission command to the data transmission / reception circuit 103 before receiving data, instructs transmission of the check data, and notifies the data transmission / reception circuit 103 of a normal status within a predetermined time. Normal data transfer is performed, and if an abnormal status is notified, it is determined and processed as an interface error.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmitting / receiving apparatus for transmitting / receiving data between apparatuses, and more particularly, to a data transmitting / receiving apparatus for detecting a connection state between apparatuses and a failure relating to data transmission / reception.

[0002]

2. Description of the Related Art Conventionally, when data is transmitted and received between devices, the devices are generally connected by a cable or the like, and data is transmitted and received through the cable. However, in such data transfer, (1) the cable is not properly connected, (2) the cable is broken, (3) a nonstandard cable is used, (4)
Data transmission / reception may not be possible due to the influence of external noise or the like.

For this reason, for example, Japanese Patent Application Laid-Open No.
In the publication, a check circuit is provided between two devices connected by a cable controlled by one controller, and a check signal output from the controller is detected. Transmits the data determined in advance, and the other device
The cable abnormality is detected by checking whether the received data is the same as the predetermined data.

[0004]

However, in the prior art as described above, since the circuit is used to check for an abnormality in the cable, the two devices connected by the cable are independently provided. In such a case, there is a problem that the device cannot be used, which hinders improvement in reliability.

The present invention has been made in view of the above, and realizes highly reliable data transmission and reception by checking whether two independent devices can normally transmit and receive data. The purpose is to:

[0006]

According to a first aspect of the present invention, there is provided a data transmission / reception device comprising a control circuit and a data transmission / reception circuit for transmitting / receiving data to / from an external device. A data register for holding a command output by the control circuit; and a transmission control unit for performing data transmission control based on a data holding state of the command register. , A first memory for storing check data and outputting data based on a control signal output by the transmission control unit; a first memory for storing transmission data output by the control circuit;
A selector for selecting and outputting any one of the data output from the memories based on a select signal output by the transmission control unit; and a line driver for transmitting the data output by the selector to the external device. A line receiver for receiving data from the external device;
A register for temporarily holding data output by the line receiver, a reception control unit for executing reception control based on the data output by the line receiver, and storing the same data as in the first memory; A second memory that outputs data based on a control signal output by a control unit, a comparator that compares and outputs data output by the register and the second memory, an output of the comparator, and the line receiver And a status register in which the status created by the reception control unit is written from the output data of the reception control unit. The control circuit outputs a check data transmission command to the data transmission / reception circuit before receiving the data, The transmission of the check data is instructed, and the data transmission and reception circuit Perform normal data transfer when the normally status is notified, it is to determine and processing that the interface error when an abnormal status is notified.

That is, two memories are used between the control circuit and the data transmission / reception circuit to use the check data, and normal data transfer is executed when a normal status is notified from the data transmission / reception circuit within a predetermined time. And
By judging and processing an interface error when an abnormal status is notified, a function for checking whether data can be transmitted and received normally is realized, and highly reliable data transmission and reception can be performed.

According to a second aspect of the present invention, there is provided a data transmission / reception device including a control circuit and a data transmission / reception circuit for transmitting / receiving data to / from an external device. A command register for holding a command output by the control circuit, a transmission control unit for executing data transmission control based on a data holding state of the command register,
A line receiver that receives data from the external device, a reception control unit that performs reception control based on data output by the line receiver, a control signal output by the transmission control unit, and a reception control unit. A memory control signal generating means for generating a memory control signal from the output control signal, a memory for storing check data, and outputting data based on a control signal output by the memory control signal generating means; A selector for selecting and outputting one of transmission data output by a transmission unit and data output by the memory based on a select signal output by the transmission control unit; And a line driver for transmitting the data output from the line driver. A register, a comparator for comparing and outputting data output from the register and the memory, and a status register in which a status created by the reception control unit is written from an output of the comparator and output data of the line receiver. The control circuit outputs a transmission command of the check data to the data transmission / reception circuit before receiving the data, instructs the transmission of the check data, and within a predetermined time, a normal transmission from the data transmission / reception circuit is performed. When the status is notified, normal data transfer is executed, and when an abnormal status is notified, it is determined and processed as an interface error.

That is, one memory is used between the control circuit and the data transmission / reception circuit to use check data, and normal data transfer is executed when a normal status is notified from the data transmission / reception circuit within a predetermined time. And
By judging and processing an interface error when an abnormal status is notified, a function for checking whether data can be transmitted and received normally is realized, and highly reliable data transmission and reception can be performed.

Further, in the data transmitting / receiving device according to the third aspect, the control circuit executes the interface check every time immediately before performing the data transmission.

That is, by confirming whether data transmission / reception can be performed normally immediately before data transmission / reception, reliable data transfer can be realized, and highly reliable data transmission / reception can be performed. .

According to a fourth aspect of the present invention, in the data transmission / reception device, the control circuit executes an interface check when the device is initialized.

That is, by confirming whether data transmission / reception can be performed at the time of initialization of the apparatus, highly reliable and high-speed data transmission / reception can be performed.

In the data transmitting / receiving apparatus according to the fifth aspect, the first and second memories or the check data stored in the memories are all test patterns used for transmission / reception. is there.

That is, it is possible to perform highly reliable data transmission and reception by checking whether data transmission and reception can be performed normally for all data patterns used for data transmission and reception.

Further, in the data transmitting / receiving apparatus according to the present invention, the first and second memories or the check data stored in the memories may include a test pattern having a high possibility of causing a problem in data transmission / reception. It is assumed that.

That is, by confirming whether or not data transmission / reception can be performed normally, only a data pattern which is likely to cause a problem, that is, a data pattern to be checked is stored in a memory and checked, thereby achieving high reliability and high speed. Data transmission and reception.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a data transmission / reception device according to the present invention will be described in detail with reference to the accompanying drawings.

[First Embodiment] (Configuration of First Embodiment) FIG. 1 is a block diagram showing a configuration of a data transmitting / receiving apparatus according to a first embodiment. In the figure, 101 is a data transmission / reception device, 102 is a control circuit, 103 is a data transmission / reception circuit, 104 is a transmission control unit, 105 stores predetermined data, and outputs data based on a control signal from the transmission control unit 104. And a selector 106 for selecting and outputting one of data from the memory 105 and data from the control circuit 102 based on a select signal from the transmission control unit 104.

Reference numeral 107 denotes a reception control unit; 108, a memory for storing the same data as the memory 105 determined in advance and outputting data based on a control signal from the reception control unit 107; Registers to be held for adjustment, 110 is a memory 108
The comparator 111 compares the data from the register 109 with the data from the register 109 and outputs the result. 111 is a command register for storing a command from the control circuit 102. 112 is a line driver for transmitting the data output from the selector 106 to the outside. , 113 are line receivers for receiving external data, 114 is a connector,
Reference numeral 115 denotes a status register for storing the status of the reception data state.

(Operation of Embodiment 1) Next, the operation of the data transmission / reception device configured as described above will be described. The data transmission / reception device 101 shown in FIG. 1 is arranged on two independent devices (device A and device B) connected by cables, and each data reception circuit receives a command input from each higher-level circuit. To transmit and receive data based on. The details will be described below.

Data Form The data transmission / reception device 101 performs a check data transmission / reception operation in addition to a normal data transmission / reception operation. For this reason, data to be transmitted / received to / from the external device can be distinguished from check data. For example, here, it is assumed that 8-bit data is transmitted / received, the data width for transmission / reception between two devices is 9 bits, and the least significant bit is used as a flag indicating whether or not the data is check data.

Operation of Command Register 111 The command register 111 holds a command from the control circuit 102. The transmission control unit 104 transmits and receives data based on the state of the command register 111. Here, the command register 111 has a 1-bit configuration. When this bit is “0”, normal data is transmitted, and when this bit is “1”, check data is transmitted.

Operation of the status register 115 The status register 115 is set by the reception control unit 107 and controls the state of the received data by the control circuit 10.
Notify 2. Here, status register 115 has a two-bit configuration of bit 0 and bit 1. When bit 0 is "1", check data is being received.
"0" indicates other than that. When the bit 1 is "1", it indicates that an interface error has occurred in receiving the check data, and when the bit is "0", it indicates that no interface error has occurred.

Operation of Transmission Control Unit 104 The transmission control unit 104 stores “1” in the command register 111.
If (instruction to send check data) is set,
A select signal is output to the selector 106 so as to output data from the memory, and control is performed so that data stored in the memory 105 is sequentially output. This gives
Check data is transmitted to the outside.

On the other hand, if the command register 111 is "0"
If there is no instruction to transmit the check data, the transmission control unit 104
A select signal is output so as to output the data from 02. As a result, normal data is transmitted to the outside.

Operation of Reception Control Unit 107 Upon reception of the check data, the reception control unit 107 sets “0” to bit 0 of the status register 115 and
Indicates that the check data is being received, and the memory 1
In step 08, control is performed so that the stored data is output in order. In this way, if the check data from the outside is different from the data stored in the memory 108, the comparator 110 detects that the data is different, and notifies the reception control unit 107 that an interface error has occurred. Notice.

When receiving an interface error from the comparator 110 while receiving the check data, the reception control unit 107 sets the status register 11
"1" is set to bit 1 of bit 5. On the other hand, when there is no notification of the interface error, the state is kept at “0”. In addition, when the reception of the check data is completed, the reception control unit 107 returns the bit 0 indicating that the check data is being received to “0”.

The operation of the control circuit 102 will now be described by way of an example in which data is transferred from device A to device B.

(1) The upper circuit of the device A transmits the command register 1 of the data transmitting / receiving circuit 103 before performing data transfer.
"1" is written into the register 11 to instruct transmission of check data. The data transmitting / receiving circuit 103 starts transmitting test data.

(2) When the check data is received by the device B, that is, when the data having the highest order of the received data is “1”, the status register 115 in the data transmission / reception circuit 103 of the device B sets the check register to Data is being received (bit 0 is “1”).

(3) When bit 0 of the status register 115 of the data transmission / reception circuit 103 of the device B changes from "1" to "0", the status register 115
Bit 1 is “0” (no interface error)
In the case of, the transmission and reception of the check data has been performed normally, so that the upper circuit of the device B has the data transmission and reception circuit 1
03 is written into the command register 111, and transmission of check data is instructed.

(4) When the check data is received by the device A, that is, when the data having the highest order of the received data is “1”, the status register 115 of the data transmission / reception circuit 103 of the device A sets the check register to Data is being received (bit is “1”).

(5) When bit 0 of the status register 115 of the data transmission / reception circuit 103 of the device A changes from “1” to “0”, the status register 115
Bit 1 is “0” (no interface error)
In the case of, transmission / reception of the check data has been performed normally.

When it is confirmed that there is no problem in data transmission / reception in the above state, the upper circuit of the device A executes normal data transfer. On the other hand, the following cases are detected as data reception interface errors.

(Case 1) If the check data transmitted from the device A cannot be received in the device B, that is, if it cannot be detected that the most significant bit of the data is “1”, the status of the device B Register 1
Since bit 0 of 15 does not become “1”, the device B does not transmit (cannot) the check data to the device A. For this reason, if the check data is not transmitted from the device B after a certain period of time when the check data has been transmitted from the device A, an interface error in data transmission / reception can be detected by setting an interface error.

(Case 2) In the apparatus B, it is possible to recognize that the check data is being transmitted from the apparatus A (although it is possible to detect that the most significant bit of the data is "1"). If the checked data pattern is not a predetermined one, bit 1 of the status register 115 of the data transmission / reception circuit 103 of the device B becomes “1”. At this time, the higher-level circuit of the device B does not issue an instruction to transmit check data.
For this reason, if the check data is not transmitted from the device B after a certain period of time when the check data has been transmitted from the device A, an interface error in data transmission / reception can be detected by setting an interface error. .

(Case 3) When the check data transmitted from the device B cannot be received in the device A while the check data is transmitted from the device B (it is determined that the most significant bit of the data is "1"). If it cannot be detected), bit 0 of the status register 115 of the device A does not become "1". That is, the device A cannot detect that the check data is being transmitted from the device B. For this reason, if the check data is not transmitted from the device B after a certain period of time when the check data has been transmitted from the device A, an interface error in data transmission / reception can be detected by setting an interface error. .

(Case 4) While the check data is transmitted from the device B, the device A can recognize that the check data transmitted from the device B is transmitted. 1) can be detected), but if the transmitted check data pattern is not a predetermined one, the status register 11 of the data transmission / reception circuit 103 of the device A
Bit 1 of 5 becomes “1”. Therefore, an interface error in data transmission / reception can be detected.

It should be noted that the same applies to the case where data is transmitted from the device A to the device B.

(Effects of First Embodiment) Next, effects of the first embodiment described above will be listed.

First, in the above example, whether or not data transfer can be performed correctly is checked every data transfer, so that the reliability of each data transfer is increased.

Second, a check as to whether or not data transfer can be performed correctly is performed only at the time of initialization of the device, and a check immediately before each data transfer is omitted. Can be achieved.

Third, the memory 105 and the memory 108
The data to be stored in the system is the data of all the patterns used for transmission and reception, and by checking the data transmission and reception, the data transmission and reception of all patterns can be checked. Can be performed.

Fourth, the memory 105 and the memory 108
The data to be stored in the memory is a small number of data patterns that may cause problems in data transmission and reception. By checking data transmission and reception, it is possible to reduce the time required to check transmission and reception. Can be performed at high speed. Further, the capacity of the memory can be reduced, and the cost can be reduced.

For example, in the case of 9-bit parallel data transfer, (10000001), (1,000,000)
10), (100000100), (10000100)
0), (100010000), (10010000)
0), (101,000,000), (110,000,000)
By storing the data pattern 0) in the memory, it is possible to detect whether or not a line corresponding to each bit of the data line of the cable is broken.

[Second Embodiment] (Configuration of Second Embodiment) FIG. 2 is a block diagram showing a configuration of a data transmitting / receiving apparatus according to a second embodiment. This data transmission / reception device is different from the configuration of FIG. 1 described above in that a transmission control unit 104 and a reception control unit 107 of a data transmission / reception circuit 103 are provided.
Instead of the data transmission / reception circuit 201
2. The reception control unit 203 is arranged. Also, the memory 105 and the memory 108 having the same configuration and storing the same data used in the data transmission / reception circuit 103 in FIG. 1 are replaced with one of the memories 204, and two systems output by the transmission control unit 104 and the reception control unit 107 are provided. A memory control signal generation unit 205 that generates one memory control signal from the memory control signal is arranged. Therefore, other components and their functions are the same as those in the first embodiment.
Therefore, the same reference numerals as in FIG. 1 are used and the description thereof is omitted.

(Operation of Embodiment 2) Next, the operation of the data transmission / reception device configured as described above will be described. The transmission control unit 202 outputs a gate signal to the reception control unit 203 during the transmission period of the check data.
Similarly, the reception control unit 203 outputs a gate signal to the transmission control unit 202 during the reception period of the check data.

The transmission control unit 202 is provided with the reception control unit 2
No memory control signal is output while the gate signal is being output from 03. Similarly, when the reception control unit 203 receives the check data while the gate signal is being output from the transmission control unit 202, the reception control unit 203 writes an interface error in the status register 115 and does not output the memory control signal. Therefore, the transmission control unit 202 and the reception control unit 203 do not output the memory control signal at the same time.

The memory control signal generator 205 makes the output signal valid when one of the memory control signals from the transmission controller 202 and the reception controller 203 becomes valid.

(Effects of Second Embodiment) Thus, with such a configuration and operation, one operation of transmitting the check data and receiving the check data can be performed by one memory 204. In addition, the cost and size can be further reduced.

[0052]

As described above, according to the data transmission / reception device of the present invention (claim 1), two memories are used between the control circuit and the data transmission / reception circuit to use the check data and to keep the data constant. Normal data transfer is performed when the normal status is notified from the data transmission / reception circuit within the time, and when an abnormal status is notified, it is determined and processed as an interface error. Check function can be realized,
Data transmission and reception with high reliability can be performed.

According to the data transmission / reception device of the present invention (claim 2), the check data is used between the control circuit and the data transmission / reception circuit by using one memory, and the data transmission / reception circuit is provided within a predetermined time. A normal data transfer is executed when a normal status is notified from the server. When an abnormal status is notified, it is determined and processed as an interface error. As a result, highly reliable data transmission and reception can be performed, and furthermore, improvement in economy and downsizing can be achieved.

According to the data transmitting / receiving apparatus of the present invention (claim 3), each time immediately before transmitting / receiving data,
Since it is confirmed whether data transmission / reception can be performed normally, reliable data transfer is realized, and highly reliable data transmission / reception can be performed.

According to the data transmission / reception device of the present invention (claim 4), it is checked whether data transmission / reception can be performed at the time of initialization of the device. Becomes possible.

According to the data transmission / reception device of the present invention (claim 5), it is necessary to check whether data transmission / reception can be performed normally for all data patterns used for data transmission / reception. Data transmission and reception with high reliability can be performed.

According to the data transmission / reception device of the present invention (claim 6), it is determined whether or not data transmission / reception can be performed normally, by checking only a data pattern which is likely to cause a problem, that is, a data pattern to be checked. Since the data is stored in the memory and checked, high-reliability and high-speed data transmission / reception can be performed, and the economic efficiency is improved by reducing the memory capacity.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data transmitting / receiving apparatus according to Embodiment 1.

FIG. 2 is a block diagram showing a configuration of a data transmitting / receiving device according to a second embodiment.

[Explanation of symbols]

 101, 201 Data transmission / reception device 102 Control circuit 103 Data transmission / reception circuit 104, 202 Transmission control unit 105, 108, 204 Memory 107, 203 Reception control unit 106 Selector 109 Register 110 Comparator 111 Command register 112 Line driver 113 Line receiver 115 Status register

Claims (6)

[Claims] 1. A data transmission / reception device including a control circuit and a data transmission / reception circuit for transmitting / receiving data to / from an external device, wherein the data transmission / reception circuit holds a command output by the control circuit. A register, a transmission control unit that executes data transmission control based on a data holding state of the command register, and a first unit that stores check data and outputs data based on a control signal output by the transmission control unit. A selector for selecting and outputting one of transmission data output by the control circuit and data output by the first memory based on a select signal output by the transmission control unit; A line driver for transmitting the data output by the external device to the external device; A line receiver for receiving data from an external device, a register for temporarily holding data output by the line receiver, a reception control unit for executing reception control based on the data output by the line receiver, 1 stores the same data as the memory,
A second memory that outputs data based on a control signal output by the reception control unit, a comparator that compares and outputs data output by the register and the second memory, an output of the comparator, A status register in which the status created by the reception control unit is written from the output data of the line receiver, wherein the control circuit outputs the check data transmission command to the data transmission / reception circuit before receiving the data. Then, transmission of the check data is instructed, normal data transfer is executed when a normal status is notified from the data transmission / reception circuit within a fixed time, and an interface error occurs when an abnormal status is notified. A data transmission / reception device, which determines and processes the data. 2. A data transmission / reception device comprising a control circuit and a data transmission / reception circuit for transmitting / receiving data to / from an external device, wherein the data transmission / reception circuit holds a command output by the control circuit. A register, a transmission control unit that performs data transmission control based on a data holding state of the command register, a line receiver that receives data from the external device, and a reception unit that receives data based on data output by the line receiver. A reception control unit for performing control, a memory control signal generating means for generating a memory control signal from a control signal output from the transmission control unit and a control signal output from the reception control unit, and storing check data Outputting data based on a control signal output by the memory control signal generating means. A selector for selecting and outputting one of transmission data output by the control unit and data output by the memory based on a select signal output by the transmission control unit; A line driver for transmitting data to the external device, a register for temporarily storing data output by the line driver, a comparator for comparing and outputting data output from the register and the memory, and an output of the comparator. And a status register in which the status created by the reception control unit is written from the output data of the line receiver, wherein the control circuit transmits the check data transmission command to the data transmission / reception circuit before receiving the data. And send the check data The normal data transfer is executed when a normal status is notified from the data transmission / reception circuit within a predetermined time, and when an abnormal status is notified, it is determined and processed as an interface error. Data transmitting and receiving device. 3. The data transmitting / receiving apparatus according to claim 1, wherein the control circuit executes an interface check every time immediately before performing data transmission. 4. The data transmission / reception device according to claim 1, wherein the control circuit executes an interface check when the device is initialized. 5. The data transmission / reception according to claim 1, wherein the first and second memories or the check data stored in the memories are all test patterns used for transmission / reception. apparatus. 6. The method according to claim 1, wherein the first and second memories or the check data stored in the memories is a test pattern that has a high possibility of causing a problem in data transmission and reception. The data transmission / reception device according to the above.